From 2cd690ea6d6b345265f2de8c40e4a003ed802002 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Thu, 3 Nov 2016 11:38:52 -0700 Subject: ARC: timer: gfrc, rtc: deuglify big endian code A standard "C" shift will be handled appropriately by the compiler depending on the endian for the build. So we don't need the explicit distinction in code Signed-off-by: Vineet Gupta --- arch/arc/kernel/time.c | 30 ++++++++---------------------- 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index c10390d1ddb6..8d66bb446209 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -86,26 +86,19 @@ static int noinline arc_get_timer_clk(struct device_node *node) static cycle_t arc_read_gfrc(struct clocksource *cs) { unsigned long flags; - union { -#ifdef CONFIG_CPU_BIG_ENDIAN - struct { u32 h, l; }; -#else - struct { u32 l, h; }; -#endif - cycle_t full; - } stamp; + u32 l, h; local_irq_save(flags); __mcip_cmd(CMD_GFRC_READ_LO, 0); - stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK); + l = read_aux_reg(ARC_REG_MCIP_READBACK); __mcip_cmd(CMD_GFRC_READ_HI, 0); - stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK); + h = read_aux_reg(ARC_REG_MCIP_READBACK); local_irq_restore(flags); - return stamp.full; + return (((cycle_t)h) << 32) | l; } static struct clocksource arc_counter_gfrc = { @@ -143,14 +136,7 @@ CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); static cycle_t arc_read_rtc(struct clocksource *cs) { unsigned long status; - union { -#ifdef CONFIG_CPU_BIG_ENDIAN - struct { u32 high, low; }; -#else - struct { u32 low, high; }; -#endif - cycle_t full; - } stamp; + u32 l, h; /* * hardware has an internal state machine which tracks readout of @@ -159,12 +145,12 @@ static cycle_t arc_read_rtc(struct clocksource *cs) * - high increments after low has been read */ do { - stamp.low = read_aux_reg(AUX_RTC_LOW); - stamp.high = read_aux_reg(AUX_RTC_HIGH); + l = read_aux_reg(AUX_RTC_LOW); + h = read_aux_reg(AUX_RTC_HIGH); status = read_aux_reg(AUX_RTC_CTRL); } while (!(status & _BITUL(31))); - return stamp.full; + return (((cycle_t)h) << 32) | l; } static struct clocksource arc_counter_rtc = { -- cgit v1.2.3 From ec7cb87bf998448471d1ff735abf156211da0874 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 31 Oct 2016 13:02:31 -0700 Subject: ARC: timer: gfrc, rtc: Read BCR to detect whether hardware exists ... ... don't rely on cpuinfo populated in arc boot code. This paves way for moving this code in drivers/clocksource/ And while at it, convert the WARN() to pr_warn() as sugested by Daniel Signed-off-by: Vineet Gupta --- arch/arc/kernel/time.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index 8d66bb446209..d3f3750a0d2d 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -111,11 +111,14 @@ static struct clocksource arc_counter_gfrc = { static int __init arc_cs_setup_gfrc(struct device_node *node) { - int exists = cpuinfo_arc700[0].extn.gfrc; + struct mcip_bcr mp; int ret; - if (WARN(!exists, "Global-64-bit-Ctr clocksource not detected")) + READ_BCR(ARC_REG_MCIP_BCR, mp); + if (!mp.gfrc) { + pr_warn("Global-64-bit-Ctr clocksource not detected"); return -ENXIO; + } ret = arc_get_timer_clk(node); if (ret) @@ -163,15 +166,20 @@ static struct clocksource arc_counter_rtc = { static int __init arc_cs_setup_rtc(struct device_node *node) { - int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc; + struct bcr_timer timer; int ret; - if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected")) + READ_BCR(ARC_REG_TIMERS_BCR, timer); + if (!timer.rtc) { + pr_warn("Local-64-bit-Ctr clocksource not detected"); return -ENXIO; + } /* Local to CPU hence not usable in SMP */ - if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP")) + if (IS_ENABLED(CONFIG_SMP)) { + pr_warn("Local-64-bit-Ctr not usable in SMP"); return -EINVAL; + } ret = arc_get_timer_clk(node); if (ret) -- cgit v1.2.3 From 044214200b0b7aa4633d2e93529e55b5ca50a5a5 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 31 Oct 2016 14:26:41 -0700 Subject: ARC: timer: gfrc, rtc: build under same option (64-bit timers) The original distinction was done as they were developed at different times and primarily because they are specific to UP (RTC) and SMP (GFRC). But given that driver handles that at runtime, (i.e. not allowing RTC as clocksource in SMP), we can simplify things a bit. Signed-off-by: Vineet Gupta --- arch/arc/Kconfig | 10 ++-------- arch/arc/configs/nsimosci_hs_smp_defconfig | 2 +- arch/arc/configs/vdk_hs38_smp_defconfig | 2 +- arch/arc/kernel/setup.c | 6 +++--- arch/arc/kernel/time.c | 6 +----- 5 files changed, 8 insertions(+), 18 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index bd204bfa29ed..bde3e558d8bc 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -410,15 +410,9 @@ config ARC_HAS_DIV_REM bool "Insn: div, divu, rem, remu" default y -config ARC_HAS_RTC - bool "Local 64-bit r/o cycle counter" - default n - depends on !SMP - -config ARC_HAS_GFRC - bool "SMP synchronized 64-bit cycle counter" +config ARC_TIMERS_64BIT + bool "64-bit r/o cycle counters RTC (up) and GFRC (smp)" default y - depends on SMP config ARC_NUMBER_OF_INTERRUPTS int "Number of interrupts" diff --git a/arch/arc/configs/nsimosci_hs_smp_defconfig b/arch/arc/configs/nsimosci_hs_smp_defconfig index 6da71ba253a9..155add7761ed 100644 --- a/arch/arc/configs/nsimosci_hs_smp_defconfig +++ b/arch/arc/configs/nsimosci_hs_smp_defconfig @@ -21,7 +21,7 @@ CONFIG_MODULES=y CONFIG_ARC_PLAT_SIM=y CONFIG_ISA_ARCV2=y CONFIG_SMP=y -# CONFIG_ARC_HAS_GFRC is not set +# CONFIG_ARC_TIMERS_64BIT is not set CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs_idu" CONFIG_PREEMPT=y # CONFIG_COMPACTION is not set diff --git a/arch/arc/configs/vdk_hs38_smp_defconfig b/arch/arc/configs/vdk_hs38_smp_defconfig index 969b206d6c67..573028f19de7 100644 --- a/arch/arc/configs/vdk_hs38_smp_defconfig +++ b/arch/arc/configs/vdk_hs38_smp_defconfig @@ -15,7 +15,7 @@ CONFIG_ARC_PLAT_AXS10X=y CONFIG_AXS103=y CONFIG_ISA_ARCV2=y CONFIG_SMP=y -# CONFIG_ARC_HAS_GFRC is not set +# CONFIG_ARC_TIMERS_64BIT is not set CONFIG_ARC_UBOOT_SUPPORT=y CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp" CONFIG_PREEMPT=y diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 0385df77a697..c6914acb68a9 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -234,11 +234,11 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) is_isa_arcompact() ? "ARCompact" : "ARCv2", IS_AVAIL1(cpu->isa.be, "[Big-Endian]")); - n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ", + n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", IS_AVAIL1(cpu->extn.timer0, "Timer0 "), IS_AVAIL1(cpu->extn.timer1, "Timer1 "), - IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ", - CONFIG_ARC_HAS_RTC)); + IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), + IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s", IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index d3f3750a0d2d..4d0c75b86b10 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -81,7 +81,7 @@ static int noinline arc_get_timer_clk(struct device_node *node) /********** Clock Source Device *********/ -#ifdef CONFIG_ARC_HAS_GFRC +#ifdef CONFIG_ARC_TIMERS_64BIT static cycle_t arc_read_gfrc(struct clocksource *cs) { @@ -128,10 +128,6 @@ static int __init arc_cs_setup_gfrc(struct device_node *node) } CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); -#endif - -#ifdef CONFIG_ARC_HAS_RTC - #define AUX_RTC_CTRL 0x103 #define AUX_RTC_LOW 0x104 #define AUX_RTC_HIGH 0x105 -- cgit v1.2.3 From 92b03314033c0d36ef3a5e68ccdc65ad2a4d17c5 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 31 Oct 2016 13:26:25 -0700 Subject: ARC: time: move time_init() out of the driver to allow future git mv of the driver into drivers/clocksource Acked-by: Daniel Lezcano Signed-off-by: Vineet Gupta --- arch/arc/kernel/setup.c | 11 +++++++++++ arch/arc/kernel/time.c | 9 --------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index c6914acb68a9..3093fa898a23 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include #include @@ -449,6 +451,15 @@ void __init setup_arch(char **cmdline_p) arc_unwind_init(); } +/* + * Called from start_kernel() - boot CPU only + */ +void __init time_init(void) +{ + of_clk_init(NULL); + clocksource_probe(); +} + static int __init customize_machine(void) { if (machine_desc->init_machine) diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index 4d0c75b86b10..417d32e031d3 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -361,12 +361,3 @@ static int __init arc_of_timer_init(struct device_node *np) return ret; } CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init); - -/* - * Called from start_kernel() - boot CPU only - */ -void __init time_init(void) -{ - of_clk_init(NULL); - clocksource_probe(); -} -- cgit v1.2.3 From c33a605dd6f36618f9f658e71c09fcdcb44fc500 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 31 Oct 2016 11:09:34 -0700 Subject: ARC: breakout aux handling into a separate header ARC timers use aux registers for programming and this paves way for moving ARC timer drivers into drivers/clocksource Signed-off-by: Vineet Gupta --- arch/arc/include/asm/arcregs.h | 85 +----------------------------------------- arch/arc/include/asm/mcip.h | 2 +- include/soc/arc/aux.h | 63 +++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 85 deletions(-) create mode 100644 include/soc/arc/aux.h diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 1bd24ec3e350..7a2c36e83186 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -112,90 +112,7 @@ #ifndef __ASSEMBLY__ -/* - ****************************************************************** - * Inline ASM macros to read/write AUX Regs - * Essentially invocation of lr/sr insns from "C" - */ - -#if 1 - -#define read_aux_reg(reg) __builtin_arc_lr(reg) - -/* gcc builtin sr needs reg param to be long immediate */ -#define write_aux_reg(reg_immed, val) \ - __builtin_arc_sr((unsigned int)(val), reg_immed) - -#else - -#define read_aux_reg(reg) \ -({ \ - unsigned int __ret; \ - __asm__ __volatile__( \ - " lr %0, [%1]" \ - : "=r"(__ret) \ - : "i"(reg)); \ - __ret; \ -}) - -/* - * Aux Reg address is specified as long immediate by caller - * e.g. - * write_aux_reg(0x69, some_val); - * This generates tightest code. - */ -#define write_aux_reg(reg_imm, val) \ -({ \ - __asm__ __volatile__( \ - " sr %0, [%1] \n" \ - : \ - : "ir"(val), "i"(reg_imm)); \ -}) - -/* - * Aux Reg address is specified in a variable - * * e.g. - * reg_num = 0x69 - * write_aux_reg2(reg_num, some_val); - * This has to generate glue code to load the reg num from - * memory to a reg hence not recommended. - */ -#define write_aux_reg2(reg_in_var, val) \ -({ \ - unsigned int tmp; \ - \ - __asm__ __volatile__( \ - " ld %0, [%2] \n\t" \ - " sr %1, [%0] \n\t" \ - : "=&r"(tmp) \ - : "r"(val), "memory"(®_in_var)); \ -}) - -#endif - -#define READ_BCR(reg, into) \ -{ \ - unsigned int tmp; \ - tmp = read_aux_reg(reg); \ - if (sizeof(tmp) == sizeof(into)) { \ - into = *((typeof(into) *)&tmp); \ - } else { \ - extern void bogus_undefined(void); \ - bogus_undefined(); \ - } \ -} - -#define WRITE_AUX(reg, into) \ -{ \ - unsigned int tmp; \ - if (sizeof(tmp) == sizeof(into)) { \ - tmp = (*(unsigned int *)&(into)); \ - write_aux_reg(reg, tmp); \ - } else { \ - extern void bogus_undefined(void); \ - bogus_undefined(); \ - } \ -} +#include /* Helpers */ #define TO_KB(bytes) ((bytes) >> 10) diff --git a/arch/arc/include/asm/mcip.h b/arch/arc/include/asm/mcip.h index c8fbe4114bad..fc28d0944801 100644 --- a/arch/arc/include/asm/mcip.h +++ b/arch/arc/include/asm/mcip.h @@ -13,7 +13,7 @@ #ifdef CONFIG_ISA_ARCV2 -#include +#include #define ARC_REG_MCIP_BCR 0x0d0 #define ARC_REG_MCIP_CMD 0x600 diff --git a/include/soc/arc/aux.h b/include/soc/arc/aux.h new file mode 100644 index 000000000000..8c3fb13e0452 --- /dev/null +++ b/include/soc/arc/aux.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2016-2017 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __SOC_ARC_AUX_H__ +#define __SOC_ARC_AUX_H__ + +#ifdef CONFIG_ARC + +#define read_aux_reg(r) __builtin_arc_lr(r) + +/* gcc builtin sr needs reg param to be long immediate */ +#define write_aux_reg(r, v) __builtin_arc_sr((unsigned int)(v), r) + +#else /* !CONFIG_ARC */ + +static inline int read_aux_reg(u32 r) +{ + return 0; +} + +/* + * function helps elide unused variable warning + * see: http://lists.infradead.org/pipermail/linux-snps-arc/2016-November/001748.html + */ +static inline void write_aux_reg(u32 r, u32 v) +{ + ; +} + +#endif + +#define READ_BCR(reg, into) \ +{ \ + unsigned int tmp; \ + tmp = read_aux_reg(reg); \ + if (sizeof(tmp) == sizeof(into)) { \ + into = *((typeof(into) *)&tmp); \ + } else { \ + extern void bogus_undefined(void); \ + bogus_undefined(); \ + } \ +} + +#define WRITE_AUX(reg, into) \ +{ \ + unsigned int tmp; \ + if (sizeof(tmp) == sizeof(into)) { \ + tmp = (*(unsigned int *)&(into)); \ + write_aux_reg(reg, tmp); \ + } else { \ + extern void bogus_undefined(void); \ + bogus_undefined(); \ + } \ +} + + +#endif -- cgit v1.2.3 From 2d7f5c48c03ee53ad649cbf803dc33730f955234 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 31 Oct 2016 11:27:08 -0700 Subject: ARC: move mcip.h into include/soc and adjust the includes Also remove the dependency on ARCv2, to increase compile coverage for !ARCV2 builds Acked-by: Daniel Lezcano Signed-off-by: Vineet Gupta --- arch/arc/include/asm/mcip.h | 107 ------------------------------------------ arch/arc/kernel/mcip.c | 2 +- arch/arc/kernel/time.c | 2 +- arch/arc/plat-axs10x/axs10x.c | 2 +- include/soc/arc/mcip.h | 103 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 106 insertions(+), 110 deletions(-) delete mode 100644 arch/arc/include/asm/mcip.h create mode 100644 include/soc/arc/mcip.h diff --git a/arch/arc/include/asm/mcip.h b/arch/arc/include/asm/mcip.h deleted file mode 100644 index fc28d0944801..000000000000 --- a/arch/arc/include/asm/mcip.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...) - * - * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_MCIP_H -#define __ASM_MCIP_H - -#ifdef CONFIG_ISA_ARCV2 - -#include - -#define ARC_REG_MCIP_BCR 0x0d0 -#define ARC_REG_MCIP_CMD 0x600 -#define ARC_REG_MCIP_WDATA 0x601 -#define ARC_REG_MCIP_READBACK 0x602 - -struct mcip_cmd { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:8, param:16, cmd:8; -#else - unsigned int cmd:8, param:16, pad:8; -#endif - -#define CMD_INTRPT_GENERATE_IRQ 0x01 -#define CMD_INTRPT_GENERATE_ACK 0x02 -#define CMD_INTRPT_READ_STATUS 0x03 -#define CMD_INTRPT_CHECK_SOURCE 0x04 - -/* Semaphore Commands */ -#define CMD_SEMA_CLAIM_AND_READ 0x11 -#define CMD_SEMA_RELEASE 0x12 - -#define CMD_DEBUG_SET_MASK 0x34 -#define CMD_DEBUG_SET_SELECT 0x36 - -#define CMD_GFRC_READ_LO 0x42 -#define CMD_GFRC_READ_HI 0x43 - -#define CMD_IDU_ENABLE 0x71 -#define CMD_IDU_DISABLE 0x72 -#define CMD_IDU_SET_MODE 0x74 -#define CMD_IDU_SET_DEST 0x76 -#define CMD_IDU_SET_MASK 0x7C - -#define IDU_M_TRIG_LEVEL 0x0 -#define IDU_M_TRIG_EDGE 0x1 - -#define IDU_M_DISTRI_RR 0x0 -#define IDU_M_DISTRI_DEST 0x2 -}; - -struct mcip_bcr { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad3:8, - idu:1, llm:1, num_cores:6, - iocoh:1, gfrc:1, dbg:1, pad2:1, - msg:1, sem:1, ipi:1, pad:1, - ver:8; -#else - unsigned int ver:8, - pad:1, ipi:1, sem:1, msg:1, - pad2:1, dbg:1, gfrc:1, iocoh:1, - num_cores:6, llm:1, idu:1, - pad3:8; -#endif -}; - -/* - * MCIP programming model - * - * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg - * (param could be irq, common_irq, core_id ...) - * - More involved commands setup MCIP_WDATA with cmd specific data - * before invoking the simple command - */ -static inline void __mcip_cmd(unsigned int cmd, unsigned int param) -{ - struct mcip_cmd buf; - - buf.pad = 0; - buf.cmd = cmd; - buf.param = param; - - WRITE_AUX(ARC_REG_MCIP_CMD, buf); -} - -/* - * Setup additional data for a cmd - * Callers need to lock to ensure atomicity - */ -static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param, - unsigned int data) -{ - write_aux_reg(ARC_REG_MCIP_WDATA, data); - - __mcip_cmd(cmd, param); -} - -#endif - -#endif diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c index f39142acc89e..560c4afc2af4 100644 --- a/arch/arc/kernel/mcip.c +++ b/arch/arc/kernel/mcip.c @@ -11,8 +11,8 @@ #include #include #include +#include #include -#include #include static DEFINE_RAW_SPINLOCK(mcip_lock); diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index 417d32e031d3..ec1b896f27b2 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -40,7 +40,7 @@ #include #include -#include +#include /* Timer related Aux registers */ #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index 86548701023c..38ff349d7f2a 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #define AXS_MB_CGU 0xE0010000 #define AXS_MB_CREG 0xE0011000 diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h new file mode 100644 index 000000000000..6902c2a8bd23 --- /dev/null +++ b/include/soc/arc/mcip.h @@ -0,0 +1,103 @@ +/* + * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...) + * + * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SOC_ARC_MCIP_H +#define __SOC_ARC_MCIP_H + +#include + +#define ARC_REG_MCIP_BCR 0x0d0 +#define ARC_REG_MCIP_CMD 0x600 +#define ARC_REG_MCIP_WDATA 0x601 +#define ARC_REG_MCIP_READBACK 0x602 + +struct mcip_cmd { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:8, param:16, cmd:8; +#else + unsigned int cmd:8, param:16, pad:8; +#endif + +#define CMD_INTRPT_GENERATE_IRQ 0x01 +#define CMD_INTRPT_GENERATE_ACK 0x02 +#define CMD_INTRPT_READ_STATUS 0x03 +#define CMD_INTRPT_CHECK_SOURCE 0x04 + +/* Semaphore Commands */ +#define CMD_SEMA_CLAIM_AND_READ 0x11 +#define CMD_SEMA_RELEASE 0x12 + +#define CMD_DEBUG_SET_MASK 0x34 +#define CMD_DEBUG_SET_SELECT 0x36 + +#define CMD_GFRC_READ_LO 0x42 +#define CMD_GFRC_READ_HI 0x43 + +#define CMD_IDU_ENABLE 0x71 +#define CMD_IDU_DISABLE 0x72 +#define CMD_IDU_SET_MODE 0x74 +#define CMD_IDU_SET_DEST 0x76 +#define CMD_IDU_SET_MASK 0x7C + +#define IDU_M_TRIG_LEVEL 0x0 +#define IDU_M_TRIG_EDGE 0x1 + +#define IDU_M_DISTRI_RR 0x0 +#define IDU_M_DISTRI_DEST 0x2 +}; + +struct mcip_bcr { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad3:8, + idu:1, llm:1, num_cores:6, + iocoh:1, gfrc:1, dbg:1, pad2:1, + msg:1, sem:1, ipi:1, pad:1, + ver:8; +#else + unsigned int ver:8, + pad:1, ipi:1, sem:1, msg:1, + pad2:1, dbg:1, gfrc:1, iocoh:1, + num_cores:6, llm:1, idu:1, + pad3:8; +#endif +}; + +/* + * MCIP programming model + * + * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg + * (param could be irq, common_irq, core_id ...) + * - More involved commands setup MCIP_WDATA with cmd specific data + * before invoking the simple command + */ +static inline void __mcip_cmd(unsigned int cmd, unsigned int param) +{ + struct mcip_cmd buf; + + buf.pad = 0; + buf.cmd = cmd; + buf.param = param; + + WRITE_AUX(ARC_REG_MCIP_CMD, buf); +} + +/* + * Setup additional data for a cmd + * Callers need to lock to ensure atomicity + */ +static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param, + unsigned int data) +{ + write_aux_reg(ARC_REG_MCIP_WDATA, data); + + __mcip_cmd(cmd, param); +} + +#endif -- cgit v1.2.3 From b26c2e3823bae6ba43a2b263d9bb75a3efd39b6a Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 31 Oct 2016 13:06:19 -0700 Subject: ARC: breakout timer include code into separate header ... ... which allows for use in drivers/clocksource later Signed-off-by: Vineet Gupta --- arch/arc/include/asm/arcregs.h | 9 +-------- arch/arc/kernel/time.c | 18 +++--------------- include/soc/arc/timers.h | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 23 deletions(-) create mode 100644 include/soc/arc/timers.h diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 7a2c36e83186..da41a54ea2d7 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -20,7 +20,6 @@ #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ #define ARC_REG_SLC_BCR 0xce #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */ -#define ARC_REG_TIMERS_BCR 0x75 #define ARC_REG_AP_BCR 0x76 #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */ #define ARC_REG_XY_MEM_BCR 0x79 @@ -208,13 +207,7 @@ struct bcr_fp_arcv2 { #endif }; -struct bcr_timer { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; -#else - unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; -#endif -}; +#include struct bcr_bpu_arcompact { #ifdef CONFIG_CPU_BIG_ENDIAN diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index ec1b896f27b2..94b9cd169374 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -38,22 +38,10 @@ #include #include #include -#include +#include #include -/* Timer related Aux registers */ -#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ -#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ -#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ -#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ -#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ -#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ - -#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ -#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ - -#define ARC_TIMER_MAX 0xFFFFFFFF static unsigned long arc_timer_freq; @@ -218,7 +206,7 @@ static int __init arc_cs_setup_timer1(struct device_node *node) if (ret) return ret; - write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); + write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); write_aux_reg(ARC_REG_TIMER1_CNT, 0); write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); @@ -296,7 +284,7 @@ static int arc_timer_starting_cpu(unsigned int cpu) evt->cpumask = cpumask_of(smp_processor_id()); - clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMER_MAX); + clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX); enable_percpu_irq(arc_timer_irq, 0); return 0; } diff --git a/include/soc/arc/timers.h b/include/soc/arc/timers.h new file mode 100644 index 000000000000..a20ed2fbc432 --- /dev/null +++ b/include/soc/arc/timers.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SOC_ARC_TIMERS_H +#define __SOC_ARC_TIMERS_H + +#include + +/* Timer related Aux registers */ +#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ +#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ +#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ +#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ +#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ +#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ + +/* CTRL reg bits */ +#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ +#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ + +#define ARC_TIMERN_MAX 0xFFFFFFFF + +#define ARC_REG_TIMERS_BCR 0x75 + +struct bcr_timer { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; +#else + unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; +#endif +}; + +#endif -- cgit v1.2.3 From c4c9a040ecb7297e011e579f5a9cc280e42d725f Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 31 Oct 2016 13:46:38 -0700 Subject: clocksource: import ARC timer driver This adds support for - CONFIG_ARC_TIMERS : legacy 32-bit TIMER0 and TIMER1 which count UP from @CNT to @LIMIT, before optionally triggering an interrupt. These are programmed using ARC auxiliary register interface. These are present in all ARC cores (ARC700 and ARC HS38) TIMER0 serves as clockevent for all ARC linux builds. TIMER1 is used for clocksource in arc700 builds. - CONFIG_ARC_TIMERS_64BIT: 64-bit counters, RTC and GFRC found in ARC HS38 cores. These are independnet IP blocks with different programming model respectively. Link: http://lkml.kernel.org/r/20161111231132.GA4186@mai Acked-by: Daniel Lezcano Signed-off-by: Vineet Gupta --- MAINTAINERS | 1 + arch/arc/Kconfig | 7 +- arch/arc/kernel/Makefile | 2 +- arch/arc/kernel/time.c | 351 ---------------------------------------- drivers/clocksource/Kconfig | 20 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/arc_timer.c | 336 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 361 insertions(+), 357 deletions(-) delete mode 100644 arch/arc/kernel/time.c create mode 100644 drivers/clocksource/arc_timer.c diff --git a/MAINTAINERS b/MAINTAINERS index 8d4148406923..34160a2dd131 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11662,6 +11662,7 @@ S: Supported F: arch/arc/ F: Documentation/devicetree/bindings/arc/* F: Documentation/devicetree/bindings/interrupt-controller/snps,arc* +F: drivers/clocksource/arc_timer.c F: drivers/tty/serial/arc_uart.c T: git git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index bde3e558d8bc..ab12723d39a0 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -8,9 +8,9 @@ config ARC def_bool y + select ARC_TIMERS select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC select BUILDTIME_EXTABLE_SORT - select CLKSRC_OF select CLONE_BACKWARDS select COMMON_CLK select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) @@ -115,6 +115,7 @@ config ISA_ARCOMPACT config ISA_ARCV2 bool "ARC ISA v2" + select ARC_TIMERS_64BIT help ISA for the Next Generation ARC-HS cores @@ -410,10 +411,6 @@ config ARC_HAS_DIV_REM bool "Insn: div, divu, rem, remu" default y -config ARC_TIMERS_64BIT - bool "64-bit r/o cycle counters RTC (up) and GFRC (smp)" - default y - config ARC_NUMBER_OF_INTERRUPTS int "Number of interrupts" range 8 240 diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile index cfcdedf52ff8..8942c5c3b4c5 100644 --- a/arch/arc/kernel/Makefile +++ b/arch/arc/kernel/Makefile @@ -8,7 +8,7 @@ # Pass UTS_MACHINE for user_regset definition CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"' -obj-y := arcksyms.o setup.o irq.o time.o reset.o ptrace.o process.o devtree.o +obj-y := arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c deleted file mode 100644 index 94b9cd169374..000000000000 --- a/arch/arc/kernel/time.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * vineetg: Jan 1011 - * -sched_clock( ) no longer jiffies based. Uses the same clocksource - * as gtod - * - * Rajeshwarr/Vineetg: Mar 2008 - * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code) - * for arch independent gettimeofday() - * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers - * - * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c - */ - -/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1 - * Each can programmed to go from @count to @limit and optionally - * interrupt when that happens. - * A write to Control Register clears the Interrupt - * - * We've designated TIMER0 for events (clockevents) - * while TIMER1 for free running (clocksource) - * - * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1 - * which however is currently broken - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - - -static unsigned long arc_timer_freq; - -static int noinline arc_get_timer_clk(struct device_node *node) -{ - struct clk *clk; - int ret; - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("timer missing clk"); - return PTR_ERR(clk); - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("Couldn't enable parent clk\n"); - return ret; - } - - arc_timer_freq = clk_get_rate(clk); - - return 0; -} - -/********** Clock Source Device *********/ - -#ifdef CONFIG_ARC_TIMERS_64BIT - -static cycle_t arc_read_gfrc(struct clocksource *cs) -{ - unsigned long flags; - u32 l, h; - - local_irq_save(flags); - - __mcip_cmd(CMD_GFRC_READ_LO, 0); - l = read_aux_reg(ARC_REG_MCIP_READBACK); - - __mcip_cmd(CMD_GFRC_READ_HI, 0); - h = read_aux_reg(ARC_REG_MCIP_READBACK); - - local_irq_restore(flags); - - return (((cycle_t)h) << 32) | l; -} - -static struct clocksource arc_counter_gfrc = { - .name = "ARConnect GFRC", - .rating = 400, - .read = arc_read_gfrc, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int __init arc_cs_setup_gfrc(struct device_node *node) -{ - struct mcip_bcr mp; - int ret; - - READ_BCR(ARC_REG_MCIP_BCR, mp); - if (!mp.gfrc) { - pr_warn("Global-64-bit-Ctr clocksource not detected"); - return -ENXIO; - } - - ret = arc_get_timer_clk(node); - if (ret) - return ret; - - return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); -} -CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); - -#define AUX_RTC_CTRL 0x103 -#define AUX_RTC_LOW 0x104 -#define AUX_RTC_HIGH 0x105 - -static cycle_t arc_read_rtc(struct clocksource *cs) -{ - unsigned long status; - u32 l, h; - - /* - * hardware has an internal state machine which tracks readout of - * low/high and updates the CTRL.status if - * - interrupt/exception taken between the two reads - * - high increments after low has been read - */ - do { - l = read_aux_reg(AUX_RTC_LOW); - h = read_aux_reg(AUX_RTC_HIGH); - status = read_aux_reg(AUX_RTC_CTRL); - } while (!(status & _BITUL(31))); - - return (((cycle_t)h) << 32) | l; -} - -static struct clocksource arc_counter_rtc = { - .name = "ARCv2 RTC", - .rating = 350, - .read = arc_read_rtc, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int __init arc_cs_setup_rtc(struct device_node *node) -{ - struct bcr_timer timer; - int ret; - - READ_BCR(ARC_REG_TIMERS_BCR, timer); - if (!timer.rtc) { - pr_warn("Local-64-bit-Ctr clocksource not detected"); - return -ENXIO; - } - - /* Local to CPU hence not usable in SMP */ - if (IS_ENABLED(CONFIG_SMP)) { - pr_warn("Local-64-bit-Ctr not usable in SMP"); - return -EINVAL; - } - - ret = arc_get_timer_clk(node); - if (ret) - return ret; - - write_aux_reg(AUX_RTC_CTRL, 1); - - return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); -} -CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); - -#endif - -/* - * 32bit TIMER1 to keep counting monotonically and wraparound - */ - -static cycle_t arc_read_timer1(struct clocksource *cs) -{ - return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); -} - -static struct clocksource arc_counter_timer1 = { - .name = "ARC Timer1", - .rating = 300, - .read = arc_read_timer1, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int __init arc_cs_setup_timer1(struct device_node *node) -{ - int ret; - - /* Local to CPU hence not usable in SMP */ - if (IS_ENABLED(CONFIG_SMP)) - return -EINVAL; - - ret = arc_get_timer_clk(node); - if (ret) - return ret; - - write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); - write_aux_reg(ARC_REG_TIMER1_CNT, 0); - write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); - - return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq); -} - -/********** Clock Event Device *********/ - -static int arc_timer_irq; - -/* - * Arm the timer to interrupt after @cycles - * The distinction for oneshot/periodic is done in arc_event_timer_ack() below - */ -static void arc_timer_event_setup(unsigned int cycles) -{ - write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); - write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ - - write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); -} - - -static int arc_clkevent_set_next_event(unsigned long delta, - struct clock_event_device *dev) -{ - arc_timer_event_setup(delta); - return 0; -} - -static int arc_clkevent_set_periodic(struct clock_event_device *dev) -{ - /* - * At X Hz, 1 sec = 1000ms -> X cycles; - * 10ms -> X / 100 cycles - */ - arc_timer_event_setup(arc_timer_freq / HZ); - return 0; -} - -static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { - .name = "ARC Timer0", - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC, - .rating = 300, - .set_next_event = arc_clkevent_set_next_event, - .set_state_periodic = arc_clkevent_set_periodic, -}; - -static irqreturn_t timer_irq_handler(int irq, void *dev_id) -{ - /* - * Note that generic IRQ core could have passed @evt for @dev_id if - * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() - */ - struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); - int irq_reenable = clockevent_state_periodic(evt); - - /* - * Any write to CTRL reg ACks the interrupt, we rewrite the - * Count when [N]ot [H]alted bit. - * And re-arm it if perioid by [I]nterrupt [E]nable bit - */ - write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - - -static int arc_timer_starting_cpu(unsigned int cpu) -{ - struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); - - evt->cpumask = cpumask_of(smp_processor_id()); - - clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX); - enable_percpu_irq(arc_timer_irq, 0); - return 0; -} - -static int arc_timer_dying_cpu(unsigned int cpu) -{ - disable_percpu_irq(arc_timer_irq); - return 0; -} - -/* - * clockevent setup for boot CPU - */ -static int __init arc_clockevent_setup(struct device_node *node) -{ - struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); - int ret; - - arc_timer_irq = irq_of_parse_and_map(node, 0); - if (arc_timer_irq <= 0) { - pr_err("clockevent: missing irq"); - return -EINVAL; - } - - ret = arc_get_timer_clk(node); - if (ret) { - pr_err("clockevent: missing clk"); - return ret; - } - - /* Needs apriori irq_set_percpu_devid() done in intc map function */ - ret = request_percpu_irq(arc_timer_irq, timer_irq_handler, - "Timer0 (per-cpu-tick)", evt); - if (ret) { - pr_err("clockevent: unable to request irq\n"); - return ret; - } - - ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING, - "AP_ARC_TIMER_STARTING", - arc_timer_starting_cpu, - arc_timer_dying_cpu); - if (ret) { - pr_err("Failed to setup hotplug state"); - return ret; - } - return 0; -} - -static int __init arc_of_timer_init(struct device_node *np) -{ - static int init_count = 0; - int ret; - - if (!init_count) { - init_count = 1; - ret = arc_clockevent_setup(np); - } else { - ret = arc_cs_setup_timer1(np); - } - - return ret; -} -CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init); diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index e2c6e43cf8ca..4866f7aa32e6 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -282,6 +282,26 @@ config CLKSRC_MPS2 select CLKSRC_MMIO select CLKSRC_OF +config ARC_TIMERS + bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS + select CLKSRC_OF + help + These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores + (ARC700 as well as ARC HS38). + TIMER0 serves as clockevent while TIMER1 provides clocksource + +config ARC_TIMERS_64BIT + bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS + depends on ARC_TIMERS + select CLKSRC_OF + help + This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP) + RTC is implemented inside the core, while GFRC sits outside the core in + ARConnect IP block. Driver automatically picks one of them for clocksource + as appropriate. + config ARM_ARCH_TIMER bool select CLKSRC_OF if OF diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cf87f407f1ad..a14111e1f087 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o +obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c new file mode 100644 index 000000000000..a49748d826c0 --- /dev/null +++ b/drivers/clocksource/arc_timer.c @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be + * programmed to go from @count to @limit and optionally interrupt. + * We've designated TIMER0 for clockevents and TIMER1 for clocksource + * + * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP) + * which are suitable for UP and SMP based clocksources respectively + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + + +static unsigned long arc_timer_freq; + +static int noinline arc_get_timer_clk(struct device_node *node) +{ + struct clk *clk; + int ret; + + clk = of_clk_get(node, 0); + if (IS_ERR(clk)) { + pr_err("timer missing clk"); + return PTR_ERR(clk); + } + + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("Couldn't enable parent clk\n"); + return ret; + } + + arc_timer_freq = clk_get_rate(clk); + + return 0; +} + +/********** Clock Source Device *********/ + +#ifdef CONFIG_ARC_TIMERS_64BIT + +static cycle_t arc_read_gfrc(struct clocksource *cs) +{ + unsigned long flags; + u32 l, h; + + local_irq_save(flags); + + __mcip_cmd(CMD_GFRC_READ_LO, 0); + l = read_aux_reg(ARC_REG_MCIP_READBACK); + + __mcip_cmd(CMD_GFRC_READ_HI, 0); + h = read_aux_reg(ARC_REG_MCIP_READBACK); + + local_irq_restore(flags); + + return (((cycle_t)h) << 32) | l; +} + +static struct clocksource arc_counter_gfrc = { + .name = "ARConnect GFRC", + .rating = 400, + .read = arc_read_gfrc, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init arc_cs_setup_gfrc(struct device_node *node) +{ + struct mcip_bcr mp; + int ret; + + READ_BCR(ARC_REG_MCIP_BCR, mp); + if (!mp.gfrc) { + pr_warn("Global-64-bit-Ctr clocksource not detected"); + return -ENXIO; + } + + ret = arc_get_timer_clk(node); + if (ret) + return ret; + + return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); +} +CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); + +#define AUX_RTC_CTRL 0x103 +#define AUX_RTC_LOW 0x104 +#define AUX_RTC_HIGH 0x105 + +static cycle_t arc_read_rtc(struct clocksource *cs) +{ + unsigned long status; + u32 l, h; + + /* + * hardware has an internal state machine which tracks readout of + * low/high and updates the CTRL.status if + * - interrupt/exception taken between the two reads + * - high increments after low has been read + */ + do { + l = read_aux_reg(AUX_RTC_LOW); + h = read_aux_reg(AUX_RTC_HIGH); + status = read_aux_reg(AUX_RTC_CTRL); + } while (!(status & _BITUL(31))); + + return (((cycle_t)h) << 32) | l; +} + +static struct clocksource arc_counter_rtc = { + .name = "ARCv2 RTC", + .rating = 350, + .read = arc_read_rtc, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init arc_cs_setup_rtc(struct device_node *node) +{ + struct bcr_timer timer; + int ret; + + READ_BCR(ARC_REG_TIMERS_BCR, timer); + if (!timer.rtc) { + pr_warn("Local-64-bit-Ctr clocksource not detected"); + return -ENXIO; + } + + /* Local to CPU hence not usable in SMP */ + if (IS_ENABLED(CONFIG_SMP)) { + pr_warn("Local-64-bit-Ctr not usable in SMP"); + return -EINVAL; + } + + ret = arc_get_timer_clk(node); + if (ret) + return ret; + + write_aux_reg(AUX_RTC_CTRL, 1); + + return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); +} +CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); + +#endif + +/* + * 32bit TIMER1 to keep counting monotonically and wraparound + */ + +static cycle_t arc_read_timer1(struct clocksource *cs) +{ + return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); +} + +static struct clocksource arc_counter_timer1 = { + .name = "ARC Timer1", + .rating = 300, + .read = arc_read_timer1, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init arc_cs_setup_timer1(struct device_node *node) +{ + int ret; + + /* Local to CPU hence not usable in SMP */ + if (IS_ENABLED(CONFIG_SMP)) + return -EINVAL; + + ret = arc_get_timer_clk(node); + if (ret) + return ret; + + write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); + write_aux_reg(ARC_REG_TIMER1_CNT, 0); + write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); + + return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq); +} + +/********** Clock Event Device *********/ + +static int arc_timer_irq; + +/* + * Arm the timer to interrupt after @cycles + * The distinction for oneshot/periodic is done in arc_event_timer_ack() below + */ +static void arc_timer_event_setup(unsigned int cycles) +{ + write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); + write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ + + write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); +} + + +static int arc_clkevent_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + arc_timer_event_setup(delta); + return 0; +} + +static int arc_clkevent_set_periodic(struct clock_event_device *dev) +{ + /* + * At X Hz, 1 sec = 1000ms -> X cycles; + * 10ms -> X / 100 cycles + */ + arc_timer_event_setup(arc_timer_freq / HZ); + return 0; +} + +static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { + .name = "ARC Timer0", + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC, + .rating = 300, + .set_next_event = arc_clkevent_set_next_event, + .set_state_periodic = arc_clkevent_set_periodic, +}; + +static irqreturn_t timer_irq_handler(int irq, void *dev_id) +{ + /* + * Note that generic IRQ core could have passed @evt for @dev_id if + * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() + */ + struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); + int irq_reenable = clockevent_state_periodic(evt); + + /* + * Any write to CTRL reg ACks the interrupt, we rewrite the + * Count when [N]ot [H]alted bit. + * And re-arm it if perioid by [I]nterrupt [E]nable bit + */ + write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + + +static int arc_timer_starting_cpu(unsigned int cpu) +{ + struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); + + evt->cpumask = cpumask_of(smp_processor_id()); + + clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX); + enable_percpu_irq(arc_timer_irq, 0); + return 0; +} + +static int arc_timer_dying_cpu(unsigned int cpu) +{ + disable_percpu_irq(arc_timer_irq); + return 0; +} + +/* + * clockevent setup for boot CPU + */ +static int __init arc_clockevent_setup(struct device_node *node) +{ + struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); + int ret; + + arc_timer_irq = irq_of_parse_and_map(node, 0); + if (arc_timer_irq <= 0) { + pr_err("clockevent: missing irq"); + return -EINVAL; + } + + ret = arc_get_timer_clk(node); + if (ret) { + pr_err("clockevent: missing clk"); + return ret; + } + + /* Needs apriori irq_set_percpu_devid() done in intc map function */ + ret = request_percpu_irq(arc_timer_irq, timer_irq_handler, + "Timer0 (per-cpu-tick)", evt); + if (ret) { + pr_err("clockevent: unable to request irq\n"); + return ret; + } + + ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING, + "AP_ARC_TIMER_STARTING", + arc_timer_starting_cpu, + arc_timer_dying_cpu); + if (ret) { + pr_err("Failed to setup hotplug state"); + return ret; + } + return 0; +} + +static int __init arc_of_timer_init(struct device_node *np) +{ + static int init_count = 0; + int ret; + + if (!init_count) { + init_count = 1; + ret = arc_clockevent_setup(np); + } else { + ret = arc_cs_setup_timer1(np); + } + + return ret; +} +CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init); -- cgit v1.2.3 From 09dcd1958be42ea473fef24a2c02d975f520ea71 Mon Sep 17 00:00:00 2001 From: Noam Camus Date: Wed, 16 Nov 2016 08:31:11 +0200 Subject: soc: Support for NPS HW scheduling This new header file is for NPS400 SoC (part of ARC architecture). The header file includes macros for save/restore of HW scheduling. The control of HW scheduling is achieved by writing core registers. This code was moved from arc/plat-eznps so it can be used from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT. Signed-off-by: Noam Camus Acked-by: Daniel Lezcano --- arch/arc/plat-eznps/include/plat/ctop.h | 2 -- include/soc/nps/mtm.h | 59 +++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 2 deletions(-) create mode 100644 include/soc/nps/mtm.h diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h index 9d6718c1a199..ee2e32df5e90 100644 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ b/arch/arc/plat-eznps/include/plat/ctop.h @@ -46,9 +46,7 @@ #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300) /* EZchip core instructions */ -#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF -#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3 #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103 #define CTOP_INST_SCHD_RW 0x3E6F7004 #define CTOP_INST_SCHD_RD 0x3E6F7084 diff --git a/include/soc/nps/mtm.h b/include/soc/nps/mtm.h new file mode 100644 index 000000000000..d2f5e7e3703e --- /dev/null +++ b/include/soc/nps/mtm.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016, Mellanox Technologies. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef SOC_NPS_MTM_H +#define SOC_NPS_MTM_H + +#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF +#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3 + +static inline void hw_schd_save(unsigned int *flags) +{ + __asm__ __volatile__( + " .word %1\n" + " st r3,[%0]\n" + : + : "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3) + : "r3", "memory"); +} + +static inline void hw_schd_restore(unsigned int flags) +{ + __asm__ __volatile__( + " mov r3, %0\n" + " .word %1\n" + : + : "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3) + : "r3"); +} + +#endif /* SOC_NPS_MTM_H */ -- cgit v1.2.3 From 0465fb495f9c9698de08ff103905008e5f38e8f1 Mon Sep 17 00:00:00 2001 From: Noam Camus Date: Wed, 16 Nov 2016 08:31:12 +0200 Subject: clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer nps_setup_clocksource() should take node as only argument as defined by typedef int (*of_init_fn_1_ret)(struct device_node *) Therefore need to replace: int __init nps_setup_clocksource(struct device_node *node, struct clk *clk) with int __init nps_setup_clocksource(struct device_node *node) This patch also serve as preparation for next patch which add support for clockevents to nps400. Specifically we add new function nps_get_timer_clk() to serve clocksource and later clockevent registration. Signed-off-by: Noam Camus Acked-by: Daniel Lezcano --- drivers/clocksource/timer-nps.c | 65 ++++++++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 26 deletions(-) diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c index 70c149af8ee0..0c8e21f905d7 100644 --- a/drivers/clocksource/timer-nps.c +++ b/drivers/clocksource/timer-nps.c @@ -46,7 +46,35 @@ /* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */ static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly; -static unsigned long nps_timer_rate; +static int __init nps_get_timer_clk(struct device_node *node, + unsigned long *timer_freq, + struct clk **clk) +{ + int ret; + + *clk = of_clk_get(node, 0); + if (IS_ERR(*clk)) { + pr_err("timer missing clk"); + return PTR_ERR(*clk); + } + + ret = clk_prepare_enable(*clk); + if (ret) { + pr_err("Couldn't enable parent clk\n"); + clk_put(*clk); + return ret; + } + + *timer_freq = clk_get_rate(*clk); + if (!(*timer_freq)) { + pr_err("Couldn't get clk rate\n"); + clk_disable_unprepare(*clk); + clk_put(*clk); + return -EINVAL; + } + + return 0; +} static cycle_t nps_clksrc_read(struct clocksource *clksrc) { @@ -55,26 +83,24 @@ static cycle_t nps_clksrc_read(struct clocksource *clksrc) return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]); } -static int __init nps_setup_clocksource(struct device_node *node, - struct clk *clk) +static int __init nps_setup_clocksource(struct device_node *node) { int ret, cluster; + struct clk *clk; + unsigned long nps_timer1_freq; + for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++) nps_msu_reg_low_addr[cluster] = nps_host_reg((cluster << NPS_CLUSTER_OFFSET), - NPS_MSU_BLKID, NPS_MSU_TICK_LOW); + NPS_MSU_BLKID, NPS_MSU_TICK_LOW); - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("Couldn't enable parent clock\n"); + ret = nps_get_timer_clk(node, &nps_timer1_freq, &clk); + if (ret) return ret; - } - nps_timer_rate = clk_get_rate(clk); - - ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick", - nps_timer_rate, 301, 32, nps_clksrc_read); + ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick", + nps_timer1_freq, 300, 32, nps_clksrc_read); if (ret) { pr_err("Couldn't register clock source.\n"); clk_disable_unprepare(clk); @@ -83,18 +109,5 @@ static int __init nps_setup_clocksource(struct device_node *node, return ret; } -static int __init nps_timer_init(struct device_node *node) -{ - struct clk *clk; - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("Can't get timer clock.\n"); - return PTR_ERR(clk); - } - - return nps_setup_clocksource(node, clk); -} - CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer", - nps_timer_init); + nps_setup_clocksource); -- cgit v1.2.3 From 60263dcd821b9558ea08b112d9d31ffbe3ac643f Mon Sep 17 00:00:00 2001 From: Noam Camus Date: Thu, 17 Nov 2016 09:12:43 +0200 Subject: clocksource: Add clockevent support to NPS400 driver Till now we used clockevent from generic ARC driver. This was enough as long as we worked with simple multicore SoC. When we are working with multithread SoC each HW thread can be scheduled to receive timer interrupt using timer mask register. This patch will provide a way to control clock events per HW thread. The design idea is that for each core there is dedicated register (TSI) serving all 16 HW threads. The register is a bitmask with one bit for each HW thread. When HW thread wants that next expiration of timer interrupt will hit it then the proper bit should be set in this dedicated register. When timer expires all HW threads within this core which their bit is set at the TSI register will be interrupted. Driver can be used from device tree by: compatible = "ezchip,nps400-timer0" <-- for clocksource compatible = "ezchip,nps400-timer1" <-- for clockevent Note that name convention for timer0/timer1 was taken from legacy ARC design. This design is our base before adding HW threads. For backward compatibility we keep "ezchip,nps400-timer" for clocksource Signed-off-by: Noam Camus Acked-by: Daniel Lezcano Acked-by: Rob Herring --- .../bindings/timer/ezchip,nps400-timer.txt | 15 -- .../bindings/timer/ezchip,nps400-timer0.txt | 17 +++ .../bindings/timer/ezchip,nps400-timer1.txt | 15 ++ drivers/clocksource/timer-nps.c | 170 +++++++++++++++++++++ 4 files changed, 202 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt deleted file mode 100644 index c8c03d700382..000000000000 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt +++ /dev/null @@ -1,15 +0,0 @@ -NPS Network Processor - -Required properties: - -- compatible : should be "ezchip,nps400-timer" - -Clocks required for compatible = "ezchip,nps400-timer": -- clocks : Must contain a single entry describing the clock input - -Example: - -timer { - compatible = "ezchip,nps400-timer"; - clocks = <&sysclk>; -}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt new file mode 100644 index 000000000000..e3cfce8fecc5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt @@ -0,0 +1,17 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer0" + +Clocks required for compatible = "ezchip,nps400-timer0": +- interrupts : The interrupt of the first timer +- clocks : Must contain a single entry describing the clock input + +Example: + +timer { + compatible = "ezchip,nps400-timer0"; + interrupts = <3>; + clocks = <&sysclk>; +}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt new file mode 100644 index 000000000000..c0ab4190b8fb --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt @@ -0,0 +1,15 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer1" + +Clocks required for compatible = "ezchip,nps400-timer1": +- clocks : Must contain a single entry describing the clock input + +Example: + +timer { + compatible = "ezchip,nps400-timer1"; + clocks = <&sysclk>; +}; diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c index 0c8e21f905d7..b4c8a023a2d4 100644 --- a/drivers/clocksource/timer-nps.c +++ b/drivers/clocksource/timer-nps.c @@ -111,3 +111,173 @@ static int __init nps_setup_clocksource(struct device_node *node) CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer", nps_setup_clocksource); +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1", + nps_setup_clocksource); + +#ifdef CONFIG_EZNPS_MTM_EXT +#include + +/* Timer related Aux registers */ +#define NPS_REG_TIMER0_TSI 0xFFFFF850 +#define NPS_REG_TIMER0_LIMIT 0x23 +#define NPS_REG_TIMER0_CTRL 0x22 +#define NPS_REG_TIMER0_CNT 0x21 + +/* + * Interrupt Enabled (IE) - re-arm the timer + * Not Halted (NH) - is cleared when working with JTAG (for debug) + */ +#define TIMER0_CTRL_IE BIT(0) +#define TIMER0_CTRL_NH BIT(1) + +static unsigned long nps_timer0_freq; +static unsigned long nps_timer0_irq; + +static void nps_clkevent_rm_thread(void) +{ + int thread; + unsigned int cflags, enabled_threads; + + hw_schd_save(&cflags); + + enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI); + + /* remove thread from TSI1 */ + thread = read_aux_reg(CTOP_AUX_THREAD_ID); + enabled_threads &= ~(1 << thread); + write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads); + + /* Acknowledge and if needed re-arm the timer */ + if (!enabled_threads) + write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH); + else + write_aux_reg(NPS_REG_TIMER0_CTRL, + TIMER0_CTRL_IE | TIMER0_CTRL_NH); + + hw_schd_restore(cflags); +} + +static void nps_clkevent_add_thread(unsigned long delta) +{ + int thread; + unsigned int cflags, enabled_threads; + + hw_schd_save(&cflags); + + /* add thread to TSI1 */ + thread = read_aux_reg(CTOP_AUX_THREAD_ID); + enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI); + enabled_threads |= (1 << thread); + write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads); + + /* set next timer event */ + write_aux_reg(NPS_REG_TIMER0_LIMIT, delta); + write_aux_reg(NPS_REG_TIMER0_CNT, 0); + write_aux_reg(NPS_REG_TIMER0_CTRL, + TIMER0_CTRL_IE | TIMER0_CTRL_NH); + + hw_schd_restore(cflags); +} + +/* + * Whenever anyone tries to change modes, we just mask interrupts + * and wait for the next event to get set. + */ +static int nps_clkevent_set_state(struct clock_event_device *dev) +{ + nps_clkevent_rm_thread(); + disable_percpu_irq(nps_timer0_irq); + + return 0; +} + +static int nps_clkevent_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + nps_clkevent_add_thread(delta); + enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE); + + return 0; +} + +static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = { + .name = "NPS Timer0", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 300, + .set_next_event = nps_clkevent_set_next_event, + .set_state_oneshot = nps_clkevent_set_state, + .set_state_oneshot_stopped = nps_clkevent_set_state, + .set_state_shutdown = nps_clkevent_set_state, + .tick_resume = nps_clkevent_set_state, +}; + +static irqreturn_t timer_irq_handler(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + nps_clkevent_rm_thread(); + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static int nps_timer_starting_cpu(unsigned int cpu) +{ + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device); + + evt->cpumask = cpumask_of(smp_processor_id()); + + clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX); + enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE); + + return 0; +} + +static int nps_timer_dying_cpu(unsigned int cpu) +{ + disable_percpu_irq(nps_timer0_irq); + return 0; +} + +static int __init nps_setup_clockevent(struct device_node *node) +{ + struct clk *clk; + int ret; + + nps_timer0_irq = irq_of_parse_and_map(node, 0); + if (nps_timer0_irq <= 0) { + pr_err("clockevent: missing irq"); + return -EINVAL; + } + + ret = nps_get_timer_clk(node, &nps_timer0_freq, &clk); + if (ret) + return ret; + + /* Needs apriori irq_set_percpu_devid() done in intc map function */ + ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler, + "Timer0 (per-cpu-tick)", + &nps_clockevent_device); + if (ret) { + pr_err("Couldn't request irq\n"); + clk_disable_unprepare(clk); + return ret; + } + + ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING, + "clockevents/nps:starting", + nps_timer_starting_cpu, + nps_timer_dying_cpu); + if (ret) { + pr_err("Failed to setup hotplug state"); + clk_disable_unprepare(clk); + free_percpu_irq(nps_timer0_irq, &nps_clockevent_device); + return ret; + } + + return 0; +} + +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0", + nps_setup_clockevent); +#endif /* CONFIG_EZNPS_MTM_EXT */ -- cgit v1.2.3 From a26b0d4962c7daf91d942a917c71c20e164b687a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 22 Nov 2016 15:33:44 +0100 Subject: clocksource: nps: avoid maybe-uninitialized warning We get a harmless false-positive warning with the newly added nps clocksource driver: drivers/clocksource/timer-nps.c: In function 'nps_setup_clocksource': drivers/clocksource/timer-nps.c:102:6: error: 'nps_timer1_freq' may be used uninitialized in this function [-Werror=maybe-uninitialized] Gcc here fails to identify that IS_ERR() is only true if PTR_ERR() has a nonzero value. Using PTR_ERR_OR_ZERO() to convert the result first makes this obvious and shuts up the warning. Fixes: 0ee4d9922df5 ("clocksource: Add clockevent support to NPS400 driver") Signed-off-by: Arnd Bergmann Signed-off-by: Vineet Gupta --- drivers/clocksource/timer-nps.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c index b4c8a023a2d4..8da5e93b6810 100644 --- a/drivers/clocksource/timer-nps.c +++ b/drivers/clocksource/timer-nps.c @@ -53,9 +53,10 @@ static int __init nps_get_timer_clk(struct device_node *node, int ret; *clk = of_clk_get(node, 0); - if (IS_ERR(*clk)) { + ret = PTR_ERR_OR_ZERO(*clk); + if (ret) { pr_err("timer missing clk"); - return PTR_ERR(*clk); + return ret; } ret = clk_prepare_enable(*clk); -- cgit v1.2.3 From 4988cc5635ed20a8c35bb7dd69b129c172ec10aa Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Fri, 18 Nov 2016 14:19:27 -0800 Subject: ARC: rename Zebu platform support to HAPS There are more ARC Linux HAPS users than Zebu ones. Same kernel would work fine on both, even with embedded DT, assuming the FPGA bitfile configuration is same Suggested-by: Francois Bedard Signed-off-by: Vineet Gupta --- arch/arc/boot/dts/haps_hs.dts | 69 ++++++++++++++++++++++++++ arch/arc/boot/dts/haps_hs_idu.dts | 85 ++++++++++++++++++++++++++++++++ arch/arc/boot/dts/zebu_hs.dts | 69 -------------------------- arch/arc/boot/dts/zebu_hs_idu.dts | 85 -------------------------------- arch/arc/configs/haps_hs_defconfig | 86 ++++++++++++++++++++++++++++++++ arch/arc/configs/haps_hs_smp_defconfig | 89 ++++++++++++++++++++++++++++++++++ arch/arc/configs/zebu_hs_defconfig | 86 -------------------------------- arch/arc/configs/zebu_hs_smp_defconfig | 89 ---------------------------------- 8 files changed, 329 insertions(+), 329 deletions(-) create mode 100644 arch/arc/boot/dts/haps_hs.dts create mode 100644 arch/arc/boot/dts/haps_hs_idu.dts delete mode 100644 arch/arc/boot/dts/zebu_hs.dts delete mode 100644 arch/arc/boot/dts/zebu_hs_idu.dts create mode 100644 arch/arc/configs/haps_hs_defconfig create mode 100644 arch/arc/configs/haps_hs_smp_defconfig delete mode 100644 arch/arc/configs/zebu_hs_defconfig delete mode 100644 arch/arc/configs/zebu_hs_smp_defconfig diff --git a/arch/arc/boot/dts/haps_hs.dts b/arch/arc/boot/dts/haps_hs.dts new file mode 100644 index 000000000000..1c1324e84965 --- /dev/null +++ b/arch/arc/boot/dts/haps_hs.dts @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton_hs.dtsi" + +/ { + model = "snps,zebu_hs"; + compatible = "snps,zebu_hs"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&core_intc>; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 */ + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; + }; + + aliases { + serial0 = &uart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + core_intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart0: serial@f0000000 { + compatible = "ns8250"; + reg = <0xf0000000 0x2000>; + interrupts = <24>; + clock-frequency = <50000000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test = <1>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/arch/arc/boot/dts/haps_hs_idu.dts b/arch/arc/boot/dts/haps_hs_idu.dts new file mode 100644 index 000000000000..65204b4c0f13 --- /dev/null +++ b/arch/arc/boot/dts/haps_hs_idu.dts @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "skeleton_hs_idu.dtsi" + +/ { + model = "snps,zebu_hs-smp"; + compatible = "snps,zebu_hs"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&core_intc>; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 */ + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug"; + }; + + aliases { + serial0 = &uart0; + }; + + fpga { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* child and parent address space 1:1 mapped */ + ranges; + + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; /* 50 MHZ */ + }; + + core_intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; +/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */ + }; + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + interrupt-parent = <&core_intc>; + /* + distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */ + #interrupt-cells = <2>; + interrupts = <24 25 26 27 28 29 30 31>; + + }; + + uart0: serial@f0000000 { + /* compatible = "ns8250"; Doesn't use FIFOs */ + compatible = "ns16550a"; + reg = <0xf0000000 0x2000>; + interrupt-parent = <&idu_intc>; + /* interrupts = <0 1>; DEST=1*/ + /* interrupts = <0 2>; DEST=2*/ + interrupts = <0 0>; /* RR*/ + clock-frequency = <50000000>; + baud = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test = <1>; + }; + + arcpct0: pct { + compatible = "snps,archs-pct"; + #interrupt-cells = <1>; + interrupts = <20>; + }; + }; +}; diff --git a/arch/arc/boot/dts/zebu_hs.dts b/arch/arc/boot/dts/zebu_hs.dts deleted file mode 100644 index 1c1324e84965..000000000000 --- a/arch/arc/boot/dts/zebu_hs.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "skeleton_hs.dtsi" - -/ { - model = "snps,zebu_hs"; - compatible = "snps,zebu_hs"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&core_intc>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 */ - }; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; - }; - - aliases { - serial0 = &uart0; - }; - - fpga { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - /* child and parent address space 1:1 mapped */ - ranges; - - core_clk: core_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - core_intc: interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - - uart0: serial@f0000000 { - compatible = "ns8250"; - reg = <0xf0000000 0x2000>; - interrupts = <24>; - clock-frequency = <50000000>; - baud = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test = <1>; - }; - - arcpct0: pct { - compatible = "snps,archs-pct"; - #interrupt-cells = <1>; - interrupts = <20>; - }; - }; -}; diff --git a/arch/arc/boot/dts/zebu_hs_idu.dts b/arch/arc/boot/dts/zebu_hs_idu.dts deleted file mode 100644 index 65204b4c0f13..000000000000 --- a/arch/arc/boot/dts/zebu_hs_idu.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "skeleton_hs_idu.dtsi" - -/ { - model = "snps,zebu_hs-smp"; - compatible = "snps,zebu_hs"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&core_intc>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 */ - }; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug"; - }; - - aliases { - serial0 = &uart0; - }; - - fpga { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - /* child and parent address space 1:1 mapped */ - ranges; - - core_clk: core_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; /* 50 MHZ */ - }; - - core_intc: interrupt-controller { - compatible = "snps,archs-intc"; - interrupt-controller; - #interrupt-cells = <1>; -/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */ - }; - - idu_intc: idu-interrupt-controller { - compatible = "snps,archs-idu-intc"; - interrupt-controller; - interrupt-parent = <&core_intc>; - /* - distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */ - #interrupt-cells = <2>; - interrupts = <24 25 26 27 28 29 30 31>; - - }; - - uart0: serial@f0000000 { - /* compatible = "ns8250"; Doesn't use FIFOs */ - compatible = "ns16550a"; - reg = <0xf0000000 0x2000>; - interrupt-parent = <&idu_intc>; - /* interrupts = <0 1>; DEST=1*/ - /* interrupts = <0 2>; DEST=2*/ - interrupts = <0 0>; /* RR*/ - clock-frequency = <50000000>; - baud = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test = <1>; - }; - - arcpct0: pct { - compatible = "snps,archs-pct"; - #interrupt-cells = <1>; - interrupts = <20>; - }; - }; -}; diff --git a/arch/arc/configs/haps_hs_defconfig b/arch/arc/configs/haps_hs_defconfig new file mode 100644 index 000000000000..57b3e599322f --- /dev/null +++ b/arch/arc/configs/haps_hs_defconfig @@ -0,0 +1,86 @@ +CONFIG_DEFAULT_HOSTNAME="ARCLinux" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/" +CONFIG_EXPERT=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_MODULES=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARC_PLAT_SIM=y +CONFIG_ISA_ARCV2=y +CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs" +CONFIG_PREEMPT=y +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_BLK_DEV is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_ARC_PS2=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_HID is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PREEMPT is not set diff --git a/arch/arc/configs/haps_hs_smp_defconfig b/arch/arc/configs/haps_hs_smp_defconfig new file mode 100644 index 000000000000..f85985adebb2 --- /dev/null +++ b/arch/arc/configs/haps_hs_smp_defconfig @@ -0,0 +1,89 @@ +CONFIG_DEFAULT_HOSTNAME="ARCLinux" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/" +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARC_PLAT_SIM=y +CONFIG_ISA_ARCV2=y +CONFIG_SMP=y +CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu" +CONFIG_PREEMPT=y +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_BLK_DEV is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_EVDEV=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_ARC_PS2=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_HID is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_DEBUG_PREEMPT is not set diff --git a/arch/arc/configs/zebu_hs_defconfig b/arch/arc/configs/zebu_hs_defconfig deleted file mode 100644 index 9f6166be7145..000000000000 --- a/arch/arc/configs/zebu_hs_defconfig +++ /dev/null @@ -1,86 +0,0 @@ -CONFIG_DEFAULT_HOSTNAME="ARCLinux" -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -# CONFIG_CROSS_MEMORY_ATTACH is not set -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/" -CONFIG_EXPERT=y -CONFIG_PERF_EVENTS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARC_PLAT_SIM=y -CONFIG_ISA_ARCV2=y -CONFIG_ARC_BUILTIN_DTB_NAME="zebu_hs" -CONFIG_PREEMPT=y -# CONFIG_COMPACTION is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=y -CONFIG_UNIX=y -CONFIG_UNIX_DIAG=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_DEVTMPFS=y -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FIRMWARE_IN_KERNEL is not set -# CONFIG_BLK_DEV is not set -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_VIA is not set -# CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_WLAN is not set -CONFIG_INPUT_EVDEV=y -CONFIG_MOUSE_PS2_TOUCHKIT=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_ARC_PS2=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_HID is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_MEMORY_INIT=y -# CONFIG_DEBUG_PREEMPT is not set diff --git a/arch/arc/configs/zebu_hs_smp_defconfig b/arch/arc/configs/zebu_hs_smp_defconfig deleted file mode 100644 index 44e9693f4257..000000000000 --- a/arch/arc/configs/zebu_hs_smp_defconfig +++ /dev/null @@ -1,89 +0,0 @@ -CONFIG_DEFAULT_HOSTNAME="ARCLinux" -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -# CONFIG_CROSS_MEMORY_ATTACH is not set -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/" -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_KPROBES=y -CONFIG_MODULES=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARC_PLAT_SIM=y -CONFIG_ISA_ARCV2=y -CONFIG_SMP=y -CONFIG_ARC_BUILTIN_DTB_NAME="zebu_hs_idu" -CONFIG_PREEMPT=y -# CONFIG_COMPACTION is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=y -CONFIG_UNIX=y -CONFIG_UNIX_DIAG=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_DEVTMPFS=y -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FIRMWARE_IN_KERNEL is not set -# CONFIG_BLK_DEV is not set -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_VIA is not set -# CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_WLAN is not set -CONFIG_INPUT_EVDEV=y -CONFIG_MOUSE_PS2_TOUCHKIT=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_ARC_PS2=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_HID is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_LOCKUP_DETECTOR=y -# CONFIG_DEBUG_PREEMPT is not set -- cgit v1.2.3 From 7badf6fefca8278e749e82411fdb98b123cca50e Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 22 Nov 2016 14:16:36 +0300 Subject: ARC: axs10x: really enable ARC PGU Up until now we had ARC PGU not enabled in axs10x defconfigs trying to not bloat kernel image again with yet another drivers and subsystems. This change configures ARC PGU (as well as DRM bits it depends on) to be built as a module and so those who need LCD screen to work on axs10x may bundle built .ko files in their target's file-system with help of the following command on host: ------------->8------------- make INSTALL_MOD_PATH=_path_to_target_fs_ modules_install ------------->8------------- and later on target with commands as simple as: ------------->8------------- modprobe adv7511.ko modprobe arcpgu.ko ------------->8------------- get LCD working. Signed-off-by: Alexey Brodkin Signed-off-by: Vineet Gupta --- arch/arc/boot/dts/axs101.dts | 2 +- arch/arc/boot/dts/axs103_idu.dts | 2 +- arch/arc/configs/axs101_defconfig | 4 +++- arch/arc/configs/axs103_smp_defconfig | 4 +++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arc/boot/dts/axs101.dts b/arch/arc/boot/dts/axs101.dts index d9b9b9dcfc4c..70aec7d6ca60 100644 --- a/arch/arc/boot/dts/axs101.dts +++ b/arch/arc/boot/dts/axs101.dts @@ -17,6 +17,6 @@ compatible = "snps,axs101", "snps,arc-sdp"; chosen { - bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0"; + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=1280x720@60"; }; }; diff --git a/arch/arc/boot/dts/axs103_idu.dts b/arch/arc/boot/dts/axs103_idu.dts index 070c29782216..5c843d9b4ac8 100644 --- a/arch/arc/boot/dts/axs103_idu.dts +++ b/arch/arc/boot/dts/axs103_idu.dts @@ -20,6 +20,6 @@ compatible = "snps,axs103", "snps,arc-sdp"; chosen { - bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1"; + bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 print-fatal-signals=1 consoleblank=0 video=1280x720@60"; }; }; diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig index 0a0eaf09aac7..6980b966a364 100644 --- a/arch/arc/configs/axs101_defconfig +++ b/arch/arc/configs/axs101_defconfig @@ -75,9 +75,11 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_DESIGNWARE_PLATFORM=y # CONFIG_HWMON is not set +CONFIG_DRM=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_ARCPGU=m CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig index 110874705085..30a3d4cf53d2 100644 --- a/arch/arc/configs/axs103_smp_defconfig +++ b/arch/arc/configs/axs103_smp_defconfig @@ -77,9 +77,11 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_DESIGNWARE_PLATFORM=y # CONFIG_HWMON is not set +CONFIG_DRM=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_ARCPGU=m CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set -- cgit v1.2.3