From 47b5d3697f6b9f53a0db30a99656a2f8f919e246 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 2 Dec 2025 13:54:31 +0400 Subject: arm64: dts: rockchip: Add overlay for the PCIe slot on RK3576 EVB1 Rockchip RK3576 EVB1 has an onboard PCIe slot (PCIe 2.1, x4 mechanically, x1 electrically), but it shares pins and PHY with the only USB3 Type-A port. There is a physical switch next to the slot to transfer respective pins connection from the USB3 port to the PCIe slot, but apart from flipping the switch one must also disable the USB3 host controller to prevent it from claiming the PHY before the PCIe slot can become usable. Add an overlay to disable the USB3 host port and instead enable the PCIe slot, along with its pin configs. The physical switch must still be flipped to the "ON - PCIe1" position for this to work. Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251202-evb1-pcie1-v2-1-810693b1b72f@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 ++++ .../boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso | 31 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index dbdda9783e93..3fdd1e4832e1 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-100ask-dshanpi-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb @@ -259,6 +260,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtb rk3576-armsom-sige5-v1.2-wifibt-dtbs := rk3576-armsom-sige5.dtb \ rk3576-armsom-sige5-v1.2-wifibt.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtb +rk3576-evb1-v10-pcie1-dtbs := rk3576-evb1-v10.dtb \ + rk3576-evb1-v10-pcie1.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6a-wifi.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso new file mode 100644 index 000000000000..dccf4a5debdb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to enable the onboard PCIe x1 slot, which shares pins and the PHY + * with the USB3 host port. + * To use the PCIe slot, apply this overlay and flip the Dial_Switch_1 right + * next to the PCIe slot to low state (labeled "ON - PCIe1"). USB3 host port + * will be unusable (not even in 2.0 mode) + */ + +/dts-v1/; +/plugin/; + +#include + +&pcie1 { + pinctrl-0 = <&pcie1m0_pins &pcie1_rst>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + pcie1 { + pcie1_rst: pcie1-rst { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usb_drd1_dwc3 { + status = "disabled"; +}; -- cgit v1.2.3 From 2cc30da80a28a8a5d1337230c3586eb2f9580120 Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Mon, 24 Nov 2025 19:30:56 +0100 Subject: arm64: dts: rockchip: Enable SPDIF audio on Rock 5 ITX The Rock5 ITX has an S/PDIF (TOSLINK) socket in its I/O-shield, whose TX signal is wired to GPIO4 C1. Activate SPDIF TX unit 1 and select the proper pinmux (M2). Signed-off-by: Torsten Duwe Link: https://patch.msgid.link/20251124183056.B853068C4E@verein.lst.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 172aeabba72a..de154adb1497 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -147,6 +147,24 @@ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; }; + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + typec_vin: regulator-typec-vin { compatible = "regulator-fixed"; enable-active-high; @@ -854,6 +872,11 @@ }; }; +&spdif_tx1 { + pinctrl-0 = <&spdif1m2_tx>; + status = "okay"; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>; -- cgit v1.2.3 From abd9bb7ad5bdbbf76316013cda3812c2719a0210 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 24 Nov 2025 19:47:01 -0800 Subject: arm64: dts: rockchip: Add accelerometer sensor to Pinephone Pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pinephone Pro uses mpu6500 according to the schematic. This was verified via `monitor-sensor --accel`. While rotating the device, the output was correct (eg. when it was face up, left edge was up, vertical, etc.). Co-developed-by: Martijn Braam Signed-off-by: Martijn Braam Co-developed-by: Kamil Trzciński Signed-off-by: Kamil Trzciński Signed-off-by: Ondrej Jirman Signed-off-by: Rudraksha Gupta Reviewed-by: Pavel Machek Link: https://patch.msgid.link/20251124-ppp_light_accel_mag_vol-down-v5-2-f9a10a0a50eb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 2dca1dca20b8..5e9867e934d2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -533,7 +533,13 @@ reg = <0x68>; interrupt-parent = <&gpio1>; interrupts = ; + vdd-supply = <&vcc_1v8>; vddio-supply = <&vcc_1v8>; + + mount-matrix = + "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; }; }; -- cgit v1.2.3 From 3fc7029d3009682b27be2fa2cd2269bc6f104c2e Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 20 Dec 2025 18:00:08 +0800 Subject: arm64: dts: rockchip: remove rtc regulator for ArmSoM Sige5 According to the schematic, RTC is powered by vcc_3v3_s3. The vcc_3v3_rtc_s5 regulator does not exist, remove it. Signed-off-by: Chukun Pan Reviewed-by: Sebastian Reichel Link: https://patch.msgid.link/20251220100010.26643-1-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 3386084f6318..392ba83ab05a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -156,16 +156,6 @@ vin-supply = <&vcc_5v0_sys>; }; - vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_rtc_s5"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v0_sys>; - }; - vcc_3v3_s0: regulator-vcc-3v3-s0 { compatible = "regulator-fixed"; regulator-name = "vcc_3v3_s0"; -- cgit v1.2.3 From 341735d92ff868eb4c46beafb313d66f015809be Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 20 Dec 2025 18:00:09 +0800 Subject: arm64: dts: rockchip: fix hp-det pin for ArmSoM Sige5 Although the hp_det pin is not used, according to the schematic, the headphone detection pin is GPIO4_B0. Fix the incorrect pin. Signed-off-by: Chukun Pan Reviewed-by: Sebastian Reichel Link: https://patch.msgid.link/20251220100010.26643-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 392ba83ab05a..a0d8f52a706f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -812,8 +812,8 @@ }; headphone { - hp_det: hp-det { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + hp_det_l: hp-det-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; -- cgit v1.2.3 From 3025d360f03515d3f6396a5cec339e776d62b2da Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 20 Dec 2025 18:00:10 +0800 Subject: arm64: dts: rockchip: enable saradc for ArmSoM Sige5 Add ADC support to ArmSoM Sige5 board. Signed-off-by: Chukun Pan Link: https://patch.msgid.link/20251220100010.26643-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index a0d8f52a706f..d372ba252af8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -897,6 +897,11 @@ status = "okay"; }; +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; full-pwr-cycle-in-suspend; -- cgit v1.2.3 From f8a1d7d136f734e8e20e414eaf8aff74e6e0d55c Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 4 Dec 2025 08:50:28 +0800 Subject: arm64: dts: rockchip: Add PCIe clkreq stuff for RK3588 EVB1 Add supports-clkreq and pinmux for PCIe ASPM L1 substates. Signed-off-by: Shawn Lin Acked-by: Manivannan Sadhasivam Reviewed-by: Hans Zhang Link: https://patch.msgid.link/1764809428-183623-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index ff1ba5ed56ef..c9d284cb738b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -522,6 +522,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>, <&wifi_host_wake_irq>; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + supports-clkreq; vpcie3v3-supply = <&vcc3v3_wlan>; status = "okay"; @@ -545,7 +546,8 @@ &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; + pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>, <&pcie30x1m1_1_clkreqn>; + supports-clkreq; status = "okay"; }; @@ -555,7 +557,8 @@ &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_reset>; + pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; -- cgit v1.2.3 From 1b2d6b75e2b3374157c9015435381b217a887145 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Tue, 2 Dec 2025 08:49:40 +0000 Subject: arm64: dts: rockchip: Add EEPROMs for Radxa ROCK 4 boards The BL24C04A EEPROM is found in the schematics for Radxa ROCK Pi 4A+ and 4B+. [1] [2] The BL24C16A EEPROM is found in the schematics for Radxa ROCK 4C+, 4SE, Radxa ROCK Pi 4A, 4B, and 4C. [3] [4] [5] [6] [7] However, newer boards/batches should have the BL24C16A, but older ones may have the BL24C04A. (the ROCK Pi 4B+ I own has a 16Kb EEPROM) For the ROCK Pi 4s (except the relatively new ROCK 4SE), add the BL24C04A eeprom node for backward compatibility. For the ROCK 4SE, add the BL24C16A eeprom node. These are designed to have data written during factory programming (regardless of whether data is actually written or not), and we at Radxa permit users to read the data but not write to it. [8] Therefore, we will add a read-only property to the eeprom node. [1] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/4ap/radxa_rock_4ap_v1730_schematic.pdf p.17 [2] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/4bp/radxa_rock_4bp_v1730_schematic.pdf p.17 [3] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/ROCK-4C+-V1.411-SCH.pdf p.22 [4] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/ROCK-4-SE-V1.53-SCH.pdf p.17 [5] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/4a/ROCK_4A_V1.52_SCH.pdf p.17 [6] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/4b/ROCK_4B_v1.52_SCH.pdf p.17 [7] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4c_v12_sch_20200620.pdf p.17 [8] https://github.com/radxa/u-boot/blob/next-dev-v2024.10/drivers/misc/radxa-i2c-eeprom.c Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251202084941.1785-3-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts | 12 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 8 ++++++++ 3 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index 74160cf89188..f95fd92d58ba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -453,6 +453,14 @@ regulator-off-in-suspend; }; }; + + eeprom@50 { + compatible = "belling,bl24c04a", "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0_s0>; + }; }; &i2c3 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts index a8b8d4acc337..c0b931b3c640 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts @@ -8,6 +8,8 @@ #include "rk3399-t.dtsi" #include "rk3399-rock-pi-4.dtsi" +/delete-node/ &eeprom; + / { model = "Radxa ROCK 4SE"; compatible = "radxa,rock-4se", "rockchip,rk3399"; @@ -17,6 +19,16 @@ }; }; +&i2c0 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0>; + }; +}; + &sdio0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 046dbe329017..a8ab043e4062 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -456,6 +456,14 @@ regulator-off-in-suspend; }; }; + + eeprom: eeprom@50 { + compatible = "belling,bl24c04a", "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0>; + }; }; &i2c1 { -- cgit v1.2.3 From e3b12fc3336240e7dee4989b9e8634be3c959c94 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Tue, 2 Dec 2025 08:49:41 +0000 Subject: arm64: dts: rockchip: Add EEPROMs for Radxa rk35xx boards The BL24C16A EEPROM is found in the schematics for Radxa CM3I, Radxa ROCK 3A, 3B, 5B+, and 5T. [1] [2] [3] [4] [5] The BL24C16F EEPROM is found in the schematic for Radxa ROCK 4D. [6] Add these eeprom nodes. These are designed to have data written during factory programming (regardless of whether data is actually written or not), and we at Radxa permit users to read the data but not write to it. [8] Therefore, we will add a read-only property to the eeprom node. [1] https://dl.radxa.com/cm3i/docs/hw/radxa_cm3i_v1310_schematic.pdf p.8 [2] https://dl.radxa.com/rock3/docs/hw/3a/radxa_rock_3a_v1310_schematic.pdf p.7 [3] https://dl.radxa.com/rock3/docs/hw/3b/Radxa_ROCK_3B_V1.51_SCH.pdf p.35 [4] https://dl.radxa.com/rock5/5b+/docs/hw/radxa_rock5bp_v1.2_schematic.pdf p.29 [5] https://dl.radxa.com/rock5/5t/docs/hw/radxa_rock5t_schematic_v1.2_20250109.pdf p.36 [6] https://dl.radxa.com/rock4/4d/docs/hw/Radxa_ROCK_4D_SCH_V1.12.pdf p.23 [7] https://github.com/radxa/u-boot/blob/next-dev-v2024.10/drivers/misc/radxa-i2c-eeprom.c Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251202084941.1785-4-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 10 +++++++++- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 14 ++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts | 10 ++++++++++ 6 files changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi index 729e38b9f620..f97a0eb7f7c0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi @@ -321,7 +321,7 @@ }; }; - vcc_3v3: SWITCH_REG1 { + gpio_vref: vcc_3v3: SWITCH_REG1 { regulator-name = "vcc_3v3"; regulator-always-on; regulator-boot-on; @@ -340,6 +340,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&gpio_vref>; + }; }; &pinctrl { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 44cfdfeed668..9214e38648f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -532,6 +532,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc3v3_pmu>; + }; }; &i2c3 { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts index 3d0c1ccfaa79..69001e453732 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -480,6 +480,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc3v3_sys>; + }; }; &i2c5 { diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index 7023dc326d0e..899a84b1fbf9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -682,6 +682,20 @@ }; }; +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16f", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &mdio0 { rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts index 07a840d9b385..30d15c7e860a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts @@ -69,6 +69,16 @@ }; }; +&i2c1 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &pcie30phy { data-lanes = <1 1 2 2>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts index 0dd90c744380..425036146b6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts @@ -60,6 +60,16 @@ status = "okay"; }; +&i2c1 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &pcie2x1l1 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_1_rst>; -- cgit v1.2.3 From 2d6fcdcaf42671dd3fb281d7a2e5ea985af11ce5 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 28 Nov 2025 15:09:22 +0800 Subject: arm64: dts: rockchip: add dma-coherent for pcie and gmac of RK3576 The RK3576 SoC employs ARM CCI for maintaining cache coherency between the CPU cluster and high-speed peripherals including USB3, SATA, GMAC, and PCIe controllers. While the USB3 and SATA controllers were correctly marked as dma-coherent, the GMAC and PCIe nodes were overlooked. Without dma-coherent, the kernel falls back to software cache maintenance for DMA operations, requiring explicit cache flushing and invalidating. This adds significant overhead that degrades performance in high-throughput workloads. Add the missing dma-coherent properties to enable hardware coherency and avoid unnecessary software cache management overhead. Signed-off-by: Shawn Lin Link: https://patch.msgid.link/1764313762-78063-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index a86fc6b4e8c4..792857aee4f7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -680,6 +680,7 @@ "aclk_dbi", "pclk", "aux"; device_type = "pci"; + dma-coherent; interrupts = , , , @@ -734,6 +735,7 @@ "aclk_dbi", "pclk", "aux"; device_type = "pci"; + dma-coherent; interrupts = , , , @@ -1696,6 +1698,7 @@ clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref"; + dma-coherent; interrupts = , ; interrupt-names = "macirq", "eth_wake_irq"; @@ -1743,6 +1746,7 @@ clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref"; + dma-coherent; interrupts = , ; interrupt-names = "macirq", "eth_wake_irq"; -- cgit v1.2.3 From 396870f53c4e736366b4ed2e127874c30ce2f965 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 20 Oct 2025 12:07:55 +0200 Subject: arm64: dts: rockchip: add gmac reset property to rk3368 Add the reset of the gmac controller block. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20251020100757.3669681-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index ce4b112b082b..4c391e2341c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -498,6 +498,8 @@ "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac"; + resets = <&cru SRST_MAC>; + reset-names = "stmmaceth"; status = "disabled"; }; -- cgit v1.2.3 From bce933a74b8e785a8090da74bee8ec3f38be40b7 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 20 Oct 2025 12:07:56 +0200 Subject: arm64: dts: rockchip: add mdio subnode to gmac on rk3368 This is needed to actually describe the per-board phys connected to the gmac when needed. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20251020100757.3669681-3-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 4c391e2341c5..f9e24b25274b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -501,6 +501,12 @@ resets = <&cru SRST_MAC>; reset-names = "stmmaceth"; status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; }; usb_host0_ehci: usb@ff500000 { -- cgit v1.2.3 From 1cb0958a26aeffe315a60b3cbbc56b94246cc25a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 20 Oct 2025 12:07:57 +0200 Subject: arm64: dts: rockchip: Correctly describe the ethernet phy on rk3368-lion So far, the board used the phy implicitly using the deprecated snps reset properties. Improve that and describe the PHY correctly under the new mdio node. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20251020100757.3669681-4-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi index 8ccc3184a836..61c52bd91784 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -154,13 +154,11 @@ assigned-clocks = <&cru SCLK_MAC>; assigned-clock-parents = <&ext_gmac>; clock_in_out = "input"; + phy-handle = <&vsc8531_2>; phy-supply = <&vcc33_io>; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; tx_delay = <0x10>; rx_delay = <0x10>; status = "okay"; @@ -285,7 +283,25 @@ status = "okay"; }; +&mdio { + vsc8531_2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_rst>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + &pinctrl { + ethernet { + phy_rst: phy-rst { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { module_led_pins: module-led-pins { rockchip,pins = -- cgit v1.2.3 From 9c68a9483e31a9ad25c5399bb5f066b2e4980ad5 Mon Sep 17 00:00:00 2001 From: Raphaël Jakse Date: Sun, 30 Nov 2025 17:12:59 +0100 Subject: arm64: dts: rockchip: Fix Bluetooth on the RockPro64 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The RockPro64 board has an optional BCM4345C5 Bluetooth device on UART0. This patch fixes audio stutters by setting its correct max-speed and compatible properties. Signed-off-by: Raphaël Jakse Link: https://patch.msgid.link/20251130161259.9828-1-raphael.kernel@jakse.fr Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts | 7 +++++++ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts index 304e3c51391c..883d9bcfe792 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts @@ -28,3 +28,10 @@ }; }; }; + +&uart0 { + bluetooth { + compatible = "brcm,bcm4345c5"; + max-speed = <1500000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index 4b42717800f7..ae3ee91dba2f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -28,3 +28,10 @@ }; }; }; + +&uart0 { + bluetooth { + compatible = "brcm,bcm4345c5"; + max-speed = <1500000>; + }; +}; -- cgit v1.2.3 From 7beae528ddadd1c3f7d5670f937d993b0f39e0ea Mon Sep 17 00:00:00 2001 From: Joseph Kogut Date: Fri, 5 Dec 2025 12:07:01 +0000 Subject: dt-bindings: arm: rockchip: Add Radxa CM5 IO board Add device tree binding for the Radxa CM5 IO board. This board is based on the rk3588s. Signed-off-by: Joseph Kogut Reviewed-by: Krzysztof Kozlowski Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251205120703.14721-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index d496421dbd87..79e99694577e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -907,6 +907,13 @@ properties: - const: radxa,cm3 - const: rockchip,rk3566 + - description: Radxa Compute Module 5 (CM5) + items: + - enum: + - radxa,cm5-io + - const: radxa,cm5 + - const: rockchip,rk3588s + - description: Radxa CM3 Industrial items: - enum: -- cgit v1.2.3 From 36ee19ba42dcebe6a15ec6b442a7d32eb327eee4 Mon Sep 17 00:00:00 2001 From: Joseph Kogut Date: Fri, 5 Dec 2025 12:07:02 +0000 Subject: arm64: dts: rockchip: Add rk3588 based Radxa CM5 Add initial support for the Radxa Compute Module 5 (CM5). The CM5 uses a proprietary connector. Specification: - Rockchip RK3588 - Up to 32 GB LPDDR4X - Up to 128 GB eMMC - 1x HDMI TX up to 8k@60 hz - 1x eDP TX up to 4k@60 hz - Gigabit Ethernet PHY Signed-off-by: Joseph Kogut Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251205120703.14721-3-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi | 280 +++++++++++++++++++++ 1 file changed, 280 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi new file mode 100644 index 000000000000..d307e19052c6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Joseph Kogut + */ + +/* + * CM5 data sheet + * https://dl.radxa.com/cm5/v2210/radxa_cm5_v2210_schematic.pdf + */ + +#include +#include +#include +#include + +/ { + compatible = "radxa,cm5", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + }; + + leds { + compatible = "gpio-leds"; + + led_sys: led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus + &gmac1_clkinout>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vdd2_ddr_s3>; + vcc14-supply = <&vdd2_ddr_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + }; + }; +}; -- cgit v1.2.3 From 51babf83f424a695179183204226d453c8af7dc7 Mon Sep 17 00:00:00 2001 From: Joseph Kogut Date: Fri, 5 Dec 2025 12:07:03 +0000 Subject: arm64: dts: rockchip: Add support for CM5 IO carrier Specification: - 1x HDMI - 2x MIPI DSI - 2x MIPI CSI - 1x eDP - 1x M.2 E key - 1x USB 3.0 Host - 1x USB 3.0 OTG - 2x USB 2.0 Host - Headphone jack w/ microphone - Gigabit Ethernet w/ PoE - microSD slot - 40-pin expansion header - 12V DC Signed-off-by: Joseph Kogut Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251205120703.14721-4-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-radxa-cm5-io.dts | 339 +++++++++++++++++++++ 2 files changed, 340 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 3fdd1e4832e1..105dae928f97 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -210,6 +210,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts new file mode 100644 index 000000000000..f80d5a00a4bd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Joseph Kogut + */ + +/* + * CM5 IO board data sheet + * https://dl.radxa.com/cm5/v2200/radxa_cm5_io_v2200_schematic.pdf + */ + +/dts-v1/; +#include "rk3588s.dtsi" +#include "rk3588s-radxa-cm5.dtsi" + +/ { + model = "Radxa Compute Module 5 (CM5) IO Board"; + compatible = "radxa,cm5-io", "radxa,cm5", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + vcc12v_dcin: regulator-12v0-vcc-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: regulator-3v3-vcc-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s0: pldo-reg4 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + fusb302: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <1000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orientation_switch: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + usbc0_role_switch: endpoint { + remote-endpoint = <&usb_host0_xhci_role_switch>; + }; + }; + + port@2 { + reg = <2>; + usbc0_dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + fusb302 { + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + sd-uhs-sdr104; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb_host0_xhci_role_switch: endpoint { + remote-endpoint = <&usbc0_role_switch>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orientation_switch>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_dp_altmode_mux>; + }; + }; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; -- cgit v1.2.3 From 2b8cd99c8cf489d539e1347adb5fd39548c53f19 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 25 Dec 2025 19:43:19 -0800 Subject: arm64: dts: rockchip: Add magnetometer sensor to Pinephone Pro Pinephone Pro uses AF8133J according to the schematic. The mount-matrix was added by Leonardo on top of Ondrej's work of adding the magnetometer. It was verified with Leonardo's compass app: https://gitlab.com/lgtrombetta/compass Co-developed-by: Leonardo G. Trombetta Signed-off-by: Leonardo G. Trombetta Signed-off-by: Ondrej Jirman Reviewed-by: Pavel Machek Signed-off-by: Rudraksha Gupta Link: https://patch.msgid.link/20251225-ppp_light_accel_mag_vol-down-v6-1-8c79a4e87001@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-pinephone-pro.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 5e9867e934d2..a100fb96c8a5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -543,6 +543,23 @@ }; }; +&i2c4 { + af8133j: compass@1c { + compatible = "voltafield,af8133j"; + reg = <0x1c>; + avdd-supply = <&vcc_3v0>; + dvdd-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&compass_rst_l>; + reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; + + mount-matrix = + "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; +}; + &io_domains { bt656-supply = <&vcc1v8_dvp>; audio-supply = <&vcca1v8_codec>; @@ -655,6 +672,12 @@ }; }; + compass { + compass_rst_l: compass-rst-l { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { red_led_pin: red-led-pin { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -- cgit v1.2.3 From a3e4bb6c9a2262c87a842d9fa42bdd65a1671edf Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 25 Dec 2025 19:43:20 -0800 Subject: arm64: dts: rockchip: Add light/proximity sensor to Pinephone Pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pinephone Pro uses STK3311 according to the schematics. Tests: ~ $ monitor-sensor --light // When the sensor is exposed, it get's fluctating values such as Light changed: 1.800000 (lux) Light changed: 1.700000 (lux) Light changed: 1.800000 (lux) Light changed: 1.700000 (lux) Light changed: 1.600000 (lux) Light changed: 1.100000 (lux) // When covering the sensor, it prints a low value and stops printing Light changed: 0.200000 (lux) ~ $ monitor-sensor --proximity // When it goes away from an object Proximity value changed: 0 // When it comes near an object Proximity value changed: 1 Co-developed-by: Martijn Braam Signed-off-by: Martijn Braam Co-developed-by: Kamil Trzciński Signed-off-by: Kamil Trzciński Signed-off-by: Ondrej Jirman Signed-off-by: Rudraksha Gupta Link: https://patch.msgid.link/20251225-ppp_light_accel_mag_vol-down-v6-2-8c79a4e87001@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index a100fb96c8a5..141ab9850290 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -520,6 +520,16 @@ touchscreen-size-x = <720>; touchscreen-size-y = <1440>; }; + + light-sensor@48 { + compatible = "sensortek,stk3311"; + reg = <0x48>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&light_int_l>; + proximity-near-level = <300>; + }; }; &i2c4 { @@ -718,6 +728,12 @@ }; }; + stk3311 { + light_int_l: light-int-l { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_input_pull_up>; + }; + }; + wifi { wifi_host_wake_l: wifi-host-wake-l { rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; -- cgit v1.2.3 From cd50298ffc5f98872ddf0ac05c51a014003a34b7 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 30 Dec 2025 17:23:34 +0400 Subject: arm64: dts: rockchip: enable UFS controller on FriendlyElec NanoPi M5 The NanoPi M5 board supports pluggable UFS modules using the UFSHC inside its Rockchip RK3576 SoC. Enable the respective devicetree node and add its supply regulators. Link: https://wiki.friendlyelec.com/wiki/images/9/97/NanoPi_M5_LP5_2411_SCH.pdf Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251230-nanopi-m5-ufs-v3-1-ed188ae34fdb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts index cce34c541f7c..af4b7c004c38 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -110,6 +110,22 @@ regulator-name = "vcc12v_dcin"; }; + vcc1v2_ufs_vccq: regulator-vcc1v2-ufs-vccq { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc1v2_ufs_vccq"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc1v8_ufs_vccq2: regulator-vcc1v8-ufs-vccq2 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_ufs_vccq2"; + vin-supply = <&vcc_1v8_s3>; + }; + vcc3v3_m2_keym: regulator-vcc3v3-m2-keym { compatible = "regulator-fixed"; enable-active-high; @@ -906,6 +922,14 @@ status = "okay"; }; +&ufshc { + vcc-supply = <&vcc_3v3_s3>; + vccq-supply = <&vcc1v2_ufs_vccq>; + vccq2-supply = <&vcc1v8_ufs_vccq2>; + vdd-hba-supply = <&vdda_1v2_s0>; + status = "okay"; +}; + &usbdp_phy { status = "okay"; }; -- cgit v1.2.3 From 7127b6d899c74a2ba7af09f1755a22cf9c72dba9 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 1 Jan 2026 07:43:09 +0100 Subject: arm64: dts: rockchip: Enable the NPU on NanoPC T6/T6-LTS Enable the NPU on FriendlyElec NanoPC T6/T6-LTS boards. The regulator vdd_npu_s0 was already in place; since the NPU power domain supply is now described, remove the regulator's always-on. Signed-off-by: Ricardo Pardini Link: https://patch.msgid.link/20260101-arm64-dts-rockchip-rk3588-npu-enablements-v2-1-013cf5d5c39d@pardini.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 36 +++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index fafeabe9adf9..90e7fe254491 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -458,7 +458,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -629,6 +628,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { gpio-leds { sys_led_pin: sys-led-pin { @@ -706,6 +709,37 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; -- cgit v1.2.3 From 628aea397d81cbec3f2ff9067c5223c927f220a2 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 1 Jan 2026 07:43:10 +0100 Subject: arm64: dts: rockchip: Enable the NPU on FriendlyElec CM3588 Enable the NPU on FriendlyElec CM3588. The regulator vdd_npu_s0 was already in place; since the NPU power domain supply is now described, remove the regulator's always-on. Signed-off-by: Ricardo Pardini Link: https://patch.msgid.link/20260101-arm64-dts-rockchip-rk3588-npu-enablements-v2-2-013cf5d5c39d@pardini.net Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588-friendlyelec-cm3588.dtsi | 35 +++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi index af431fdcbea7..49cf4b85c4e9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -182,7 +182,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -264,6 +263,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { @@ -294,6 +297,36 @@ }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; -- cgit v1.2.3 From 5360ad495b7bf1e3ea95f0e47961d5447a829f8e Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 1 Jan 2026 07:43:11 +0100 Subject: arm64: dts: rockchip: Enable the NPU on Turing RK1 Enable the NPU on Turing RK1. The regulator vdd_npu_s0 was already in place; since the NPU power domain supply is now described, remove the regulator's always-on. Signed-off-by: Ricardo Pardini Link: https://patch.msgid.link/20260101-arm64-dts-rockchip-rk3588-npu-enablements-v2-3-013cf5d5c39d@pardini.net Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 35 +++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6daea8961fdd..b11d24dcc180 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -171,7 +171,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -293,6 +292,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { fan { fan_int: fan-int { @@ -333,6 +336,36 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; -- cgit v1.2.3 From f01f0e0700740dc7a2e5ed1af89d9770c1127d2e Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 6 Jan 2026 18:00:00 +0800 Subject: arm64: dts: rockchip: Enable PCIe for ArmSoM Sige1 Enable the RTL8125 network controller and corresponding PHY connected via PCIe on the ArmSoM Sige1. Signed-off-by: Chukun Pan Reviewed-by: Jonas Karlman Link: https://patch.msgid.link/20260106100000.225445-1-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts index 6e21579365a5..c41af8fc0c8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -232,6 +232,10 @@ }; }; +&combphy { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -293,6 +297,14 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_perstn>; + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + &pinctrl { bluetooth { bt_reg_on_h: bt-reg-on-h { @@ -324,6 +336,12 @@ }; }; + pcie { + pcie20_perstn: pcie20-perstn { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + rtc { rtc_int_l: rtc-int-l { rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; -- cgit v1.2.3 From 77712fe6847b2471a558ec88868311a4784afdce Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:32:44 -0600 Subject: arm64: dts: rockchip: Add missing everest,es8388 supplies to rk3399-roc-pc-plus The regulator supplies for everest,es8388 audio codec are missing and are required. Add them based on the schematics found here: https://personalbsd.org/download/Documents/SCH/ROC-RK3399-PC-PLUS-V20-20210809.pdf With this, "regulator-always-on" should no longer be necessary for LDO5. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260105193245.3167500-1-robh@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts index 8e3858cf988c..4f2831097624 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts @@ -116,6 +116,10 @@ reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; #sound-dai-cells = <0>; + AVDD-supply = <&vcca3v0_codec>; + DVDD-supply = <&vcca1v8_codec>; + HPVDD-supply = <&vcca3v0_codec>; + PVDD-supply = <&vcca1v8_codec>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index fc9279627ef6..ac62e8f5d9f5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -408,7 +408,6 @@ vcca3v0_codec: LDO_REG5 { regulator-name = "vcca3v0_codec"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; -- cgit v1.2.3 From a1823b88d35f1bf04ec4e4f86b9206f699b362d0 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 29 Dec 2025 04:58:37 +0000 Subject: dt-bindings: arm: rockchip: fix description for Radxa CM3I "Radxa CM3I" is the correct name[1], so fix the description. [1] https://dl.radxa.com/cm3i/docs/hw/radxa_cm3i_product_brief.pdf Signed-off-by: FUKAUMI Naoki Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251229045838.2917-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 79e99694577e..410a9715a0fc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -914,7 +914,7 @@ properties: - const: radxa,cm5 - const: rockchip,rk3588s - - description: Radxa CM3 Industrial + - description: Radxa CM3I items: - enum: - radxa,e25 -- cgit v1.2.3 From fc808f80cf298caaa403755ca808cf650844f2f5 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 29 Dec 2025 04:58:38 +0000 Subject: dt-bindings: arm: rockchip: fix description for Radxa CM5 "Radxa CM5" is the correct name[1], so fix the description. While at it, move the CM5 entry after the CM3I. [1] https://dl.radxa.com/cm5/radxa_cm5_product_brief.pdf Signed-off-by: FUKAUMI Naoki Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251229045838.2917-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 410a9715a0fc..59a7aed538b4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -907,13 +907,6 @@ properties: - const: radxa,cm3 - const: rockchip,rk3566 - - description: Radxa Compute Module 5 (CM5) - items: - - enum: - - radxa,cm5-io - - const: radxa,cm5 - - const: rockchip,rk3588s - - description: Radxa CM3I items: - enum: @@ -921,6 +914,13 @@ properties: - const: radxa,cm3i - const: rockchip,rk3568 + - description: Radxa CM5 + items: + - enum: + - radxa,cm5-io + - const: radxa,cm5 + - const: rockchip,rk3588s + - description: Radxa E20C items: - const: radxa,e20c -- cgit v1.2.3 From 8fd18d9b7b74bbd5ee5c562c2b94fdb7a356867e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 12 Aug 2025 10:52:12 +0200 Subject: arm64: dts: rockchip: enable NPU on rk3588-tiger Enable the NPU cores and their mmus and wire up the supply-regulator. The regulator itself was already defined, but it does not need to be always on - the npu can control it. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Tested-by: Quentin Schulz Link: https://patch.msgid.link/20250812085213.1071106-1-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 35 +++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 365c1d958f2d..27269b7b08aa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -197,7 +197,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -340,6 +339,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -372,6 +375,36 @@ pinctrl-names = "default"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; -- cgit v1.2.3 From 843b912c7241ed0259f6234243da05e10ce67c0f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 12 Aug 2025 10:52:13 +0200 Subject: arm64: dts: rockchip: enable NPU on rk3588-jaguar Enable the NPU cores and their mmus and wire up the supply-regulator. The regulator itself was already defined, but it does not need to be always on - the npu can control it. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Tested-by: Quentin Schulz Link: https://patch.msgid.link/20250812085213.1071106-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 35 +++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 176925d0a1a8..952affaf455c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -393,7 +393,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -564,6 +563,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -618,6 +621,36 @@ }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; -- cgit v1.2.3 From 309598fca339abd4e8eef0efe0d630714ca79ac9 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:00 +0400 Subject: arm64: dts: rockchip: Use a readable audio card name on NanoPi M5 'simple-audio-card,name' ends up in user visible places such as ALSA mixer names, so use a more human-readable name instead of realtek,rt5616-codec Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-3-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts index af4b7c004c38..9cb5acb555d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -220,7 +220,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,hp-det-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,name = "Onboard Analog RT5616"; simple-audio-card,routing = "Headphones", "HPOL", -- cgit v1.2.3 From bde555926b61740c6256a38a9cf5a4833be345cc Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:01 +0400 Subject: arm64: dts: rockchip: Enable HDMI sound on FriendlyElec NanoPi M5 All RK3576 boards get their HDMI sound from SAI6, which is internally connected to the HDMI codec. Enable this for FriendlyElec NanoPi M5. Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-4-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts index 9cb5acb555d8..959ea96b313f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -340,6 +340,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -864,6 +868,10 @@ status = "okay"; }; +&sai6 { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8_s0>; status = "okay"; -- cgit v1.2.3 From 87af7643234a2b4cb49a97dfe7fb455633b3185d Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:02 +0400 Subject: arm64: dts: rockchip: Enable HDMI sound on Luckfox Core3576 All RK3576 boards get their HDMI sound from SAI6, which is internally connected to the HDMI codec. Enable this for Luckfox Core3576 Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-5-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi index 9187012d6fa4..749f0a54b478 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi @@ -246,6 +246,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -691,6 +695,10 @@ status = "okay"; }; +&sai6 { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8_s0>; status = "okay"; -- cgit v1.2.3 From f5c9549964adbac931e163693bd17db872976679 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:03 +0400 Subject: arm64: dts: rockchip: Enable HDMI sound on RK3576 EVB1 All RK3576 boards get their HDMI sound from SAI6, which is internally connected to the HDMI codec. Enable this for Rockchip RK3576 EVB1 Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-6-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index db8fef7a4f1b..deab20ff4d97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -315,6 +315,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -835,6 +839,10 @@ }; }; +&sai6 { + status = "okay"; +}; + &sdhci { bus-width = <8>; full-pwr-cycle-in-suspend; -- cgit v1.2.3 From d8872b9dd9208c493f1f3811d42997fb968de064 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:04 +0400 Subject: arm64: dts: rockchip: Enable analog sound on RK3576 EVB1 Rockchip RK3576 EVB1 board uses the typical configuration with an ES8388 analog codec driven from built-in SAI I2S. Add device tree nodes for it. Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-7-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 99 ++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index deab20ff4d97..0789733c2073 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -246,6 +246,63 @@ regulator-max-microvolt = <1800000>; vin-supply = <&vcc_1v8_s3>; }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + simple-audio-card,name = "On-board Analog ES8388"; + simple-audio-card,aux-devs = <&hp_power>, <&spk_power>; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&masterdai>; + simple-audio-card,hp-det-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = + "Headphone Power INL", "LOUT1", + "Headphone Power INR", "ROUT1", + "Speaker Power INL", "LOUT2", + "Speaker Power INR", "ROUT2", + "Headphones", "Headphone Power OUTL", + "Headphones", "Headphone Power OUTR", + "Speaker", "Speaker Power OUTL", + "Speaker", "Speaker Power OUTR", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + simple-audio-card,widgets = + "Microphone", "Main Mic", + "Microphone", "Headset Mic", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + hp_power: headphone-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_ctl>; + sound-name-prefix = "Headphone Power"; + }; + + spk_power: speaker-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctl>; + sound-name-prefix = "Speaker Power"; + VCC-supply = <&vcc5v0_device>; + }; }; &cpu_l0 { @@ -712,6 +769,25 @@ }; }; +&i2c3 { + status = "okay"; + + es8388: audio-codec@10 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + AVDD-supply = <&vcca_3v3_s0>; + DVDD-supply = <&vcc_1v8_s0>; + HPVDD-supply = <&vcca_3v3_s0>; + PVDD-supply = <&vcc_1v8_s0>; + assigned-clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + assigned-clock-rates = <12288000>; + clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_mclk>; + #sound-dai-cells = <0>; + }; +}; + &mdio0 { rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; @@ -778,6 +854,20 @@ }; &pinctrl { + audio { + hp_det: hp-det { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hp_ctl: hp-ctl { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + spk_ctl: spk-ctl { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + bluetooth { bt_reg_on: bt-reg-on { rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; @@ -839,6 +929,15 @@ }; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; + status = "okay"; +}; + &sai6 { status = "okay"; }; -- cgit v1.2.3 From 97a9b5edcdd4179063773f17a00904a464b8aa7c Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 19 Nov 2025 16:55:26 -0600 Subject: arm64: dts: rockchip: Add HDMI to Gameforce Ace Add support for the HDMI port for the Gameforce Ace. The HDMI port has no HPD pin present (the manufacturer's devicetree states the pin is reused for an additional face button) so add the attribute of no-hpd to poll for connected devices. Signed-off-by: Chris Morgan Link: https://patch.msgid.link/20251119225526.70588-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-gameforce-ace.dts | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 21eb003198fe..e8ad525ba3f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -300,6 +300,20 @@ sound-name-prefix = "Headphones Amplifier"; }; + hdmi0-con { + compatible = "hdmi-connector"; + ddc-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdmi0_en>; + pinctrl-names = "default"; + type = "d"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + pwm_fan: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; @@ -498,6 +512,34 @@ status = "okay"; }; +&hdmi0 { + no-hpd; + pinctrl-0 = <&hdmim0_tx0_cec>, <&hdmim0_tx0_scl>, + <&hdmim0_tx0_sda>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; pinctrl-names = "default"; @@ -746,6 +788,10 @@ status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &mipidcphy0 { status = "okay"; }; @@ -846,6 +892,13 @@ }; }; + hdmi { + hdmi0_en: hdmi0-en { + rockchip,pins = + <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = @@ -1450,6 +1503,16 @@ status = "okay"; }; +&vp0 { + #address-cells = <1>; + #size-cells = <0>; + + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + &vp3 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From a770eb1f3219dfc4c28dac66c96735fa8acba4e6 Mon Sep 17 00:00:00 2001 From: David Petry Date: Tue, 21 Oct 2025 18:06:02 +0200 Subject: arm64: dts: rockchip: Enable second HDMI output on CM3588 Enable the second HDMI output port found on FriendlyElec CM3588 and CM3588 Plus Signed-off-by: David Petry Link: https://patch.msgid.link/20251021160603.96934-1-petry103@gmail.com Signed-off-by: Heiko Stuebner --- .../rockchip/rk3588-friendlyelec-cm3588-nas.dts | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts index 5fbbeb6f5a93..10a7d3691a26 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -101,6 +101,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; @@ -335,6 +346,22 @@ }; }; +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + &hdmi_receiver_cma { status = "okay"; }; @@ -350,6 +377,10 @@ status = "okay"; }; +&hdptxphy1 { + status = "okay"; +}; + /* Connected to MIPI-DSI0 */ &i2c5 { pinctrl-names = "default"; @@ -840,3 +871,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; -- cgit v1.2.3 From 5d719a4703566267492129d13516d87066f288f8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 27 Oct 2025 23:56:35 +0200 Subject: dt-bindings: arm: rockchip: Add Orange Pi CM5 Base The Orange Pi CM5 Base board is a carrier board for the Orange Pi CM5 compute module. It has 3 ethernet ports, 2 USB ports, one HDMI output and 4 CSI-2 inputs. Signed-off-by: Laurent Pinchart Acked-by: Conor Dooley Link: https://patch.msgid.link/20251027215637.20715-2-laurent.pinchart@ideasonboard.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 59a7aed538b4..c9b078be3a90 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1306,6 +1306,12 @@ properties: - xunlong,orangepi-5b - const: rockchip,rk3588s + - description: Xunlong Orange Pi CM5 + items: + - const: xunlong,orangepi-cm5-base + - const: xunlong,orangepi-cm5 + - const: rockchip,rk3588s + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 -- cgit v1.2.3 From 3cdaec4d5e8c24ce3298c93bac80c31820b91aff Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 27 Oct 2025 23:56:36 +0200 Subject: arm64: dts: rockchip: Add rk3588s-orangepi-cm5-base device tree The Orange Pi CM5 Base board is a carrier board for the Orange Pi CM5 compute module. It has 3 ethernet ports, 2 USB ports, one HDMI output and 4 CSI-2 inputs. The device tree is split in two files, a .dtsi for the compute module and a .dts for the carrier board. All the devices present on the carrier board are enabled and tested, with the exception of the IR receiver due to missing support for input capture in the PWM device's DT binding (and driver). This work is based on a combination of the Orange Pi 5 device tree from the upstream kernel and the Orange Pi CM5 device tree from the BSP kernel. All nodes and properties have been carefully checked to the best of my abilities against the schematics of the carrier board. The schematics of the compute module is not available publicly, so the configuration of the PMIC hasn't been double-checked. Signed-off-by: Laurent Pinchart Link: https://patch.msgid.link/20251027215637.20715-3-laurent.pinchart@ideasonboard.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588s-orangepi-cm5-base.dts | 355 ++++++++++++++++ .../boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi | 472 +++++++++++++++++++++ 3 files changed, 828 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 105dae928f97..a02510bb9c48 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -210,6 +210,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-cm5-base.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts new file mode 100644 index 000000000000..06120b2db690 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +#include "rk3588s-orangepi-cm5.dtsi" + +/ { + model = "Xunlong Orange Pi CM5 Base"; + compatible = "xunlong,orangepi-cm5-base", "xunlong,orangepi-cm5", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button { + debounce-interval = <50>; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + label = "USERKEY"; + linux,code = ; + wakeup-source; + }; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + max-brightness = <255>; + pwms = <&pwm2 0 25000 0>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_WAN; + max-brightness = <255>; + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + max-brightness = <255>; + pwms = <&pwm5 0 25000 PWM_POLARITY_INVERTED>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; + }; + }; + + vbus_5v0: regulator-vbus-5v0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_5v0_en_pin>; + regulator-name = "vbus_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3v3_en_pin>; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_rx_bus2 + &gmac1_tx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + status = "okay"; +}; + +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda + &hdmi_frl_pin>; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_pin>; + wakeup-source; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + /* YT8531C */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy_pin>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pinctrl { + camera { + cam1_reset_pin: cam1-reset-pin { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam2_reset_pin: cam2-reset-pin { + rockchip,pins = <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam3_reset_pin: cam3-reset-pin { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam4_reset_pin: cam4-reset-pin { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + rgmii_phy_pin: rgmii-phy-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + hdmi_frl_pin: hdmi-frl-pin { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + power { + vcc_3v3_en_pin: vcc-3v3-en-pin { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtc { + rtc_int_pin: rtc-int-pin { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vbus_5v0_en_pin: vbus-5v0-en-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +&pwm6 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus_5v0>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vbus_5v0>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi new file mode 100644 index 000000000000..32357eba4b78 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include + +#include "rk3588s.dtsi" +#include "rk8xx.h" + +/ { + aliases { + mmc0 = &sdhci; + }; + + /* Can't be verified due to missing schematics for the CM5. */ + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + rockchip,reset-mode = ; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + /* + * The TSADC_SHUT pin is exposed to carrier boards as a signal named + * PMIC_RESET_L, meant to be driven externally. Reference carrier + * boards connect it to a reset button that pulls the signal to GND + * through a 100Ω resistor. This is too weak to overcome even the + * minimum drive strength of the TSADC_SHUT pin when driven in + * push-pull mode. Configure it as a GPIO, reset will be generated + * through the CRU. + */ + pinctrl-0 = <&tsadc_gpio_func>; + status = "okay"; +}; -- cgit v1.2.3 From f61731bd60627b129b688c2d7b2071a5fe7f01d7 Mon Sep 17 00:00:00 2001 From: Detlev Casanova Date: Mon, 20 Oct 2025 17:20:08 -0400 Subject: arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588 Add the vdpu381 Video Decoders to the rk3588-base devicetree. The RK3588 based SoCs all embed 2 vdpu381 decoders. This also adds the dedicated IOMMU controllers. Signed-off-by: Detlev Casanova Link: https://patch.msgid.link/20251020212009.8852-2-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 2a7921793020..aa74e8d7b4e9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1353,6 +1353,70 @@ #iommu-cells = <0>; }; + vdec0: video-codec@fdc38000 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdc38100 0x0 0x500>, + <0x0 0xfdc38000 0x0 0x100>, + <0x0 0xfdc38600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = ; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus = <&vdec0_mmu>; + power-domains = <&power RK3588_PD_RKVDEC0>; + resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&vdec0_sram>; + }; + + vdec0_mmu: iommu@fdc38700 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RKVDEC0>; + #iommu-cells = <0>; + }; + + vdec1: video-codec@fdc40000 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdc40100 0x0 0x500>, + <0x0 0xfdc40000 0x0 0x100>, + <0x0 0xfdc40600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = ; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus = <&vdec1_mmu>; + power-domains = <&power RK3588_PD_RKVDEC1>; + resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&vdec1_sram>; + }; + + vdec1_mmu: iommu@fdc40700 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RKVDEC1>; + #iommu-cells = <0>; + }; + av1d: video-codec@fdc70000 { compatible = "rockchip,rk3588-av1-vpu"; reg = <0x0 0xfdc70000 0x0 0x800>; @@ -3249,6 +3313,16 @@ ranges = <0x0 0x0 0xff001000 0xef000>; #address-cells = <1>; #size-cells = <1>; + + vdec0_sram: codec-sram@0 { + reg = <0x0 0x78000>; + pool; + }; + + vdec1_sram: codec-sram@78000 { + reg = <0x78000 0x77000>; + pool; + }; }; pinctrl: pinctrl { -- cgit v1.2.3 From da0de806d8b46238ac3891a894806da4d1c26cdf Mon Sep 17 00:00:00 2001 From: Detlev Casanova Date: Mon, 20 Oct 2025 17:20:09 -0400 Subject: arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576 Add the vdpu383 Video Decoder variant to the RK3576 device tree. Also allow using the dedicated SRAM as a pool. Signed-off-by: Detlev Casanova Link: https://patch.msgid.link/20251020212009.8852-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 792857aee4f7..7286d968e2b0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1279,6 +1279,41 @@ status = "disabled"; }; + vdec: video-codec@27b00000 { + compatible = "rockchip,rk3576-vdec"; + reg = <0x0 0x27b00100 0x0 0x500>, + <0x0 0x27b00000 0x0 0x100>, + <0x0 0x27b00600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = ; + clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <600000000>, <600000000>, + <500000000>, <1000000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3576_PD_VDEC>; + resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, + <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&rkvdec_sram>; + }; + + vdec_mmu: iommu@27b00800 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; + interrupts = ; + clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3576_PD_VDEC>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + }; + vop: vop@27d00000 { compatible = "rockchip,rk3576-vop"; reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; @@ -2684,6 +2719,7 @@ /* start address and size should be 4k align */ rkvdec_sram: rkvdec-sram@0 { reg = <0x0 0x78000>; + pool; }; }; -- cgit v1.2.3