From 7b7c66ec81d80581939d3d774491acd761808f20 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 10 Aug 2022 14:10:37 +0300 Subject: ARM: dts: ste: ux500: align SPI node name with dtschema The node names should be generic and DT schema expects certain pattern. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220810111037.280959-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts | 2 +- arch/arm/boot/dts/ste-ux500-samsung-codina.dts | 2 +- arch/arm/boot/dts/ste-ux500-samsung-gavini.dts | 2 +- arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts index d6940e0afa86..17dff403f77a 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -239,7 +239,7 @@ }; }; - spi-gpio-0 { + spi { compatible = "spi-gpio"; /* Clock on GPIO220, pin SCL */ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 5f41256d7f4b..9db490cc395b 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -325,7 +325,7 @@ }; }; - spi-gpio-0 { + spi { compatible = "spi-gpio"; /* Clock on GPIO220, pin SCL */ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 806da3fc33cd..79d43fc68cd8 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -269,7 +269,7 @@ /* * TODO: See if we can use the PL023 for this instead. */ - spi-gpio-0 { + spi { compatible = "spi-gpio"; /* Clock on GPIO220, pin SCL */ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index ed5c79c3d04b..b34bd19ad815 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -263,7 +263,7 @@ * this derivative is 3wire support, so it cannot be used to drive * this panel interface. We have to use GPIO bit-banging instead. */ - spi-gpio-0 { + spi { compatible = "spi-gpio"; /* Clock on GPIO220 */ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3 From 7341b2c1b9c8997ffb87b5bfdb8feaf02b52d8bf Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 15 Aug 2022 21:34:40 +0200 Subject: ARM: dts: ux500: Fix up the Janice NFC chip The NFC chip in Janice is a PNX544 not PNX547 and it is on I2C address 0x2b. Fix it up. This is only mounted in Janice models designated GT-I9070P. Cc: Stefan Hansson Link: https://lore.kernel.org/r/20220815193440.388695-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index b34bd19ad815..04cd3c3757d6 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -365,9 +365,13 @@ #address-cells = <1>; #size-cells = <0>; - nfc@30 { - compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; - reg = <0x30>; + /* This is only mounted on the GT-I9070P */ + nfc@2b { /* 0x30? */ + /* NXP NFC circuit PN544 C1 marked NXP 44501 */ + compatible = "nxp,pn544-i2c"; + /* IF0, IF1 high, gives I2C address 0x2B */ + reg = <0x2b>; + clock-frequency = <400000>; /* NFC IRQ on GPIO32 */ interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; @@ -376,7 +380,7 @@ /* GPIO88 */ enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pn547_janice_default>; + pinctrl-0 = <&pn544_janice_default>; }; }; @@ -951,7 +955,7 @@ }; }; nfc { - pn547_janice_default: pn547_janice { + pn544_janice_default: pn544_janice { /* Interrupt line */ janice_cfg1 { pins = "GPIO32_V2"; -- cgit v1.2.3 From a26b17fa52294c0f92e6b0f5a471649467f07af2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 21 Jul 2022 17:36:10 +0200 Subject: ARM: dts: DBx500 cryp and hash uses power domain The cryp and hash blocks of the DBx500 uses the VAPE power domain, the special regulator is a leftover that is not used anymore. Link: https://lore.kernel.org/r/20220721153610.1053845-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 9afe8301bd47..a42a4fd69299 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1149,17 +1149,15 @@ compatible = "stericsson,ux500-cryp"; reg = <0xa03cb000 0x1000>; interrupts = ; - - v-ape-supply = <&db8500_vape_reg>; clocks = <&prcc_pclk 6 1>; + power-domains = <&pm_domains DOMAIN_VAPE>; }; hash@a03c2000 { compatible = "stericsson,ux500-hash"; reg = <0xa03c2000 0x1000>; - - v-ape-supply = <&db8500_vape_reg>; clocks = <&prcc_pclk 6 2>; + power-domains = <&pm_domains DOMAIN_VAPE>; }; }; }; -- cgit v1.2.3 From 1e15c02cf8c8085d0e6e548bfa2ee0b2f6231221 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 15 Aug 2022 22:30:44 +0200 Subject: ARM: dts: ux500: Add GPS to the Kyle This adds the GPS chip to the Kyle device tree. Link: https://lore.kernel.org/r/20220815203044.468686-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-kyle.dts | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts index c57676faf181..e6a7d608e326 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts @@ -307,6 +307,21 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ + compatible = "csr,csrg05ta03-icje-r"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&g05ta03_kyle_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to AB8505 USB */ @@ -666,6 +681,20 @@ }; }; }; + g05ta03 { + g05ta03_kyle_default: g05ta03 { + /* Reset line, start out de-asserted */ + kyle_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_hi>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + kyle_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; }; &ab8505_gpio { -- cgit v1.2.3