From 978400b7a68f19d09ef3767b69447f855bd5ea43 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 16 Jan 2026 22:43:53 +0100 Subject: arm64: dts: qcom: monaco: Complete SDHC definition Add the missing SDHC properties required to enable HS200, HS400, and HS400 Enhanced Strobe modes, as supported by this controller. Select the proper default pinctrls. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260116214354.256878-2-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 5d2df4305d1c..12333709206c 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4740,11 +4740,21 @@ interconnect-names = "sdhc-ddr", "cpu-sdhc"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + qcom,dll-config = <0x000f64ee>; qcom,ddr-config = <0x80040868>; + bus-width = <8>; supports-cqe; dma-coherent; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "disabled"; sdhc1_opp_table: opp-table { -- cgit v1.2.3