From f65ca6c5117981784943eb3fe9ba4e11e85746ea Mon Sep 17 00:00:00 2001 From: Marco Crivellari Date: Thu, 13 Nov 2025 17:06:05 +0100 Subject: wifi: rtw88: add WQ_PERCPU to alloc_workqueue users MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently if a user enqueues a work item using schedule_delayed_work() the used wq is "system_wq" (per-cpu wq) while queue_delayed_work() use WORK_CPU_UNBOUND (used when a cpu is not specified). The same applies to schedule_work() that is using system_wq and queue_work(), that makes use again of WORK_CPU_UNBOUND. This lack of consistency cannot be addressed without refactoring the API. For more details see the Link tag below. alloc_workqueue() treats all queues as per-CPU by default, while unbound workqueues must opt-in via WQ_UNBOUND. This default is suboptimal: most workloads benefit from unbound queues, allowing the scheduler to place worker threads where they’re needed and reducing noise when CPUs are isolated. This continues the effort to refactor workqueue APIs, which began with the introduction of new workqueues and a new alloc_workqueue flag in: commit 128ea9f6ccfb ("workqueue: Add system_percpu_wq and system_dfl_wq") commit 930c2ea566af ("workqueue: Add new WQ_PERCPU flag") This change adds a new WQ_PERCPU flag to explicitly request alloc_workqueue() to be per-cpu when WQ_UNBOUND has not been specified. With the introduction of the WQ_PERCPU flag (equivalent to !WQ_UNBOUND), any alloc_workqueue() caller that doesn’t explicitly specify WQ_UNBOUND must now use WQ_PERCPU. Once migration is complete, WQ_UNBOUND can be removed and unbound will become the implicit default. Suggested-by: Tejun Heo Signed-off-by: Marco Crivellari Link: https://lore.kernel.org/all/20250221112003.1dSuoGyc@linutronix.de/ Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20251113160605.381777-3-marco.crivellari@suse.com --- drivers/net/wireless/realtek/rtw88/usb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c index 3b5126ffc81a..db60e142268d 100644 --- a/drivers/net/wireless/realtek/rtw88/usb.c +++ b/drivers/net/wireless/realtek/rtw88/usb.c @@ -965,7 +965,8 @@ static int rtw_usb_init_rx(struct rtw_dev *rtwdev) struct sk_buff *rx_skb; int i; - rtwusb->rxwq = alloc_workqueue("rtw88_usb: rx wq", WQ_BH, 0); + rtwusb->rxwq = alloc_workqueue("rtw88_usb: rx wq", WQ_BH | WQ_PERCPU, + 0); if (!rtwusb->rxwq) { rtw_err(rtwdev, "failed to create RX work queue\n"); return -ENOMEM; -- cgit v1.2.3 From e497fc05e9f5c119aedf7b4e3780a6568a9b12e5 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Wed, 14 Jan 2026 09:39:39 +0800 Subject: wifi: rtw89: mac: clear global interrupt right after power-on The global interrupt indicator is always persistent, and firmware will handle it right after boot. To prevent this unnecessary handling, clear the indicator before downloading firmware. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-2-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/mac.c | 2 + drivers/net/wireless/realtek/rtw89/mac.h | 9 ++++ drivers/net/wireless/realtek/rtw89/mac_be.c | 10 +++++ drivers/net/wireless/realtek/rtw89/reg.h | 66 +++++++++++++++++++++++++++++ 4 files changed, 87 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c index 1435e4c664b6..4f0f17c499fa 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.c +++ b/drivers/net/wireless/realtek/rtw89/mac.c @@ -1554,6 +1554,7 @@ static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_TP_MAJOR); + rtw89_mac_clr_aon_intr(rtwdev); } else { clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); @@ -7303,6 +7304,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { .sys_init = sys_init_ax, .trx_init = trx_init_ax, .preload_init = preload_init_set_ax, + .clr_aon_intr = NULL, .err_imr_ctrl = err_imr_ctrl_ax, .mac_func_en = NULL, .hci_func_en = rtw89_mac_hci_func_en_ax, diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h index 14fffb660a29..784a1cf4c6f4 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.h +++ b/drivers/net/wireless/realtek/rtw89/mac.h @@ -1039,6 +1039,7 @@ struct rtw89_mac_gen_def { int (*trx_init)(struct rtw89_dev *rtwdev); int (*preload_init)(struct rtw89_dev *rtwdev, u8 mac_idx, enum rtw89_qta_mode mode); + void (*clr_aon_intr)(struct rtw89_dev *rtwdev); void (*err_imr_ctrl)(struct rtw89_dev *rtwdev, bool en); int (*mac_func_en)(struct rtw89_dev *rtwdev); void (*hci_func_en)(struct rtw89_dev *rtwdev); @@ -1251,6 +1252,14 @@ int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, return mac->check_mac_en(rtwdev, band, sel); } +static inline void rtw89_mac_clr_aon_intr(struct rtw89_dev *rtwdev) +{ + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + + if (mac->clr_aon_intr) + mac->clr_aon_intr(rtwdev); +} + int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); diff --git a/drivers/net/wireless/realtek/rtw89/mac_be.c b/drivers/net/wireless/realtek/rtw89/mac_be.c index 142e892f85c4..028fb63014eb 100644 --- a/drivers/net/wireless/realtek/rtw89/mac_be.c +++ b/drivers/net/wireless/realtek/rtw89/mac_be.c @@ -1990,6 +1990,15 @@ static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx, return 0; } +static void clr_aon_intr_be(struct rtw89_dev *rtwdev) +{ + if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE) + return; + + rtw89_write32_clr(rtwdev, R_BE_FWS0IMR, B_BE_FS_GPIOA_INT_EN); + rtw89_write32_set(rtwdev, R_BE_FWS0ISR, B_BE_FS_GPIOA_INT); +} + static int dbcc_bb_ctrl_be(struct rtw89_dev *rtwdev, bool bb1_en) { u32 set = B_BE_FEN_BB1PLAT_RSTB | B_BE_FEN_BB1_IP_RSTN; @@ -3179,6 +3188,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .sys_init = sys_init_be, .trx_init = trx_init_be, .preload_init = preload_init_be, + .clr_aon_intr = clr_aon_intr_be, .err_imr_ctrl = err_imr_ctrl_be, .mac_func_en = mac_func_en_be, .hci_func_en = rtw89_mac_hci_func_en_be, diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index efeb4507b1a9..df0866ba1d17 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -4315,6 +4315,72 @@ #define R_BE_SECURE_BOOT_MALLOC_INFO 0x0184 +#define R_BE_FWS0IMR 0x0190 +#define B_BE_FS_HALT_H2C_INT_EN BIT(31) +#define B_BE_FS_FSM_HIOE_TO_EVENT_INT_EN BIT(30) +#define B_BE_FS_HCI_SUS_INT_EN BIT(29) +#define B_BE_FS_HCI_RES_INT_EN BIT(28) +#define B_BE_FS_HCI_RESET_INT_EN BIT(27) +#define B_BE_FS_BT_SB1_INT_EN BIT(26) +#define B_BE_FS_ACT2RECOVERY_INT_EN BIT(25) +#define B_BE_FS_GEN1GEN2_SWITCH_INT_EN BIT(24) +#define B_BE_FS_USB_LPMRSM_INT_EN BIT(22) +#define B_BE_FS_USB_LPMINT_INT_EN BIT(21) +#define B_BE_FS_PWMERR_INT_EN BIT(20) +#define B_BE_FS_PDNINT_EN BIT(19) +#define B_BE_FS_SPSA_OCP_INT_EN BIT(18) +#define B_BE_FS_SPSD_OCP_INT_EN BIT(17) +#define B_BE_FS_BT_SB0_INT_EN BIT(16) +#define B_BE_FS_GPIOF_INT_EN BIT(15) +#define B_BE_FS_GPIOE_INT_EN BIT(14) +#define B_BE_FS_GPIOD_INT_EN BIT(13) +#define B_BE_FS_GPIOC_INT_EN BIT(12) +#define B_BE_FS_GPIOB_INT_EN BIT(11) +#define B_BE_FS_GPIOA_INT_EN BIT(10) +#define B_BE_FS_GPIO9_INT_EN BIT(9) +#define B_BE_FS_GPIO8_INT_EN BIT(8) +#define B_BE_FS_GPIO7_INT_EN BIT(7) +#define B_BE_FS_GPIO6_INT_EN BIT(6) +#define B_BE_FS_GPIO5_INT_EN BIT(5) +#define B_BE_FS_GPIO4_INT_EN BIT(4) +#define B_BE_FS_GPIO3_INT_EN BIT(3) +#define B_BE_FS_GPIO2_INT_EN BIT(2) +#define B_BE_FS_GPIO1_INT_EN BIT(1) +#define B_BE_FS_GPIO0_INT_EN BIT(0) + +#define R_BE_FWS0ISR 0x0194 +#define B_BE_FS_HALT_H2C_INT BIT(31) +#define B_BE_FS_FSM_HIOE_TO_EVENT_INT BIT(30) +#define B_BE_FS_HCI_SUS_INT BIT(29) +#define B_BE_FS_HCI_RES_INT BIT(28) +#define B_BE_FS_HCI_RESET_INT BIT(27) +#define B_BE_FS_BT_SB1_INT BIT(26) +#define B_BE_FS_ACT2RECOVERY_INT BIT(25) +#define B_BE_FS_GEN1GEN2_SWITCH_INT BIT(24) +#define B_BE_FS_USB_LPMRSM_INT BIT(22) +#define B_BE_FS_USB_LPMINT_INT BIT(21) +#define B_BE_FS_PWMERR_INT BIT(20) +#define B_BE_FS_PDNINT BIT(19) +#define B_BE_FS_SPSA_OCP_INT BIT(18) +#define B_BE_FS_SPSD_OCP_INT BIT(17) +#define B_BE_FS_BT_SB0_INT BIT(16) +#define B_BE_FS_GPIOF_INT BIT(15) +#define B_BE_FS_GPIOE_INT BIT(14) +#define B_BE_FS_GPIOD_INT BIT(13) +#define B_BE_FS_GPIOC_INT BIT(12) +#define B_BE_FS_GPIOB_INT BIT(11) +#define B_BE_FS_GPIOA_INT BIT(10) +#define B_BE_FS_GPIO9_INT BIT(9) +#define B_BE_FS_GPIO8_INT BIT(8) +#define B_BE_FS_GPIO7_INT BIT(7) +#define B_BE_FS_GPIO6_INT BIT(6) +#define B_BE_FS_GPIO5_INT BIT(5) +#define B_BE_FS_GPIO4_INT BIT(4) +#define B_BE_FS_GPIO3_INT BIT(3) +#define B_BE_FS_GPIO2_INT BIT(2) +#define B_BE_FS_GPIO1_INT BIT(1) +#define B_BE_FS_GPIO0_INT BIT(0) + #define R_BE_FWS1IMR 0x0198 #define B_BE_FS_RPWM_INT_EN_V1 BIT(24) #define B_BE_PCIE_HOTRST_EN BIT(22) -- cgit v1.2.3 From 1e3c50e0b491eaca8beb6b5ec9cb8261b4f1e38f Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Wed, 14 Jan 2026 09:39:40 +0800 Subject: wifi: rtw89: phy: add {read,write}_rf_v3 for RTL8922D Implement to access RF registers for RTL8922D. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-3-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy.c | 122 +++++++++++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/phy.h | 4 + drivers/net/wireless/realtek/rtw89/reg.h | 13 ++++ 3 files changed, 139 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 0b72d3dcf666..20d3f3a42b4b 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -1036,6 +1036,68 @@ u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, } EXPORT_SYMBOL(rtw89_phy_read_rf_v2); +static u32 rtw89_phy_read_full_rf_v3_a(struct rtw89_dev *rtwdev, + enum rtw89_rf_path rf_path, u32 addr) +{ + bool done; + u32 busy; + int ret; + u32 val; + + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, + 1, 30, false, + rtwdev, R_SW_SI_DATA_BE4, + B_SW_SI_W_BUSY_BE4 | B_SW_SI_R_BUSY_BE4); + if (ret) { + rtw89_warn(rtwdev, "poll HWSI is busy\n"); + return INV_RF_DATA; + } + + val = u32_encode_bits(rf_path, GENMASK(10, 8)) | + u32_encode_bits(addr, GENMASK(7, 0)); + + rtw89_phy_write32_mask(rtwdev, R_SW_SI_READ_ADDR_BE4, B_SW_SI_READ_ADDR_BE4, val); + + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, + 1, 30, false, + rtwdev, R_SW_SI_DATA_BE4, B_SW_SI_READ_DATA_DONE_BE4); + if (ret) { + rtw89_warn(rtwdev, "read HWSI is busy\n"); + return INV_RF_DATA; + } + + val = rtw89_phy_read32_mask(rtwdev, R_SW_SI_DATA_BE4, B_SW_SI_READ_DATA_BE4); + + return val; +} + +static u32 rtw89_phy_read_rf_v3_a(struct rtw89_dev *rtwdev, + enum rtw89_rf_path rf_path, u32 addr, u32 mask) +{ + u32 val; + + val = rtw89_phy_read_full_rf_v3_a(rtwdev, rf_path, addr); + + return (val & mask) >> __ffs(mask); +} + +u32 rtw89_phy_read_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, + u32 addr, u32 mask) +{ + bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); + + if (rf_path >= rtwdev->chip->rf_path_num) { + rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); + return INV_RF_DATA; + } + + if (ad_sel) + return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); + else + return rtw89_phy_read_rf_v3_a(rtwdev, rf_path, addr, mask); +} +EXPORT_SYMBOL(rtw89_phy_read_rf_v3); + bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask, u32 data) { @@ -1175,6 +1237,66 @@ bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, } EXPORT_SYMBOL(rtw89_phy_write_rf_v2); +static +bool rtw89_phy_write_full_rf_v3_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, + u32 addr, u32 data) +{ + u32 busy; + u32 val; + int ret; + + ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, + 1, 30, false, + rtwdev, R_SW_SI_DATA_BE4, + B_SW_SI_W_BUSY_BE4 | B_SW_SI_R_BUSY_BE4); + if (ret) { + rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__); + return false; + } + + val = u32_encode_bits(rf_path, B_SW_SI_DATA_PATH_BE4) | + u32_encode_bits(addr, B_SW_SI_DATA_ADR_BE4) | + u32_encode_bits(data, B_SW_SI_DATA_DAT_BE4); + + rtw89_phy_write32(rtwdev, R_SW_SI_WDATA_BE4, val); + + return true; +} + +static +bool rtw89_phy_write_rf_a_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, + u32 addr, u32 mask, u32 data) +{ + u32 val; + + if (mask == RFREG_MASK) { + val = data; + } else { + val = rtw89_phy_read_full_rf_v3_a(rtwdev, rf_path, addr); + val &= ~mask; + val |= (data << __ffs(mask)) & mask; + } + + return rtw89_phy_write_full_rf_v3_a(rtwdev, rf_path, addr, val); +} + +bool rtw89_phy_write_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, + u32 addr, u32 mask, u32 data) +{ + bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); + + if (rf_path >= rtwdev->chip->rf_path_num) { + rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); + return INV_RF_DATA; + } + + if (ad_sel) + return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); + else + return rtw89_phy_write_rf_a_v3(rtwdev, rf_path, addr, mask, data); +} +EXPORT_SYMBOL(rtw89_phy_write_rf_v3); + static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) { return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 9caacffd0af8..444b4ff86ebc 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -823,12 +823,16 @@ u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask); u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask); +u32 rtw89_phy_read_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, + u32 addr, u32 mask); bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask, u32 data); bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask, u32 data); bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask, u32 data); +bool rtw89_phy_write_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, + u32 addr, u32 mask, u32 data); void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev); void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index df0866ba1d17..bb991e7450bf 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -10124,6 +10124,19 @@ #define R_TSSI_K_P1 0xE7A0 #define B_TSSI_K_OFDM_P1 GENMASK(29, 20) +#define R_SW_SI_WDATA_BE4 0x20370 +#define B_SW_SI_DATA_PATH_BE4 GENMASK(31, 28) +#define B_SW_SI_DATA_ADR_BE4 GENMASK(27, 20) +#define B_SW_SI_DATA_DAT_BE4 GENMASK(19, 0) +#define R_SW_SI_READ_ADDR_BE4 0x20378 +#define B_SW_SI_READ_ADDR_BE4 GENMASK(10, 0) + +#define R_SW_SI_DATA_BE4 0x2CF4C +#define B_SW_SI_READ_DATA_BE4 GENMASK(19, 0) +#define B_SW_SI_W_BUSY_BE4 BIT(24) +#define B_SW_SI_R_BUSY_BE4 BIT(25) +#define B_SW_SI_READ_DATA_DONE_BE4 BIT(26) + /* WiFi CPU local domain */ #define R_AX_WDT_CTRL 0x0040 #define B_AX_WDT_EN BIT(31) -- cgit v1.2.3 From 3b99dac7bf917df0e298412430a9fb30eee6cc97 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Wed, 14 Jan 2026 09:39:41 +0800 Subject: wifi: rtw89: phy: add ops rtw89_phy_gen_be_v1 for RTL8922D Define RTL8922D specific registers, including PHY base control register, PHY status, CFO registers, and TX power registers. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-4-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy.h | 1 + drivers/net/wireless/realtek/rtw89/phy_be.c | 134 +++++++++++++++++++++++++++- drivers/net/wireless/realtek/rtw89/reg.h | 58 +++++++++++- 3 files changed, 185 insertions(+), 8 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 444b4ff86ebc..02bbb975ce65 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -559,6 +559,7 @@ struct rtw89_phy_gen_def { extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; +extern const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1; static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index bd17714f13d1..895615df5d7e 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -74,17 +74,88 @@ static const struct rtw89_ccx_regs rtw89_ccx_regs_be = { .nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK, }; +static const struct rtw89_ccx_regs rtw89_ccx_regs_be_v1 = { + .setting_addr = R_CCX_BE4, + .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1, + .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, + .trig_opt_mask = B_CCX_TRIG_OPT_MSK, + .en_mask = B_CCX_EN_MSK, + .ifs_cnt_addr = R_IFS_COUNTER_BE4, + .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, + .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, + .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, + .ifs_collect_en_mask = B_IFS_COLLECT_EN, + .ifs_t1_addr = R_IFS_T1_BE4, + .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, + .ifs_t1_en_mask = B_IFS_T1_EN_MSK, + .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, + .ifs_t2_addr = R_IFS_T2_BE4, + .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, + .ifs_t2_en_mask = B_IFS_T2_EN_MSK, + .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, + .ifs_t3_addr = R_IFS_T3_BE4, + .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, + .ifs_t3_en_mask = B_IFS_T3_EN_MSK, + .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, + .ifs_t4_addr = R_IFS_T4_BE4, + .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, + .ifs_t4_en_mask = B_IFS_T4_EN_MSK, + .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, + .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_BE4, + .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, + .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, + .ifs_clm_cca_addr = R_IFS_CLM_CCA_BE4, + .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, + .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, + .ifs_clm_fa_addr = R_IFS_CLM_FA_BE4, + .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, + .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, + .ifs_his_addr = R_IFS_T1_HIS_BE4, + .ifs_t4_his_mask = B_IFS_T4_HIS_BE4, + .ifs_t3_his_mask = B_IFS_T3_HIS_BE4, + .ifs_t2_his_mask = B_IFS_T2_HIS_BE4, + .ifs_t1_his_mask = B_IFS_T1_HIS_BE4, + .ifs_avg_l_addr = R_IFS_T1_AVG_BE4, + .ifs_t2_avg_mask = B_IFS_T2_AVG_BE4, + .ifs_t1_avg_mask = B_IFS_T1_AVG_BE4, + .ifs_avg_h_addr = R_IFS_T3_AVG_BE4, + .ifs_t4_avg_mask = B_IFS_T4_AVG_BE4, + .ifs_t3_avg_mask = B_IFS_T3_AVG_BE4, + .ifs_cca_l_addr = R_IFS_T1_CLM_BE4, + .ifs_t2_cca_mask = B_IFS_T2_CLM_BE4, + .ifs_t1_cca_mask = B_IFS_T1_CLM_BE4, + .ifs_cca_h_addr = R_IFS_T3_CLM_BE4, + .ifs_t4_cca_mask = B_IFS_T4_CLM_BE4, + .ifs_t3_cca_mask = B_IFS_T3_CLM_BE4, + .ifs_total_addr = R_IFS_TOTAL_BE4, + .ifs_cnt_done_mask = B_IFS_CNT_DONE_BE4, + .ifs_total_mask = B_IFS_TOTAL_BE4, +}; + static const struct rtw89_physts_regs rtw89_physts_regs_be = { .setting_addr = R_PLCP_HISTOGRAM, .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, }; +static const struct rtw89_physts_regs rtw89_physts_regs_be_v1 = { + .setting_addr = R_PLCP_HISTOGRAM_BE_V1, + .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, + .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, +}; + static const struct rtw89_cfo_regs rtw89_cfo_regs_be = { - .comp = R_DCFO_WEIGHT_V1, - .weighting_mask = B_DCFO_WEIGHT_MSK_V1, - .comp_seg0 = R_DCFO_OPT_V1, - .valid_0_mask = B_DCFO_OPT_EN_V1, + .comp = R_DCFO_WEIGHT_BE, + .weighting_mask = B_DCFO_WEIGHT_MSK_BE, + .comp_seg0 = R_DCFO_OPT_BE, + .valid_0_mask = B_DCFO_OPT_EN_BE, +}; + +static const struct rtw89_cfo_regs rtw89_cfo_regs_be_v1 = { + .comp = R_DCFO_WEIGHT_BE_V1, + .weighting_mask = B_DCFO_WEIGHT_MSK_BE, + .comp_seg0 = R_DCFO_OPT_BE_V1, + .valid_0_mask = B_DCFO_OPT_EN_BE, }; static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr) @@ -105,6 +176,25 @@ static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr) return ofst; } +static u32 rtw89_phy0_phy1_offset_be_v1(struct rtw89_dev *rtwdev, u32 addr) +{ + u32 phy_page = addr >> 8; + u32 ofst = 0; + + if ((phy_page >= 0x204 && phy_page <= 0x20F) || + (phy_page >= 0x220 && phy_page <= 0x22F) || + (phy_page >= 0x240 && phy_page <= 0x24f) || + (phy_page >= 0x260 && phy_page <= 0x26f) || + (phy_page >= 0x2C0 && phy_page <= 0x2C9) || + (phy_page >= 0x2E4 && phy_page <= 0x2E8) || + phy_page == 0x2EE) + ofst = 0x1000; + else + ofst = 0x0; + + return ofst; +} + union rtw89_phy_bb_gain_arg_be { u32 addr; struct { @@ -301,6 +391,16 @@ static void rtw89_phy_preinit_rf_nctl_be(struct rtw89_dev *rtwdev) } } +static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev) +{ + rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C0_BE4, B_GOTX_IQKDPK, 0x3); + rtw89_phy_write32_mask(rtwdev, R_GOTX_IQKDPK_C1_BE4, B_GOTX_IQKDPK, 0x3); + rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK_BE4, B_IOQ_IQK_DPK_RST, 0x1); + rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST_BE4, B_IQK_DPK_RST, 0x1); + rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_BE4, B_IQK_DPK_PRST, 0x1); + rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_C1_BE4, B_IQK_DPK_PRST, 0x1); +} + static void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) { @@ -441,6 +541,14 @@ static void rtw89_phy_ch_info_init_be(struct rtw89_dev *rtwdev) rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_TYPE_SCAL, B_CHINFO_SCAL, 0x0); } +static void rtw89_phy_ch_info_init_be_v1(struct rtw89_dev *rtwdev) +{ + rtw89_phy_write32_mask(rtwdev, R_CHINFO_SEG_BE4, B_CHINFO_SEG_LEN_BE4, 0); + rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_OPT_BE4, B_CHINFO_OPT_BE4, 0x3); + rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_NX_BE4, B_CHINFO_NX_BE4, 0x669); + rtw89_phy_set_phy_regs(rtwdev, R_CHINFO_ALG_BE4, B_CHINFO_ALG_BE4, 0); +} + struct rtw89_byr_spec_ent_be { struct rtw89_rate_desc init; u8 num_of_idx; @@ -1019,3 +1127,21 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be = { .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_be, }; EXPORT_SYMBOL(rtw89_phy_gen_be); + +const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = { + .cr_base = 0x0, + .ccx = &rtw89_ccx_regs_be_v1, + .physts = &rtw89_physts_regs_be_v1, + .cfo = &rtw89_cfo_regs_be_v1, + .phy0_phy1_offset = rtw89_phy0_phy1_offset_be_v1, + .config_bb_gain = rtw89_phy_config_bb_gain_be, + .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be_v1, + .bb_wrap_init = rtw89_phy_bb_wrap_init_be, + .ch_info_init = rtw89_phy_ch_info_init_be_v1, + + .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_be, + .set_txpwr_offset = rtw89_phy_set_txpwr_offset_be, + .set_txpwr_limit = rtw89_phy_set_txpwr_limit_be, + .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_be, +}; +EXPORT_SYMBOL(rtw89_phy_gen_be_v1); diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index bb991e7450bf..4d8329742f8c 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -8690,6 +8690,7 @@ #define R_MAC_PIN_SEL 0x0734 #define B_CH_IDX_SEG0 GENMASK(23, 16) #define R_PLCP_HISTOGRAM 0x0738 +#define R_PLCP_HISTOGRAM_BE_V1 0x20738 #define B_STS_PARSING_TIME GENMASK(19, 16) #define B_STS_DIS_TRIG_BY_FAIL BIT(3) #define B_STS_DIS_TRIG_BY_BRK BIT(2) @@ -8742,6 +8743,7 @@ #define R_DBCC_80P80_SEL_EVM_RPT 0x0A10 #define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0) #define R_CCX 0x0C00 +#define R_CCX_BE4 0x20C00 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4) #define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4) #define B_MEASUREMENT_TRIG_MSK BIT(2) @@ -8770,34 +8772,42 @@ #define R_FAHM 0x0C1C #define B_RXTD_CKEN BIT(2) #define R_IFS_COUNTER 0x0C28 +#define R_IFS_COUNTER_BE4 0x20C28 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16) #define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14) #define B_IFS_COUNTER_CLR_MSK BIT(13) #define B_IFS_COLLECT_EN BIT(12) #define R_IFS_T1 0x0C2C +#define R_IFS_T1_BE4 0x20C2C #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16) #define B_IFS_T1_EN_MSK BIT(15) #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0) #define R_IFS_T2 0x0C30 +#define R_IFS_T2_BE4 0x20C30 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16) #define B_IFS_T2_EN_MSK BIT(15) #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0) #define R_IFS_T3 0x0C34 +#define R_IFS_T3_BE4 0x20C34 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16) #define B_IFS_T3_EN_MSK BIT(15) #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0) #define R_IFS_T4 0x0C38 +#define R_IFS_T4_BE4 0x20C38 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16) #define B_IFS_T4_EN_MSK BIT(15) #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0) #define R_PD_CTRL 0x0C3C #define B_PD_HIT_DIS BIT(9) #define R_IOQ_IQK_DPK 0x0C60 +#define R_IOQ_IQK_DPK_BE4 0x20C60 #define B_IOQ_IQK_DPK_CLKEN GENMASK(1, 0) #define B_IOQ_IQK_DPK_EN BIT(1) +#define B_IOQ_IQK_DPK_RST BIT(0) #define R_GNT_BT_WGT_EN 0x0C6C #define B_GNT_BT_WGT_EN BIT(21) #define R_IQK_DPK_RST 0x0C6C +#define R_IQK_DPK_RST_BE4 0x20C6C #define R_IQK_DPK_RST_C1 0x1C6C #define B_IQK_DPK_RST BIT(0) #define R_TX_COLLISION_T2R_ST 0x0C70 @@ -8915,14 +8925,17 @@ #define B_NHM_READY_MSK BIT(16) #define R_IFS_CLM_TX_CNT 0x1ACC #define R_IFS_CLM_TX_CNT_V1 0x0ECC +#define R_IFS_CLM_TX_CNT_BE4 0x20ECC #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0) #define R_IFS_CLM_CCA 0x1AD0 #define R_IFS_CLM_CCA_V1 0x0ED0 +#define R_IFS_CLM_CCA_BE4 0x20ED0 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16) #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0) #define R_IFS_CLM_FA 0x1AD4 #define R_IFS_CLM_FA_V1 0x0ED4 +#define R_IFS_CLM_FA_BE4 0x20ED4 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16) #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0) #define R_IFS_HIS 0x1AD8 @@ -9579,12 +9592,14 @@ #define B_S0_DACKQ7_K GENMASK(15, 8) #define R_S0_DACKQ8 0x5E98 #define B_S0_DACKQ8_K GENMASK(15, 8) -#define R_DCFO_WEIGHT_V1 0x6244 -#define B_DCFO_WEIGHT_MSK_V1 GENMASK(31, 28) +#define R_DCFO_WEIGHT_BE 0x6244 +#define R_DCFO_WEIGHT_BE_V1 0x24808 +#define B_DCFO_WEIGHT_MSK_BE GENMASK(31, 28) #define R_DAC_CLK 0x625C #define B_DAC_CLK GENMASK(31, 30) -#define R_DCFO_OPT_V1 0x6260 -#define B_DCFO_OPT_EN_V1 BIT(17) +#define R_DCFO_OPT_BE 0x6260 +#define R_DCFO_OPT_BE_V1 0x24824 +#define B_DCFO_OPT_EN_BE BIT(17) #define R_TXFCTR 0x627C #define B_TXFCTR_THD GENMASK(19, 10) #define R_TXSCALE 0x6284 @@ -10094,10 +10109,14 @@ #define R_GAIN_MAP1 0xE54C #define B_GAIN_MAP1_EN BIT(0) #define R_GOTX_IQKDPK_C0 0xE464 +#define R_GOTX_IQKDPK_C0_BE4 0x2E464 #define R_GOTX_IQKDPK_C1 0xE564 +#define R_GOTX_IQKDPK_C1_BE4 0x2E564 #define B_GOTX_IQKDPK GENMASK(28, 27) #define R_IQK_DPK_PRST 0xE4AC +#define R_IQK_DPK_PRST_BE4 0x2E4AC #define R_IQK_DPK_PRST_C1 0xE5AC +#define R_IQK_DPK_PRST_C1_BE4 0x2E5AC #define B_IQK_DPK_PRST BIT(27) #define R_TXPWR_RSTA 0xE60C #define B_TXPWR_RSTA BIT(16) @@ -10124,12 +10143,43 @@ #define R_TSSI_K_P1 0xE7A0 #define B_TSSI_K_OFDM_P1 GENMASK(29, 20) +#define R_CHINFO_SEG_BE4 0x200B4 +#define B_CHINFO_SEG_LEN_BE4 GENMASK(12, 10) + #define R_SW_SI_WDATA_BE4 0x20370 #define B_SW_SI_DATA_PATH_BE4 GENMASK(31, 28) #define B_SW_SI_DATA_ADR_BE4 GENMASK(27, 20) #define B_SW_SI_DATA_DAT_BE4 GENMASK(19, 0) #define R_SW_SI_READ_ADDR_BE4 0x20378 #define B_SW_SI_READ_ADDR_BE4 GENMASK(10, 0) +#define R_IFS_T1_AVG_BE4 0x20EDC +#define B_IFS_T1_AVG_BE4 GENMASK(15, 0) +#define B_IFS_T2_AVG_BE4 GENMASK(31, 16) +#define R_IFS_T3_AVG_BE4 0x20EE0 +#define B_IFS_T3_AVG_BE4 GENMASK(15, 0) +#define B_IFS_T4_AVG_BE4 GENMASK(31, 16) +#define R_IFS_T1_CLM_BE4 0x20EE4 +#define B_IFS_T1_CLM_BE4 GENMASK(15, 0) +#define B_IFS_T2_CLM_BE4 GENMASK(31, 16) +#define R_IFS_T3_CLM_BE4 0x20EE8 +#define B_IFS_T3_CLM_BE4 GENMASK(15, 0) +#define B_IFS_T4_CLM_BE4 GENMASK(31, 16) +#define R_IFS_TOTAL_BE4 0x20EEC +#define B_IFS_TOTAL_BE4 GENMASK(15, 0) +#define B_IFS_CNT_DONE_BE4 BIT(16) +#define R_IFS_T1_HIS_BE4 0x20F50 +#define B_IFS_T1_HIS_BE4 GENMASK(15, 0) +#define B_IFS_T2_HIS_BE4 GENMASK(31, 16) +#define R_IFS_T3_HIS_BE4 0x20F54 +#define B_IFS_T3_HIS_BE4 GENMASK(15, 0) +#define B_IFS_T4_HIS_BE4 GENMASK(31, 16) + +#define R_CHINFO_OPT_BE4 0x267C8 +#define B_CHINFO_OPT_BE4 GENMASK(14, 13) +#define R_CHINFO_NX_BE4 0x267D0 +#define B_CHINFO_NX_BE4 GENMASK(16, 6) +#define R_CHINFO_ALG_BE4 0x267C8 +#define B_CHINFO_ALG_BE4 GENMASK(31, 30) #define R_SW_SI_DATA_BE4 0x2CF4C #define B_SW_SI_READ_DATA_BE4 GENMASK(19, 0) -- cgit v1.2.3 From fc31826cbc24115091a4a68a95fa2697cf725416 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Wed, 14 Jan 2026 09:39:42 +0800 Subject: wifi: rtw89: phy: abstract start address and EHT of PHY status bitmap Select PHY status being reported by a set of addresses. Abstract the address and EHT bitmap to share common flow. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-5-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy.c | 31 ++++++++++++++++++++++++----- drivers/net/wireless/realtek/rtw89/phy.h | 2 ++ drivers/net/wireless/realtek/rtw89/phy_be.c | 4 ++++ drivers/net/wireless/realtek/rtw89/reg.h | 5 ++++- 4 files changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 20d3f3a42b4b..3ae540a6fa4f 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -6407,14 +6407,16 @@ static bool rtw89_physts_ie_page_valid(struct rtw89_dev *rtwdev, return true; } -static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) +static u32 rtw89_phy_get_ie_bitmap_addr(struct rtw89_dev *rtwdev, + enum rtw89_phy_status_bitmap ie_page) { + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; static const u8 ie_page_shift = 2; if (ie_page == RTW89_EHT_PKT) - return R_PHY_STS_BITMAP_EHT; + return phy->physt_bmp_eht; - return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); + return phy->physt_bmp_start + (ie_page << ie_page_shift); } static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, @@ -6426,7 +6428,7 @@ static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, if (!rtw89_physts_ie_page_valid(rtwdev, &ie_page)) return 0; - addr = rtw89_phy_get_ie_bitmap_addr(ie_page); + addr = rtw89_phy_get_ie_bitmap_addr(rtwdev, ie_page); return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx); } @@ -6444,7 +6446,7 @@ static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, if (chip->chip_id == RTL8852A) val &= B_PHY_STS_BITMAP_MSK_52A; - addr = rtw89_phy_get_ie_bitmap_addr(ie_page); + addr = rtw89_phy_get_ie_bitmap_addr(rtwdev, ie_page); rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx); } @@ -6468,6 +6470,17 @@ static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, } } +static void rtw89_physts_enable_hdr_2(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) +{ + const struct rtw89_chip_info *chip = rtwdev->chip; + + if (chip->chip_gen == RTW89_CHIP_AX || chip->chip_id == RTL8922A) + return; + + rtw89_phy_write32_idx_set(rtwdev, R_STS_HDR2_PARSING_BE4, + B_STS_HDR2_PARSING_BE4, phy_idx); +} + static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) { @@ -6477,6 +6490,9 @@ static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev, rtw89_physts_enable_fail_report(rtwdev, false, phy_idx); + /* enable hdr_2 for 8922D (PHYSTS_BE_GEN2 above) */ + rtw89_physts_enable_hdr_2(rtwdev, phy_idx); + for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { if (i == RTW89_RSVD_9 || (i == RTW89_EHT_PKT && chip->chip_gen == RTW89_CHIP_AX)) @@ -6842,6 +6858,9 @@ static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, { const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; + if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) + return; + rtw89_phy_write32_idx(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, dig_regs->p0_p20_pagcugc_en.mask, enable, bb->phy_idx); rtw89_phy_write32_idx(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, @@ -8211,6 +8230,8 @@ static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = { const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { .cr_base = 0x10000, + .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START, + .physt_bmp_eht = 0xfc, .ccx = &rtw89_ccx_regs_ax, .physts = &rtw89_physts_regs_ax, .cfo = &rtw89_cfo_regs_ax, diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 02bbb975ce65..8506c607de4d 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -531,6 +531,8 @@ struct rtw89_phy_rfk_log_fmt { struct rtw89_phy_gen_def { u32 cr_base; + u32 physt_bmp_start; + u32 physt_bmp_eht; const struct rtw89_ccx_regs *ccx; const struct rtw89_physts_regs *physts; const struct rtw89_cfo_regs *cfo; diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index 895615df5d7e..a609cd0c5268 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -1112,6 +1112,8 @@ static void rtw89_phy_set_txpwr_limit_ru_be(struct rtw89_dev *rtwdev, const struct rtw89_phy_gen_def rtw89_phy_gen_be = { .cr_base = 0x20000, + .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START, + .physt_bmp_eht = R_PHY_STS_BITMAP_EHT, .ccx = &rtw89_ccx_regs_be, .physts = &rtw89_physts_regs_be, .cfo = &rtw89_cfo_regs_be, @@ -1130,6 +1132,8 @@ EXPORT_SYMBOL(rtw89_phy_gen_be); const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = { .cr_base = 0x0, + .physt_bmp_start = R_PHY_STS_BITMAP_ADDR_START_BE4, + .physt_bmp_eht = R_PHY_STS_BITMAP_EHT_BE4, .ccx = &rtw89_ccx_regs_be_v1, .physts = &rtw89_physts_regs_be_v1, .cfo = &rtw89_cfo_regs_be_v1, diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 4d8329742f8c..115d3b008452 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -8695,6 +8695,7 @@ #define B_STS_DIS_TRIG_BY_FAIL BIT(3) #define B_STS_DIS_TRIG_BY_BRK BIT(2) #define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL +#define R_PHY_STS_BITMAP_ADDR_START_BE4 0x2073C #define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2) #define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C #define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f @@ -8713,6 +8714,7 @@ #define R_PHY_STS_BITMAP_VHT 0x0770 #define R_PHY_STS_BITMAP_HE 0x0774 #define R_PHY_STS_BITMAP_EHT 0x0788 +#define R_PHY_STS_BITMAP_EHT_BE4 0x20788 #define R_EDCCA_RPTREG_SEL_BE 0x078C #define B_EDCCA_RPTREG_SEL_BE_MSK GENMASK(22, 20) #define R_PMAC_GNT 0x0980 @@ -10145,7 +10147,8 @@ #define R_CHINFO_SEG_BE4 0x200B4 #define B_CHINFO_SEG_LEN_BE4 GENMASK(12, 10) - +#define R_STS_HDR2_PARSING_BE4 0x2070C +#define B_STS_HDR2_PARSING_BE4 BIT(10) #define R_SW_SI_WDATA_BE4 0x20370 #define B_SW_SI_DATA_PATH_BE4 GENMASK(31, 28) #define B_SW_SI_DATA_ADR_BE4 GENMASK(27, 20) -- cgit v1.2.3 From 0e8818a309f70b095d9b7753beca92da285a1c36 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Wed, 14 Jan 2026 09:39:43 +0800 Subject: wifi: rtw89: phy: extend register to read history 2 of PHY env_monitor For old chips, history is 8 bits storing in single one register, and RTL8922D's one is 16 bits and two registers. Extend to common flow accordingly. Signed-off-by: Eric Huang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-6-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/core.h | 2 +- drivers/net/wireless/realtek/rtw89/phy.c | 6 ++++-- drivers/net/wireless/realtek/rtw89/phy.h | 1 + drivers/net/wireless/realtek/rtw89/phy_be.c | 2 ++ 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h index 1abd09d9d29c..d2eb7c66f041 100644 --- a/drivers/net/wireless/realtek/rtw89/core.h +++ b/drivers/net/wireless/realtek/rtw89/core.h @@ -5686,7 +5686,7 @@ struct rtw89_env_monitor_info { u16 ifs_clm_cckfa; u16 ifs_clm_cckcca_excl_fa; u16 ifs_clm_total_ifs; - u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; + u16 ifs_clm_his[RTW89_IFS_CLM_NUM]; u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; u8 ifs_clm_tx_ratio; diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 3ae540a6fa4f..77481695cd2e 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -6140,11 +6140,12 @@ static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev, env->ifs_clm_his[1] = rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, ccx->ifs_t2_his_mask, bb->phy_idx); + env->ifs_clm_his[2] = - rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, + rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr2, ccx->ifs_t3_his_mask, bb->phy_idx); env->ifs_clm_his[3] = - rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, + rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr2, ccx->ifs_t4_his_mask, bb->phy_idx); env->ifs_clm_avg[0] = @@ -8185,6 +8186,7 @@ static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, .ifs_his_addr = R_IFS_HIS, + .ifs_his_addr2 = R_IFS_HIS, .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 8506c607de4d..f28580689626 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -416,6 +416,7 @@ struct rtw89_ccx_regs { u32 ifs_clm_ofdm_fa_mask; u32 ifs_clm_cck_fa_mask; u32 ifs_his_addr; + u32 ifs_his_addr2; u32 ifs_t4_his_mask; u32 ifs_t3_his_mask; u32 ifs_t2_his_mask; diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index a609cd0c5268..33c28a1666d4 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -44,6 +44,7 @@ static const struct rtw89_ccx_regs rtw89_ccx_regs_be = { .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, .ifs_his_addr = R_IFS_HIS_V1, + .ifs_his_addr2 = R_IFS_HIS_V1, .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, @@ -111,6 +112,7 @@ static const struct rtw89_ccx_regs rtw89_ccx_regs_be_v1 = { .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, .ifs_his_addr = R_IFS_T1_HIS_BE4, + .ifs_his_addr2 = R_IFS_T3_HIS_BE4, /* for 3/4 */ .ifs_t4_his_mask = B_IFS_T4_HIS_BE4, .ifs_t3_his_mask = B_IFS_T3_HIS_BE4, .ifs_t2_his_mask = B_IFS_T2_HIS_BE4, -- cgit v1.2.3 From ace51dc80334f1a9b479fb039e31a0c7d581e9cf Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Wed, 14 Jan 2026 09:39:44 +0800 Subject: wifi: rtw89: phy: abstract BB wrap registers to share initial flow BB wrap registers are to configure TX power in MAC register domain, but they are controlled and designed by BB layer. Since coming chips use different register address, add a struct to define them. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-7-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy.c | 1 + drivers/net/wireless/realtek/rtw89/phy.h | 6 ++++++ drivers/net/wireless/realtek/rtw89/phy_be.c | 20 ++++++++++++++++++-- drivers/net/wireless/realtek/rtw89/reg.h | 2 ++ 4 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 77481695cd2e..d311de093425 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -8237,6 +8237,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { .ccx = &rtw89_ccx_regs_ax, .physts = &rtw89_physts_regs_ax, .cfo = &rtw89_cfo_regs_ax, + .bb_wrap = NULL, .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax, .config_bb_gain = rtw89_phy_config_bb_gain_ax, .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax, diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index f28580689626..0834569278cd 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -460,6 +460,11 @@ struct rtw89_cfo_regs { u32 valid_0_mask; }; +struct rtw89_bb_wrap_regs { + u32 pwr_macid_lmt; + u32 pwr_macid_path; +}; + enum rtw89_bandwidth_section_num_ax { RTW89_BW20_SEC_NUM_AX = 8, RTW89_BW40_SEC_NUM_AX = 4, @@ -537,6 +542,7 @@ struct rtw89_phy_gen_def { const struct rtw89_ccx_regs *ccx; const struct rtw89_physts_regs *physts; const struct rtw89_cfo_regs *cfo; + const struct rtw89_bb_wrap_regs *bb_wrap; u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr); void (*config_bb_gain)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index 33c28a1666d4..e333c3eb1e9b 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -160,6 +160,16 @@ static const struct rtw89_cfo_regs rtw89_cfo_regs_be_v1 = { .valid_0_mask = B_DCFO_OPT_EN_BE, }; +static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be = { + .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE, + .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE, +}; + +static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be_v1 = { + .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE_V1, + .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE_V1, +}; + static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr) { u32 phy_page = addr >> 8; @@ -406,9 +416,11 @@ static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev) static void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) { + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; + const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap; u32 macid_idx, cr, base_macid_lmt, max_macid = 32; - base_macid_lmt = R_BE_PWR_MACID_LMT_BASE; + base_macid_lmt = bb_wrap->pwr_macid_lmt; for (macid_idx = 0; macid_idx < 4 * max_macid; macid_idx += 4) { cr = base_macid_lmt + macid_idx; @@ -419,8 +431,10 @@ void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) static void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev) { + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; + const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap; + u32 cr = bb_wrap->pwr_macid_path; int i, max_macid = 32; - u32 cr = R_BE_PWR_MACID_PATH_BASE; for (i = 0; i < max_macid; i++, cr += 4) rtw89_write32(rtwdev, cr, 0x03C86000); @@ -1119,6 +1133,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be = { .ccx = &rtw89_ccx_regs_be, .physts = &rtw89_physts_regs_be, .cfo = &rtw89_cfo_regs_be, + .bb_wrap = &rtw89_bb_wrap_regs_be, .phy0_phy1_offset = rtw89_phy0_phy1_offset_be, .config_bb_gain = rtw89_phy_config_bb_gain_be, .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be, @@ -1139,6 +1154,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = { .ccx = &rtw89_ccx_regs_be_v1, .physts = &rtw89_physts_regs_be_v1, .cfo = &rtw89_cfo_regs_be_v1, + .bb_wrap = &rtw89_bb_wrap_regs_be_v1, .phy0_phy1_offset = rtw89_phy0_phy1_offset_be_v1, .config_bb_gain = rtw89_phy_config_bb_gain_be, .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be_v1, diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 115d3b008452..ab344d0269f7 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -6432,7 +6432,9 @@ #define B_BE_PTA_GNT_BT1_BB_SWCTRL BIT(0) #define R_BE_PWR_MACID_PATH_BASE 0x0E500 +#define R_BE_PWR_MACID_PATH_BASE_V1 0x1C000 #define R_BE_PWR_MACID_LMT_BASE 0x0ED00 +#define R_BE_PWR_MACID_LMT_BASE_V1 0x1C800 #define R_BE_CMAC_FUNC_EN 0x10000 #define R_BE_CMAC_FUNC_EN_C1 0x14000 -- cgit v1.2.3 From d6cc6e12c15b92ecca4f3839baabed94533fc09e Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Wed, 14 Jan 2026 09:39:45 +0800 Subject: wifi: rtw89: phy: update bb wrapper TPU init Set DBW by rate to on in TPU (TX Power Unit) init, and extend to initialize two hardware bands. Signed-off-by: Eric Huang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-8-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy_be.c | 23 ++++++++++++++++------- drivers/net/wireless/realtek/rtw89/reg.h | 1 + 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index e333c3eb1e9b..766ea4404ffc 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -443,14 +443,23 @@ void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev) static void rtw89_phy_bb_wrap_tpu_set_all(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx) { - u32 addr; + u32 addr, t; + + addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_FTM_SS, mac_idx); + rtw89_write32_mask(rtwdev, addr, B_BE_PWR_BY_RATE_DBW_ON, 0x3); - for (addr = R_BE_PWR_BY_RATE; addr <= R_BE_PWR_BY_RATE_END; addr += 4) - rtw89_write32(rtwdev, addr, 0); - for (addr = R_BE_PWR_RULMT_START; addr <= R_BE_PWR_RULMT_END; addr += 4) - rtw89_write32(rtwdev, addr, 0); - for (addr = R_BE_PWR_RATE_OFST_CTRL; addr <= R_BE_PWR_RATE_OFST_END; addr += 4) - rtw89_write32(rtwdev, addr, 0); + for (addr = R_BE_PWR_BY_RATE; addr <= R_BE_PWR_BY_RATE_END; addr += 4) { + t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); + rtw89_write32(rtwdev, t, 0); + } + for (addr = R_BE_PWR_RULMT_START; addr <= R_BE_PWR_RULMT_END; addr += 4) { + t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); + rtw89_write32(rtwdev, t, 0); + } + for (addr = R_BE_PWR_RATE_OFST_CTRL; addr <= R_BE_PWR_RATE_OFST_END; addr += 4) { + t = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); + rtw89_write32(rtwdev, t, 0); + } addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_REF_CTRL, mac_idx); rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMT_DB, 0); diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index ab344d0269f7..275b3b2fd9e8 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -8311,6 +8311,7 @@ #define R_BE_PWR_FTM 0x11B00 #define R_BE_PWR_FTM_SS 0x11B04 +#define B_BE_PWR_BY_RATE_DBW_ON GENMASK(27, 26) #define R_BE_PWR_BY_RATE 0x11E00 #define R_BE_PWR_BY_RATE_MAX 0x11FA8 -- cgit v1.2.3 From 51cc8220f8ce556d86f225e4c0732315acf029ff Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Wed, 14 Jan 2026 09:39:46 +0800 Subject: wifi: rtw89: phy: update BB wrapper RFSI RTL8922D adds newly BB wrapper RFSI, including compensation values and threshold, bandedge settings, and CIM3K coefficient. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-9-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/mac.h | 8 + drivers/net/wireless/realtek/rtw89/phy.h | 6 + drivers/net/wireless/realtek/rtw89/phy_be.c | 328 ++++++++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/reg.h | 207 ++++++++++++++++++ 4 files changed, 549 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h index 784a1cf4c6f4..0c8614fc3000 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.h +++ b/drivers/net/wireless/realtek/rtw89/mac.h @@ -1139,6 +1139,14 @@ rtw89_write16_idx(struct rtw89_dev *rtwdev, u32 addr, u16 data, u8 band) rtw89_write16(rtwdev, addr, data); } +static inline void +rtw89_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data, u8 band) +{ + addr = rtw89_mac_reg_by_idx(rtwdev, addr, band); + + rtw89_write32_mask(rtwdev, addr, mask, data); +} + static inline u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) { diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 0834569278cd..4e985a604338 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -893,6 +893,12 @@ static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev) phy->bb_wrap_init(rtwdev); } +void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev, + enum rtw89_phy_idx phy_idx); +void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev, + const struct rtw89_chan *chan, + enum rtw89_phy_idx phy_idx); + static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev) { const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index 766ea4404ffc..f64dc47a5850 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -2,6 +2,7 @@ /* Copyright(c) 2023 Realtek Corporation */ +#include "chan.h" #include "debug.h" #include "mac.h" #include "phy.h" @@ -519,6 +520,332 @@ static void rtw89_phy_bb_wrap_ftm_init(struct rtw89_dev *rtwdev, rtw89_write32_mask(rtwdev, addr, 0x7, 0); } +static u32 rtw89_phy_bb_wrap_be_bandedge_decision(struct rtw89_dev *rtwdev, + const struct rtw89_chan *chan) +{ + u8 pri_ch = chan->primary_channel; + u32 val = 0; + + switch (chan->band_type) { + default: + case RTW89_BAND_2G: + if (pri_ch == 1 || pri_ch == 13) + val = BIT(1) | BIT(0); + else if (pri_ch == 3 || pri_ch == 11) + val = BIT(1); + break; + case RTW89_BAND_5G: + if (pri_ch == 36 || pri_ch == 64 || pri_ch == 100) + val = BIT(3) | BIT(2) | BIT(1) | BIT(0); + else if (pri_ch == 40 || pri_ch == 60 || pri_ch == 104) + val = BIT(3) | BIT(2) | BIT(1); + else if ((pri_ch > 40 && pri_ch < 60) || pri_ch == 108 || pri_ch == 112) + val = BIT(3) | BIT(2); + else if (pri_ch > 112 && pri_ch < 132) + val = BIT(3); + break; + case RTW89_BAND_6G: + if (pri_ch == 233) + val = BIT(0); + break; + } + + return val; +} + +void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev, + enum rtw89_phy_idx phy_idx) +{ + u32 reg; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_0_BE4, phy_idx); + rtw89_write32(rtwdev, reg, 0x00010001); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_RFSI_CT_OPT_8_BE4, phy_idx); + rtw89_write32(rtwdev, reg, 0x00010001); +} +EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_ct_opt); + +void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev, + const struct rtw89_chan *chan, + enum rtw89_phy_idx phy_idx) +{ + u32 reg; + u32 val; + + val = rtw89_phy_bb_wrap_be_bandedge_decision(rtwdev, chan); + + rtw89_phy_write32_idx(rtwdev, R_TX_CFR_MANUAL_EN_BE4, B_TX_CFR_MANUAL_EN_BE4_M, + chan->primary_channel == 13, phy_idx); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); + rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW20_BE4, val & BIT(0)); + reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); + rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW40_BE4, (val & BIT(1)) >> 1); + reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWX_BE4, phy_idx); + rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW80_BE4, (val & BIT(2)) >> 2); + reg = rtw89_mac_reg_by_idx(rtwdev, R_BANDEDGE_DBWY_BE4, phy_idx); + rtw89_write32_mask(rtwdev, reg, B_BANDEDGE_DBW160_BE4, (val & BIT(3)) >> 3); +} +EXPORT_SYMBOL(rtw89_phy_bb_wrap_set_rfsi_bandedge_ch); + +static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(struct rtw89_dev *rtwdev, + enum rtw89_mac_idx mac_idx) +{ + /* TH0 */ + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_0_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_3_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_1_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_4_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_7_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_0_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_3_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_6_BE4, 0x1, mac_idx); + /* TH1 */ + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_1_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_4_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_2_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_5_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_8_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_1_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_4_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_7_BE4, 0x2, mac_idx); + /* TH2 */ + rtw89_write32_idx(rtwdev, R_QAM_TH0_BE4, B_QAM_TH0_2_BE4, 0x4, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_0_BE4, 0x4, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_3_BE4, 0x4, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_6_BE4, 0x4, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH1_BE4, B_QAM_TH1_9_BE4, 0x4, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_2_BE4, 0x4, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_5_BE4, 0x4, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_TH2_BE4, B_QAM_TH2_8_BE4, 0x4, mac_idx); + /* DPD 160M */ + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_0_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_1_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_2_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_3_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH0_BE4, B_DPD_DBW160_TH0_4_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_5_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_6_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_DBW160_TH1_BE4, B_DPD_DBW160_TH1_7_BE4, 0x1, mac_idx); + /* DPD 20M */ + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_0_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_1_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_2_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_3_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_4_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_5_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH0_BE4, B_DPD_CBW20_TH0_6_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH1_7_BE4, 0x2, mac_idx); + /* DPD 40M */ + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_0_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_1_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_2_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_3_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW40_TH1_4_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_3_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_4_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW20_TH0_5_BE4, 0x2, mac_idx); + /* DPD 80M */ + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH1_BE4, B_DPD_CBW80_TH1_0_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_1_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_2_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_3_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_4_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_5_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_6_BE4, 0x2, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW_TH2_BE4, B_DPD_CBW80_TH2_7_BE4, 0x2, mac_idx); + /* CIM3K */ + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH2_BE4, 0x2, mac_idx); +} + +static void rtw89_phy_bb_wrap_tx_rfsi_scenario_def(struct rtw89_dev *rtwdev, + enum rtw89_mac_idx mac_idx) +{ + rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_ER_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SUBF_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_FTM_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_RFSI_CT_DEF_BE4, B_RFSI_CT_SENS_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DEF_BE, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_PB_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_WO_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_DL_BF_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_MUMIMO_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_FTM_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_FBTB_CT_DEF_BE4, B_FBTB_CT_SENS_BE4, 0x0, mac_idx); +} + +static void rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(struct rtw89_dev *rtwdev, + enum rtw89_mac_idx mac_idx) +{ + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKLWORD, 0x4010, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH0_BE4, MASKHWORD, 0x4410, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKLWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH1_BE4, MASKHWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKLWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH2_BE4, MASKHWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKLWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH3_BE4, MASKHWORD, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_L, 0x8, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_M, 0x8, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_H, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_L, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_M, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_H, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_L, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_M, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2L, 0x8, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2M, 0x8, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH4_BE4, B_QAM_COMP_TH4_2H, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2L, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2M, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH5_BE4, B_QAM_COMP_TH5_2H, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2L, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_QAM_COMP_TH6_BE4, B_QAM_COMP_TH6_2M, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKLWORD, 0x4010, mac_idx); + rtw89_write32_idx(rtwdev, R_OW_VAL_0_BE4, MASKHWORD, 0x4010, mac_idx); + rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKLWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OW_VAL_1_BE4, MASKHWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKLWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OW_VAL_2_BE4, MASKHWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKLWORD, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OW_VAL_3_BE4, MASKHWORD, 0x0, mac_idx); +} + +static void rtw89_phy_bb_set_oob_dpd_qam_comp_val(struct rtw89_dev *rtwdev, + enum rtw89_mac_idx mac_idx) +{ + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_CCK7_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_CCK7_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW20_BE4, B_OOB_CBW20_TH7_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_TH7_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_TH7_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW20_OW7_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW40_BE4, B_OOB_CBW40_OW7_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_OOB_CBW80_BE4, B_OOB_CBW80_OW7_BE4, 0x0, mac_idx); +} + +static void rtw89_phy_bb_set_mdpd_qam_comp_val(struct rtw89_dev *rtwdev, + enum rtw89_mac_idx mac_idx) +{ + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_TH7_BE4, 0x0, mac_idx); + + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW0_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW1_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW2_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW3_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW4_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW5_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW6_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_DPD_CBW160_BE4, B_DPD_CBW160_OW7_BE4, 0x0, mac_idx); +} + +static void rtw89_phy_bb_set_cim3k_val(struct rtw89_dev *rtwdev, + enum rtw89_mac_idx mac_idx) +{ + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_OW_BE4, 0x0, mac_idx); + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_NONBE_BE4, 0x1, mac_idx); + rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_BANDEDGE_BE4, 0x1, mac_idx); +} + +static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev, + enum rtw89_mac_idx mac_idx) +{ + enum rtw89_phy_idx phy_idx = mac_idx != RTW89_MAC_0 ? RTW89_PHY_1 : RTW89_PHY_0; + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; + const struct rtw89_chan *chan; + + if (chip_id != RTL8922D) + return; + + rtw89_phy_bb_wrap_tx_rfsi_qam_comp_th_init(rtwdev, mac_idx); + rtw89_phy_bb_wrap_tx_rfsi_scenario_def(rtwdev, mac_idx); + rtw89_phy_bb_wrap_tx_rfsi_qam_comp_val(rtwdev, mac_idx); + rtw89_phy_bb_set_oob_dpd_qam_comp_val(rtwdev, mac_idx); + rtw89_phy_bb_set_mdpd_qam_comp_val(rtwdev, mac_idx); + rtw89_phy_bb_set_cim3k_val(rtwdev, mac_idx); + + rtw89_phy_bb_wrap_set_rfsi_ct_opt(rtwdev, phy_idx); + + chan = rtw89_mgnt_chan_get(rtwdev, phy_idx); + if (chan) + rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(rtwdev, chan, phy_idx); +} + static void rtw89_phy_bb_wrap_ul_pwr(struct rtw89_dev *rtwdev) { enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; @@ -545,6 +872,7 @@ static void __rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev, rtw89_phy_bb_wrap_force_cr_init(rtwdev, mac_idx); rtw89_phy_bb_wrap_ftm_init(rtwdev, mac_idx); rtw89_phy_bb_wrap_tpu_set_all(rtwdev, mac_idx); + rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(rtwdev, mac_idx); rtw89_phy_bb_wrap_ul_pwr(rtwdev); } diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 275b3b2fd9e8..895795228268 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -10148,6 +10148,210 @@ #define R_TSSI_K_P1 0xE7A0 #define B_TSSI_K_OFDM_P1 GENMASK(29, 20) +#define R_COMP_CIM3K_BE4 0x11998 +#define B_COMP_CIM3K_OW_BE4 BIT(1) +#define B_COMP_CIM3K_TH_BE4 BIT(2) +#define B_COMP_CIM3K_TH2_BE4 GENMASK(5, 3) +#define B_COMP_CIM3K_TXPWR_EN_BE4 BIT(6) +#define B_COMP_CIM3K_NONBE_BE4 BIT(7) +#define B_COMP_CIM3K_BANDEDGE_BE4 BIT(8) +#define R_DPD_CBW160_BE4 0x119B4 +#define B_DPD_CBW160_TH0_BE4 BIT(0) +#define B_DPD_CBW160_TH1_BE4 BIT(1) +#define B_DPD_CBW160_TH2_BE4 BIT(2) +#define B_DPD_CBW160_TH3_BE4 BIT(3) +#define B_DPD_CBW160_TH4_BE4 BIT(4) +#define B_DPD_CBW160_TH5_BE4 BIT(5) +#define B_DPD_CBW160_TH6_BE4 BIT(6) +#define B_DPD_CBW160_TH7_BE4 BIT(7) +#define B_DPD_CBW160_OW0_BE4 BIT(8) +#define B_DPD_CBW160_OW1_BE4 BIT(9) +#define B_DPD_CBW160_OW2_BE4 BIT(10) +#define B_DPD_CBW160_OW3_BE4 BIT(11) +#define B_DPD_CBW160_OW4_BE4 BIT(12) +#define B_DPD_CBW160_OW5_BE4 BIT(13) +#define B_DPD_CBW160_OW6_BE4 BIT(14) +#define B_DPD_CBW160_OW7_BE4 BIT(15) +#define R_OOB_CBW20_BE4 0x119B4 +#define B_OOB_CBW20_CCK0_BE4 BIT(16) +#define B_OOB_CBW20_CCK1_BE4 BIT(17) +#define B_OOB_CBW20_CCK2_BE4 BIT(18) +#define B_OOB_CBW20_CCK3_BE4 BIT(19) +#define B_OOB_CBW20_CCK4_BE4 BIT(20) +#define B_OOB_CBW20_CCK5_BE4 BIT(21) +#define B_OOB_CBW20_CCK6_BE4 BIT(22) +#define B_OOB_CBW20_CCK7_BE4 BIT(23) +#define B_OOB_CBW20_TH0_BE4 BIT(24) +#define B_OOB_CBW20_TH1_BE4 BIT(25) +#define B_OOB_CBW20_TH2_BE4 BIT(26) +#define B_OOB_CBW20_TH3_BE4 BIT(27) +#define B_OOB_CBW20_TH4_BE4 BIT(28) +#define B_OOB_CBW20_TH5_BE4 BIT(29) +#define B_OOB_CBW20_TH6_BE4 BIT(30) +#define B_OOB_CBW20_TH7_BE4 BIT(31) +#define R_OOB_CBW40_BE4 0x119B8 +#define B_OOB_CBW20_OW0_BE4 BIT(0) +#define B_OOB_CBW20_OW1_BE4 BIT(1) +#define B_OOB_CBW20_OW2_BE4 BIT(2) +#define B_OOB_CBW20_OW3_BE4 BIT(3) +#define B_OOB_CBW20_OW4_BE4 BIT(4) +#define B_OOB_CBW20_OW5_BE4 BIT(5) +#define B_OOB_CBW20_OW6_BE4 BIT(6) +#define B_OOB_CBW20_OW7_BE4 BIT(7) +#define B_OOB_CBW40_CCK0_BE4 BIT(8) +#define B_OOB_CBW40_CCK1_BE4 BIT(9) +#define B_OOB_CBW40_CCK2_BE4 BIT(10) +#define B_OOB_CBW40_CCK3_BE4 BIT(11) +#define B_OOB_CBW40_CCK4_BE4 BIT(12) +#define B_OOB_CBW40_CCK5_BE4 BIT(13) +#define B_OOB_CBW40_CCK6_BE4 BIT(14) +#define B_OOB_CBW40_CCK7_BE4 BIT(15) +#define B_OOB_CBW40_TH0_BE4 BIT(16) +#define B_OOB_CBW40_TH1_BE4 BIT(17) +#define B_OOB_CBW40_TH2_BE4 BIT(18) +#define B_OOB_CBW40_TH3_BE4 BIT(19) +#define B_OOB_CBW40_TH4_BE4 BIT(20) +#define B_OOB_CBW40_TH5_BE4 BIT(21) +#define B_OOB_CBW40_TH6_BE4 BIT(22) +#define B_OOB_CBW40_TH7_BE4 BIT(23) +#define B_OOB_CBW40_OW0_BE4 BIT(24) +#define B_OOB_CBW40_OW1_BE4 BIT(25) +#define B_OOB_CBW40_OW2_BE4 BIT(26) +#define B_OOB_CBW40_OW3_BE4 BIT(27) +#define B_OOB_CBW40_OW4_BE4 BIT(28) +#define B_OOB_CBW40_OW5_BE4 BIT(29) +#define B_OOB_CBW40_OW6_BE4 BIT(30) +#define B_OOB_CBW40_OW7_BE4 BIT(31) +#define R_OOB_CBW80_BE4 0x119BC +#define B_OOB_CBW80_TH0_BE4 BIT(0) +#define B_OOB_CBW80_TH1_BE4 BIT(1) +#define B_OOB_CBW80_TH2_BE4 BIT(2) +#define B_OOB_CBW80_TH3_BE4 BIT(3) +#define B_OOB_CBW80_TH4_BE4 BIT(4) +#define B_OOB_CBW80_TH5_BE4 BIT(5) +#define B_OOB_CBW80_TH6_BE4 BIT(6) +#define B_OOB_CBW80_TH7_BE4 BIT(7) +#define B_OOB_CBW80_OW0_BE4 BIT(8) +#define B_OOB_CBW80_OW1_BE4 BIT(9) +#define B_OOB_CBW80_OW2_BE4 BIT(10) +#define B_OOB_CBW80_OW3_BE4 BIT(11) +#define B_OOB_CBW80_OW4_BE4 BIT(12) +#define B_OOB_CBW80_OW5_BE4 BIT(13) +#define B_OOB_CBW80_OW6_BE4 BIT(14) +#define B_OOB_CBW80_OW7_BE4 BIT(15) +#define R_DPD_DBW160_TH0_BE4 0x119BC +#define B_DPD_DBW160_TH0_0_BE4 GENMASK(18, 16) +#define B_DPD_DBW160_TH0_1_BE4 GENMASK(21, 19) +#define B_DPD_DBW160_TH0_2_BE4 GENMASK(24, 22) +#define B_DPD_DBW160_TH0_3_BE4 GENMASK(27, 25) +#define B_DPD_DBW160_TH0_4_BE4 GENMASK(30, 28) +#define R_DPD_DBW160_TH1_BE4 0x119C0 +#define B_DPD_DBW160_TH1_5_BE4 GENMASK(2, 0) +#define B_DPD_DBW160_TH1_6_BE4 GENMASK(5, 3) +#define B_DPD_DBW160_TH1_7_BE4 GENMASK(8, 6) +#define R_DPD_CBW_TH0_BE4 0x119C0 +#define B_DPD_CBW20_TH0_0_BE4 GENMASK(11, 9) +#define B_DPD_CBW20_TH0_1_BE4 GENMASK(14, 12) +#define B_DPD_CBW20_TH0_2_BE4 GENMASK(17, 15) +#define B_DPD_CBW20_TH0_3_BE4 GENMASK(20, 18) +#define B_DPD_CBW20_TH0_4_BE4 GENMASK(23, 21) +#define B_DPD_CBW20_TH0_5_BE4 GENMASK(26, 24) +#define B_DPD_CBW20_TH0_6_BE4 GENMASK(29, 27) +#define R_DPD_CBW_TH1_BE4 0x119C4 +#define B_DPD_CBW20_TH1_7_BE4 GENMASK(2, 0) +#define B_DPD_CBW40_TH1_0_BE4 GENMASK(5, 3) +#define B_DPD_CBW40_TH1_1_BE4 GENMASK(8, 6) +#define B_DPD_CBW40_TH1_2_BE4 GENMASK(11, 9) +#define B_DPD_CBW40_TH1_3_BE4 GENMASK(14, 12) +#define B_DPD_CBW40_TH1_4_BE4 GENMASK(17, 15) +#define B_DPD_CBW40_TH1_5_BE4 GENMASK(20, 18) +#define B_DPD_CBW40_TH1_6_BE4 GENMASK(23, 21) +#define B_DPD_CBW40_TH1_7_BE4 GENMASK(26, 24) +#define B_DPD_CBW80_TH1_0_BE4 GENMASK(29, 27) +#define R_DPD_CBW_TH2_BE4 0x119C8 +#define B_DPD_CBW80_TH2_1_BE4 GENMASK(2, 0) +#define B_DPD_CBW80_TH2_2_BE4 GENMASK(5, 3) +#define B_DPD_CBW80_TH2_3_BE4 GENMASK(8, 6) +#define B_DPD_CBW80_TH2_4_BE4 GENMASK(11, 9) +#define B_DPD_CBW80_TH2_5_BE4 GENMASK(14, 12) +#define B_DPD_CBW80_TH2_6_BE4 GENMASK(17, 15) +#define B_DPD_CBW80_TH2_7_BE4 GENMASK(20, 18) +#define R_QAM_TH0_BE4 0x119E4 +#define B_QAM_TH0_0_BE4 GENMASK(18, 16) +#define B_QAM_TH0_1_BE4 GENMASK(21, 19) +#define B_QAM_TH0_2_BE4 GENMASK(24, 22) +#define B_QAM_TH0_3_BE4 GENMASK(27, 25) +#define B_QAM_TH0_4_BE4 GENMASK(30, 28) +#define R_QAM_TH1_BE4 0x119E8 +#define B_QAM_TH1_0_BE4 GENMASK(2, 0) +#define B_QAM_TH1_1_BE4 GENMASK(5, 3) +#define B_QAM_TH1_2_BE4 GENMASK(8, 6) +#define B_QAM_TH1_3_BE4 GENMASK(11, 9) +#define B_QAM_TH1_4_BE4 GENMASK(14, 12) +#define B_QAM_TH1_5_BE4 GENMASK(17, 15) +#define B_QAM_TH1_6_BE4 GENMASK(20, 18) +#define B_QAM_TH1_7_BE4 GENMASK(23, 21) +#define B_QAM_TH1_8_BE4 GENMASK(26, 24) +#define B_QAM_TH1_9_BE4 GENMASK(29, 27) +#define R_QAM_TH2_BE4 0x119EC +#define B_QAM_TH2_0_BE4 GENMASK(2, 0) +#define B_QAM_TH2_1_BE4 GENMASK(5, 3) +#define B_QAM_TH2_2_BE4 GENMASK(8, 6) +#define B_QAM_TH2_3_BE4 GENMASK(11, 9) +#define B_QAM_TH2_4_BE4 GENMASK(14, 12) +#define B_QAM_TH2_5_BE4 GENMASK(17, 15) +#define B_QAM_TH2_6_BE4 GENMASK(20, 18) +#define B_QAM_TH2_7_BE4 GENMASK(23, 21) +#define B_QAM_TH2_8_BE4 GENMASK(26, 24) +#define R_RFSI_CT_DEF_BE4 0x119F0 +#define B_RFSI_CT_ER_BE4 GENMASK(18, 15) +#define B_RFSI_CT_SUBF_BE4 GENMASK(22, 19) +#define B_RFSI_CT_FTM_BE4 GENMASK(26, 23) +#define B_RFSI_CT_SENS_BE4 GENMASK(30, 27) +#define R_FBTB_CT_DEF_BE4 0x119F4 +#define B_FBTB_CT_DEF_BE GENMASK(3, 0) +#define B_FBTB_CT_PB_BE4 GENMASK(7, 4) +#define B_FBTB_CT_DL_WO_BE4 GENMASK(11, 8) +#define B_FBTB_CT_DL_BF_BE4 GENMASK(15, 12) +#define B_FBTB_CT_MUMIMO_BE4 GENMASK(19, 16) +#define B_FBTB_CT_FTM_BE4 GENMASK(23, 20) +#define B_FBTB_CT_SENS_BE4 GENMASK(27, 24) +#define R_RFSI_CT_OPT_0_BE4 0x11A94 +#define R_RFSI_CT_OPT_8_BE4 0x11A98 +#define R_QAM_COMP_TH0_BE4 0x11A9C +#define R_QAM_COMP_TH1_BE4 0x11AA0 +#define R_QAM_COMP_TH2_BE4 0x11AA4 +#define R_QAM_COMP_TH3_BE4 0x11AA8 +#define R_QAM_COMP_TH4_BE4 0x11ABC +#define B_QAM_COMP_TH4_L GENMASK(4, 0) +#define B_QAM_COMP_TH4_M GENMASK(14, 10) +#define B_QAM_COMP_TH4_H GENMASK(24, 20) +#define B_QAM_COMP_TH4_2L GENMASK(9, 5) +#define B_QAM_COMP_TH4_2M GENMASK(19, 15) +#define B_QAM_COMP_TH4_2H GENMASK(29, 25) +#define R_QAM_COMP_TH5_BE4 0x11AC0 +#define B_QAM_COMP_TH5_L GENMASK(4, 0) +#define B_QAM_COMP_TH5_M GENMASK(14, 10) +#define B_QAM_COMP_TH5_H GENMASK(24, 20) +#define B_QAM_COMP_TH5_2L GENMASK(9, 5) +#define B_QAM_COMP_TH5_2M GENMASK(19, 15) +#define B_QAM_COMP_TH5_2H GENMASK(29, 25) +#define R_QAM_COMP_TH6_BE4 0x11AC4 +#define B_QAM_COMP_TH6_L GENMASK(4, 0) +#define B_QAM_COMP_TH6_M GENMASK(14, 10) +#define B_QAM_COMP_TH6_2L GENMASK(9, 5) +#define B_QAM_COMP_TH6_2M GENMASK(19, 15) +#define R_OW_VAL_0_BE4 0x11AAC +#define R_OW_VAL_1_BE4 0x11AB0 +#define R_OW_VAL_2_BE4 0x11AB4 +#define R_OW_VAL_3_BE4 0x11AB8 +#define R_BANDEDGE_DBWX_BE4 0x11ACC +#define B_BANDEDGE_DBW20_BE4 BIT(29) +#define B_BANDEDGE_DBW40_BE4 BIT(30) +#define B_BANDEDGE_DBW80_BE4 BIT(31) +#define R_BANDEDGE_DBWY_BE4 0x11AD0 +#define B_BANDEDGE_DBW160_BE4 BIT(0) + #define R_CHINFO_SEG_BE4 0x200B4 #define B_CHINFO_SEG_LEN_BE4 GENMASK(12, 10) #define R_STS_HDR2_PARSING_BE4 0x2070C @@ -10180,6 +10384,9 @@ #define B_IFS_T3_HIS_BE4 GENMASK(15, 0) #define B_IFS_T4_HIS_BE4 GENMASK(31, 16) +#define R_TX_CFR_MANUAL_EN_BE4 0x2483C +#define B_TX_CFR_MANUAL_EN_BE4_M BIT(30) + #define R_CHINFO_OPT_BE4 0x267C8 #define B_CHINFO_OPT_BE4 GENMASK(14, 13) #define R_CHINFO_NX_BE4 0x267D0 -- cgit v1.2.3 From ee866bb4aa7826fe37974b105e1c2938247ff9c1 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Wed, 14 Jan 2026 09:39:47 +0800 Subject: wifi: rtw89: phy: write BB wrapper registers with flush BB wrapper is a hardware circuit to control TX power, and for single writing it needs an additional flush to ensure writing is properly completed. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-10-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy_be.c | 40 +++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index f64dc47a5850..d037bbb907a8 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -414,6 +414,42 @@ static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev) rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_PRST_C1_BE4, B_IQK_DPK_PRST, 0x1); } +static u32 rtw89_phy_bb_wrap_flush_addr(struct rtw89_dev *rtwdev, u32 addr) +{ + struct rtw89_hal *hal = &rtwdev->hal; + + if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) + return 0; + + if (rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7025) { + if (addr >= R_BE_PWR_MACID_PATH_BASE_V1 && + addr <= R_BE_PWR_MACID_PATH_BASE_V1 + 0xFF) + return addr + 0x800; + + if (addr >= R_BE_PWR_MACID_LMT_BASE_V1 && + addr <= R_BE_PWR_MACID_LMT_BASE_V1 + 0xFF) + return addr - 0x800; + } + + return 0; +} + +static +void rtw89_write_bb_wrap_flush(struct rtw89_dev *rtwdev, u32 addr, u32 data) +{ + /* To write registers of pwr_macid_lmt and pwr_macid_path with flush */ + u32 flush_addr; + u32 val32; + + flush_addr = rtw89_phy_bb_wrap_flush_addr(rtwdev, addr); + if (flush_addr) { + val32 = rtw89_read32(rtwdev, flush_addr); + rtw89_write32(rtwdev, flush_addr, val32); + } + + rtw89_write32(rtwdev, addr, data); +} + static void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) { @@ -425,7 +461,7 @@ void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) for (macid_idx = 0; macid_idx < 4 * max_macid; macid_idx += 4) { cr = base_macid_lmt + macid_idx; - rtw89_write32(rtwdev, cr, 0x03007F7F); + rtw89_write_bb_wrap_flush(rtwdev, cr, 0x03007F7F); } } @@ -438,7 +474,7 @@ void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev) int i, max_macid = 32; for (i = 0; i < max_macid; i++, cr += 4) - rtw89_write32(rtwdev, cr, 0x03C86000); + rtw89_write_bb_wrap_flush(rtwdev, cr, 0x03C86000); } static void rtw89_phy_bb_wrap_tpu_set_all(struct rtw89_dev *rtwdev, -- cgit v1.2.3 From a0343cdc7767578e21822bd4e0961d204add2eef Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Wed, 14 Jan 2026 09:39:48 +0800 Subject: wifi: rtw89: phy: refine initial flow of BB wrapper Set initial value of TX power and TX path per MAC ID to 0x0, and reorder initial flow as vendor driver does. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-11-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy_be.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index d037bbb907a8..2dbc194eb329 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -461,7 +461,7 @@ void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) for (macid_idx = 0; macid_idx < 4 * max_macid; macid_idx += 4) { cr = base_macid_lmt + macid_idx; - rtw89_write_bb_wrap_flush(rtwdev, cr, 0x03007F7F); + rtw89_write_bb_wrap_flush(rtwdev, cr, 0); } } @@ -474,7 +474,7 @@ void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev) int i, max_macid = 32; for (i = 0; i < max_macid; i++, cr += 4) - rtw89_write_bb_wrap_flush(rtwdev, cr, 0x03C86000); + rtw89_write_bb_wrap_flush(rtwdev, cr, 0); } static void rtw89_phy_bb_wrap_tpu_set_all(struct rtw89_dev *rtwdev, @@ -902,13 +902,13 @@ static void rtw89_phy_bb_wrap_ul_pwr(struct rtw89_dev *rtwdev) static void __rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx) { - rtw89_phy_bb_wrap_pwr_by_macid_init(rtwdev); rtw89_phy_bb_wrap_tx_path_by_macid_init(rtwdev); - rtw89_phy_bb_wrap_listen_path_en_init(rtwdev); - rtw89_phy_bb_wrap_force_cr_init(rtwdev, mac_idx); - rtw89_phy_bb_wrap_ftm_init(rtwdev, mac_idx); + rtw89_phy_bb_wrap_pwr_by_macid_init(rtwdev); rtw89_phy_bb_wrap_tpu_set_all(rtwdev, mac_idx); rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(rtwdev, mac_idx); + rtw89_phy_bb_wrap_force_cr_init(rtwdev, mac_idx); + rtw89_phy_bb_wrap_ftm_init(rtwdev, mac_idx); + rtw89_phy_bb_wrap_listen_path_en_init(rtwdev); rtw89_phy_bb_wrap_ul_pwr(rtwdev); } -- cgit v1.2.3 From 76bada91a41a08e101b05c241c0066cd85bdfa68 Mon Sep 17 00:00:00 2001 From: Po-Hao Huang Date: Wed, 14 Jan 2026 09:39:49 +0800 Subject: wifi: rtw89: phy: fix incorrect power limit by mac_id Modify the power register range based on chip ability. When not set, the default value is random. This fixes incorrect power limit on some ICs. Signed-off-by: Po-Hao Huang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-12-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy_be.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c index 2dbc194eb329..08fd24a55d85 100644 --- a/drivers/net/wireless/realtek/rtw89/phy_be.c +++ b/drivers/net/wireless/realtek/rtw89/phy_be.c @@ -455,7 +455,8 @@ void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev) { const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap; - u32 macid_idx, cr, base_macid_lmt, max_macid = 32; + u32 max_macid = rtwdev->chip->support_macid_num; + u32 macid_idx, cr, base_macid_lmt; base_macid_lmt = bb_wrap->pwr_macid_lmt; @@ -470,8 +471,9 @@ void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev) { const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap; + u32 max_macid = rtwdev->chip->support_macid_num; u32 cr = bb_wrap->pwr_macid_path; - int i, max_macid = 32; + int i; for (i = 0; i < max_macid; i++, cr += 4) rtw89_write_bb_wrap_flush(rtwdev, cr, 0); -- cgit v1.2.3 From 6f6d7a325fbde4f025ee1b1277f6f44727e21223 Mon Sep 17 00:00:00 2001 From: Po-Hao Huang Date: Wed, 14 Jan 2026 09:39:50 +0800 Subject: wifi: rtw89: fix unable to receive probe responses under MLO connection During MLO connections, A1 of the probe responses we received are in link address, these frames will then be dropped by mac80211 due to not matching the MLD address in ieee80211_scan_accept_presp(). Fix this by using MLD address to scan when not using random MAC address. Signed-off-by: Po-Hao Huang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114013950.19704-13-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index f09387e089a2..0691341b9c83 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -8779,6 +8779,7 @@ int rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct cfg80211_scan_request *req = &scan_req->req; const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); + struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; struct rtw89_chanctx_pause_parm pause_parm = { .rsn = RTW89_CHANCTX_PAUSE_REASON_HW_SCAN, @@ -8807,6 +8808,8 @@ int rtw89_hw_scan_start(struct rtw89_dev *rtwdev, if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) get_random_mask_addr(mac_addr, req->mac_addr, req->mac_addr_mask); + else if (ieee80211_vif_is_mld(vif)) + ether_addr_copy(mac_addr, vif->addr); else ether_addr_copy(mac_addr, rtwvif_link->mac_addr); -- cgit v1.2.3 From 5f65ebf9aaf00c7443252136066138435ec03958 Mon Sep 17 00:00:00 2001 From: Shin-Yi Lin Date: Wed, 14 Jan 2026 09:49:06 +0800 Subject: wifi: rtw89: Add default ID 28de:2432 for RTL8832CU Add 28de:2432 for RTL8832CU-based adapters that use this default ID. Signed-off-by: Shin-Yi Lin Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260114014906.21829-1-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/rtw8852cu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852cu.c b/drivers/net/wireless/realtek/rtw89/rtw8852cu.c index 2708b523ca14..3b9825c92a0d 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852cu.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852cu.c @@ -46,6 +46,8 @@ static const struct usb_device_id rtw_8852cu_id_table[] = { .driver_info = (kernel_ulong_t)&rtw89_8852cu_info }, { USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0x991d, 0xff, 0xff, 0xff), .driver_info = (kernel_ulong_t)&rtw89_8852cu_info }, + { USB_DEVICE_AND_INTERFACE_INFO(0x28de, 0x2432, 0xff, 0xff, 0xff), + .driver_info = (kernel_ulong_t)&rtw89_8852cu_info }, { USB_DEVICE_AND_INTERFACE_INFO(0x35b2, 0x0502, 0xff, 0xff, 0xff), .driver_info = (kernel_ulong_t)&rtw89_8852cu_info }, { USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0101, 0xff, 0xff, 0xff), -- cgit v1.2.3 From 6070a44051b1c35714fa130de7726cfe91ca5559 Mon Sep 17 00:00:00 2001 From: Zilin Guan Date: Fri, 16 Jan 2026 13:08:34 +0000 Subject: wifi: rtw89: debug: Fix memory leak in __print_txpwr_map() In __print_txpwr_map(), memory is allocated to bufp via vzalloc(). If max_valid_addr is 0, the function returns -EOPNOTSUPP immediately without freeing bufp, leading to a memory leak. Since the validation of max_valid_addr does not depend on the allocated memory, fix this by moving the vzalloc() call after the check. Compile tested only. Issue found using a prototype static analysis tool and code review. Fixes: 036042e15770 ("wifi: rtw89: debug: txpwr table supports Wi-Fi 7 chips") Suggested-by: Zong-Zhe Yang Signed-off-by: Zilin Guan Reviewed-by: Zong-Zhe Yang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260116130834.1413924-1-zilin@seu.edu.cn --- drivers/net/wireless/realtek/rtw89/debug.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c index 2b48ccea27fb..969b9c7e35a3 100644 --- a/drivers/net/wireless/realtek/rtw89/debug.c +++ b/drivers/net/wireless/realtek/rtw89/debug.c @@ -826,10 +826,6 @@ static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t buf s8 *bufp, tmp; int ret; - bufp = vzalloc(map->addr_to - map->addr_from + 4); - if (!bufp) - return -ENOMEM; - if (path_num == 1) max_valid_addr = map->addr_to_1ss; else @@ -838,6 +834,10 @@ static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t buf if (max_valid_addr == 0) return -EOPNOTSUPP; + bufp = vzalloc(map->addr_to - map->addr_from + 4); + if (!bufp) + return -ENOMEM; + for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); if (ret) -- cgit v1.2.3 From 32f6bf1872cb41c46e601c1c59e55b78699d0a0d Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Sat, 17 Jan 2026 12:41:49 +0800 Subject: wifi: rtw89: phy: add chip_ops to calculate RX gain from efuse to support PS mode In PS mode, it needs to restore RX gain settings while waking up. Add to get RX gain values from chip specific ops, and pass these data to firmware when going to enter PS mode. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-2-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/core.h | 25 +++++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/rtw8851b.c | 1 + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 1 + drivers/net/wireless/realtek/rtw89/rtw8852b.c | 1 + drivers/net/wireless/realtek/rtw89/rtw8852bt.c | 1 + drivers/net/wireless/realtek/rtw89/rtw8852c.c | 1 + drivers/net/wireless/realtek/rtw89/rtw8922a.c | 1 + 7 files changed, 31 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h index d2eb7c66f041..dd99638c6e3d 100644 --- a/drivers/net/wireless/realtek/rtw89/core.h +++ b/drivers/net/wireless/realtek/rtw89/core.h @@ -23,6 +23,7 @@ struct rtw89_efuse_block_cfg; struct rtw89_h2c_rf_tssi; struct rtw89_fw_txpwr_track_cfg; struct rtw89_phy_rfk_log_fmt; +struct rtw89_phy_calc_efuse_gain; struct rtw89_debugfs; struct rtw89_regd_data; struct rtw89_wow_cam_info; @@ -3822,6 +3823,11 @@ struct rtw89_chip_ops { s8 pw_ofst, enum rtw89_mac_idx mac_idx); void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); + void (*calc_rx_gain_normal)(struct rtw89_dev *rtwdev, + const struct rtw89_chan *chan, + enum rtw89_rf_path path, + enum rtw89_phy_idx phy_idx, + struct rtw89_phy_calc_efuse_gain *calc); int (*pwr_on_func)(struct rtw89_dev *rtwdev); int (*pwr_off_func)(struct rtw89_dev *rtwdev); void (*query_rxdesc)(struct rtw89_dev *rtwdev, @@ -5887,6 +5893,12 @@ struct rtw89_phy_efuse_gain { s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ }; +struct rtw89_phy_calc_efuse_gain { + s8 cck_mean_gain_bias; + s8 cck_rpl_ofst; + s8 rssi_ofst; +}; + #define RTW89_MAX_PATTERN_NUM 18 #define RTW89_MAX_PATTERN_MASK_SIZE 4 #define RTW89_MAX_PATTERN_SIZE 128 @@ -7341,6 +7353,19 @@ static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, chip->ops->digital_pwr_comp(rtwdev, phy_idx); } +static inline +void rtw89_chip_calc_rx_gain_normal(struct rtw89_dev *rtwdev, + const struct rtw89_chan *chan, + enum rtw89_rf_path path, + enum rtw89_phy_idx phy_idx, + struct rtw89_phy_calc_efuse_gain *calc) +{ + const struct rtw89_chip_info *chip = rtwdev->chip; + + if (chip->ops->calc_rx_gain_normal) + chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc); +} + static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, const struct rtw89_txpwr_table *tbl) { diff --git a/drivers/net/wireless/realtek/rtw89/rtw8851b.c b/drivers/net/wireless/realtek/rtw89/rtw8851b.c index 0383d3b5c7bc..d6deb44a685b 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8851b.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8851b.c @@ -2530,6 +2530,7 @@ static const struct rtw89_chip_ops rtw8851b_chip_ops = { .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path, .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset, .digital_pwr_comp = NULL, + .calc_rx_gain_normal = NULL, .pwr_on_func = rtw8851b_pwr_on_func, .pwr_off_func = rtw8851b_pwr_off_func, .query_rxdesc = rtw89_core_query_rxdesc, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c index 329fc0a7b07b..5ea7a36ab5ab 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852a.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c @@ -2224,6 +2224,7 @@ static const struct rtw89_chip_ops rtw8852a_chip_ops = { .cfg_txrx_path = NULL, .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, .digital_pwr_comp = NULL, + .calc_rx_gain_normal = NULL, .pwr_on_func = NULL, .pwr_off_func = NULL, .query_rxdesc = rtw89_core_query_rxdesc, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b.c b/drivers/net/wireless/realtek/rtw89/rtw8852b.c index f44674a39e30..197e3f5fb21b 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852b.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852b.c @@ -857,6 +857,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = { .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path, .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset, .digital_pwr_comp = NULL, + .calc_rx_gain_normal = NULL, .pwr_on_func = rtw8852b_pwr_on_func, .pwr_off_func = rtw8852b_pwr_off_func, .query_rxdesc = rtw89_core_query_rxdesc, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852bt.c b/drivers/net/wireless/realtek/rtw89/rtw8852bt.c index ab60ed389ff7..92bbd6e5d699 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852bt.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852bt.c @@ -703,6 +703,7 @@ static const struct rtw89_chip_ops rtw8852bt_chip_ops = { .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path, .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset, .digital_pwr_comp = NULL, + .calc_rx_gain_normal = NULL, .pwr_on_func = rtw8852bt_pwr_on_func, .pwr_off_func = rtw8852bt_pwr_off_func, .query_rxdesc = rtw89_core_query_rxdesc, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852c.c b/drivers/net/wireless/realtek/rtw89/rtw8852c.c index d2138be3640d..de5d343f80a5 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852c.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852c.c @@ -3065,6 +3065,7 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = { .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, .digital_pwr_comp = NULL, + .calc_rx_gain_normal = NULL, .pwr_on_func = rtw8852c_pwr_on_func, .pwr_off_func = rtw8852c_pwr_off_func, .query_rxdesc = rtw89_core_query_rxdesc, diff --git a/drivers/net/wireless/realtek/rtw89/rtw8922a.c b/drivers/net/wireless/realtek/rtw89/rtw8922a.c index 6d2cd914e16e..0a3c2207dd4b 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8922a.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8922a.c @@ -2838,6 +2838,7 @@ static const struct rtw89_chip_ops rtw8922a_chip_ops = { .cfg_txrx_path = rtw8922a_bb_cfg_txrx_path, .set_txpwr_ul_tb_offset = NULL, .digital_pwr_comp = rtw8922a_digital_pwr_comp, + .calc_rx_gain_normal = NULL, .pwr_on_func = rtw8922a_pwr_on_func, .pwr_off_func = rtw8922a_pwr_off_func, .query_rxdesc = rtw89_core_query_rxdesc_v2, -- cgit v1.2.3 From 496a0752fe5042908c8dd44d477916fa83414595 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Sat, 17 Jan 2026 12:41:50 +0800 Subject: wifi: rtw89: phy: handle C2H event for PS mode report Introduce support for processing the new PS C2H report, enabling detailed debugging of low-power state hardware changes. Signed-off-by: Eric Huang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-3-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/debug.h | 1 + drivers/net/wireless/realtek/rtw89/fw.h | 20 ++++++++++ drivers/net/wireless/realtek/rtw89/phy.c | 59 ++++++++++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/phy.h | 1 + 4 files changed, 81 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/debug.h b/drivers/net/wireless/realtek/rtw89/debug.h index a364e7adb079..7cdceb24f52d 100644 --- a/drivers/net/wireless/realtek/rtw89/debug.h +++ b/drivers/net/wireless/realtek/rtw89/debug.h @@ -31,6 +31,7 @@ enum rtw89_debug_mask { RTW89_DBG_CHAN = BIT(20), RTW89_DBG_ACPI = BIT(21), RTW89_DBG_EDCCA = BIT(22), + RTW89_DBG_PS = BIT(23), RTW89_DBG_UNEXP = BIT(31), }; diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index 018b3bed57d2..12e798f01df7 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -3829,6 +3829,26 @@ struct rtw89_c2h_ra_rpt { #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15) #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16) +struct rtw89_c2h_lps_rpt { + struct rtw89_c2h_hdr hdr; + u8 type; + u8 cnt_bbcr; + u8 cnt_bbmcucr; + u8 cnt_rfcr; + u8 data[]; + /* + * The layout of data: + * u8 info[][4], size = total_len - size of below fields + * __le16 bbcr_addr[], size = cnt_bbcr + * __le32 bbcr_data[], size = cnt_bbcr + * __le16 bbmcucr_addr[], size = cnt_bbmcucr + * __le32 bbmcucr_data[], size = cnt_bbmcucr + * __le16 rfcr_addr[], size = cnt_rfcr + * __le32 rfcr_data_a[], size = cnt_rfcr + * __le32 rfcr_data_b[], size = cnt_rfcr + */ +} __packed; + struct rtw89_c2h_fw_scan_rpt { struct rtw89_c2h_hdr hdr; u8 phy_idx; diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index d311de093425..6fd903b44bdb 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -3339,6 +3339,64 @@ rtw89_phy_c2h_lowrt_rty(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) { } +static void +rtw89_phy_c2h_lps_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) +{ + const struct rtw89_c2h_lps_rpt *c2h_rpt = (const void *)c2h->data; + const __le32 *data_a, *data_b; + u16 len_info, cr_len, idx; + const __le16 *addr; + const u8 *info; + + /* elements size of BBCR/BBMCUCR/RFCR are 6/6/10 bytes respectively */ + cr_len = c2h_rpt->cnt_bbcr * 6 + + c2h_rpt->cnt_bbmcucr * 6 + + c2h_rpt->cnt_rfcr * 10; + len_info = len - (sizeof(*c2h_rpt) + cr_len); + + if (len < sizeof(*c2h_rpt) + cr_len || len_info % 4 != 0) { + rtw89_debug(rtwdev, RTW89_DBG_PS, + "Invalid LPS RPT len(%d) TYPE(%d) CRCNT: BB(%d) MCU(%d) RF(%d)\n", + len, c2h_rpt->type, c2h_rpt->cnt_bbcr, + c2h_rpt->cnt_bbmcucr, c2h_rpt->cnt_rfcr); + return; + } + + rtw89_debug(rtwdev, RTW89_DBG_PS, + "LPS RPT TYPE(%d), CRCNT: BB(%d) MCU(%d) RF(%d)\n", + c2h_rpt->type, c2h_rpt->cnt_bbcr, + c2h_rpt->cnt_bbmcucr, c2h_rpt->cnt_rfcr); + + info = &c2h_rpt->data[0]; + for (idx = 0; idx < len_info; idx += 4, info += 4) + rtw89_debug(rtwdev, RTW89_DBG_PS, + "BB LPS INFO (%02d) - 0x%02x,0x%02x,0x%02x,0x%02x\n", + idx, info[3], info[2], info[1], info[0]); + + addr = (const void *)(info); + data_a = (const void *)(addr + c2h_rpt->cnt_bbcr); + for (idx = 0; idx < c2h_rpt->cnt_bbcr; idx++, addr++, data_a++) + rtw89_debug(rtwdev, RTW89_DBG_PS, + "LPS BB CR - 0x%04x=0x%08x\n", + le16_to_cpu(*addr), le32_to_cpu(*data_a)); + + addr = (const void *)data_a; + data_a = (const void *)(addr + c2h_rpt->cnt_bbmcucr); + for (idx = 0; idx < c2h_rpt->cnt_bbmcucr; idx++, addr++, data_a++) + rtw89_debug(rtwdev, RTW89_DBG_PS, + "LPS BBMCU - 0x%04x=0x%08x\n", + le16_to_cpu(*addr), le32_to_cpu(*data_a)); + + addr = (const void *)data_a; + data_a = (const void *)(addr + c2h_rpt->cnt_rfcr); + data_b = (const void *)(data_a + c2h_rpt->cnt_rfcr); + for (idx = 0; idx < c2h_rpt->cnt_rfcr; idx++, addr++, data_a++, data_b++) + rtw89_debug(rtwdev, RTW89_DBG_PS, + "LPS RFCR - 0x%04x=0x%05x,0x%05x\n", + le16_to_cpu(*addr), le32_to_cpu(*data_a), + le32_to_cpu(*data_b)); +} + static void rtw89_phy_c2h_fw_scan_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) { @@ -3360,6 +3418,7 @@ void (* const rtw89_phy_c2h_dm_handler[])(struct rtw89_dev *rtwdev, [RTW89_PHY_C2H_DM_FUNC_SIGB] = NULL, [RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY] = rtw89_phy_c2h_lowrt_rty, [RTW89_PHY_C2H_DM_FUNC_MCC_DIG] = NULL, + [RTW89_PHY_C2H_DM_FUNC_LPS] = rtw89_phy_c2h_lps_rpt, [RTW89_PHY_C2H_DM_FUNC_FW_SCAN] = rtw89_phy_c2h_fw_scan_rpt, }; diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 4e985a604338..0c5224780e84 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -165,6 +165,7 @@ enum rtw89_phy_c2h_dm_func { RTW89_PHY_C2H_DM_FUNC_SIGB, RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, RTW89_PHY_C2H_DM_FUNC_MCC_DIG, + RTW89_PHY_C2H_DM_FUNC_LPS = 0x9, RTW89_PHY_C2H_DM_FUNC_FW_SCAN = 0xc, RTW89_PHY_C2H_DM_FUNC_NUM, }; -- cgit v1.2.3 From 20380a039ddd6504e663d3701e55e29a20da5721 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Sat, 17 Jan 2026 12:41:51 +0800 Subject: wifi: rtw89: phy: add H2C command to send detail RX gain and link parameters for PS mode Introduce support for a new PS multi-link common info version (v1) for RTL8922D, enabling the driver to send detailed RX gain and link parameters to firmware via a new H2C command. A dedicated 20 MHz beacon channel (chan_bcn) that replicates the primary channel and band type of the original channel but forces a 20 MHz width. This ensures that beacon mode always reference the 20 MHz gain table, fixing the mis-assignment that could degrade signal strength or cause incorrect RSSI calibration. Signed-off-by: Eric Huang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-4-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/core.h | 1 + drivers/net/wireless/realtek/rtw89/fw.c | 155 ++++++++++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/fw.h | 65 +++++++++++++ drivers/net/wireless/realtek/rtw89/ps.c | 2 + drivers/net/wireless/realtek/rtw89/reg.h | 1 + 5 files changed, 224 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h index dd99638c6e3d..363d1bbe6869 100644 --- a/drivers/net/wireless/realtek/rtw89/core.h +++ b/drivers/net/wireless/realtek/rtw89/core.h @@ -4767,6 +4767,7 @@ enum rtw89_fw_feature { RTW89_FW_FEATURE_ADDR_CAM_V0, RTW89_FW_FEATURE_SER_L1_BY_EVENT, RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C, + RTW89_FW_FEATURE_LPS_ML_INFO_V1, NUM_OF_RTW89_FW_FEATURES, }; diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index 0691341b9c83..b635579e90d3 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -3264,6 +3264,161 @@ fail: return ret; } +void rtw89_bb_lps_cmn_info_rx_gain_fill(struct rtw89_dev *rtwdev, + struct rtw89_bb_link_info_rx_gain *h2c_gain, + const struct rtw89_chan *chan, u8 phy_idx) +{ + const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be; + enum rtw89_bb_link_rx_gain_table_type tab_idx; + struct rtw89_chan chan_bcn; + u8 bw = chan->band_width; + u8 gain_band; + u8 bw_idx; + u8 path; + int i; + + rtw89_chan_create(&chan_bcn, chan->primary_channel, chan->primary_channel, + chan->band_type, RTW89_CHANNEL_WIDTH_20); + + for (tab_idx = RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_A; + tab_idx < RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX; tab_idx++) { + struct rtw89_phy_calc_efuse_gain calc = {}; + + path = (tab_idx & BIT(0)) ? (RF_PATH_B) : (RF_PATH_A); + if (tab_idx & BIT(1)) { + rtw89_chip_calc_rx_gain_normal(rtwdev, chan, path, phy_idx, + &calc); + gain_band = rtw89_subband_to_gain_band_be(chan->subband_type); + if (bw > RTW89_CHANNEL_WIDTH_40) + bw_idx = RTW89_BB_BW_80_160_320; + else + bw_idx = RTW89_BB_BW_20_40; + } else { + rtw89_chip_calc_rx_gain_normal(rtwdev, &chan_bcn, path, phy_idx, + &calc); + gain_band = rtw89_subband_to_gain_band_be(chan_bcn.subband_type); + bw_idx = RTW89_BB_BW_20_40; + } + + /* efuse ofst and comp */ + h2c_gain->gain_ofst[tab_idx] = calc.rssi_ofst; + h2c_gain->cck_gain_ofst[tab_idx] = calc.cck_rpl_ofst; + h2c_gain->cck_rpl_bias_comp[tab_idx][0] = calc.cck_mean_gain_bias; + h2c_gain->cck_rpl_bias_comp[tab_idx][1] = calc.cck_mean_gain_bias; + + for (i = 0; i < TIA_GAIN_NUM; i++) { + h2c_gain->gain_err_tia[tab_idx][i] = + cpu_to_le16(gain->tia_gain[gain_band][bw_idx][path][i]); + } + memcpy(h2c_gain->gain_err_lna[tab_idx], + gain->lna_gain[gain_band][bw_idx][path], + LNA_GAIN_NUM); + memcpy(h2c_gain->op1db_lna[tab_idx], + gain->lna_op1db[gain_band][bw_idx][path], + LNA_GAIN_NUM); + memcpy(h2c_gain->op1db_tia[tab_idx], + gain->tia_lna_op1db[gain_band][bw_idx][path], + LNA_GAIN_NUM + 1); + + memcpy(h2c_gain->rpl_bias_comp_bw[tab_idx]._20M, + gain->rpl_ofst_20[gain_band][path], + RTW89_BW20_SC_20M); + memcpy(h2c_gain->rpl_bias_comp_bw[tab_idx]._40M, + gain->rpl_ofst_40[gain_band][path], + RTW89_BW20_SC_40M); + memcpy(h2c_gain->rpl_bias_comp_bw[tab_idx]._80M, + gain->rpl_ofst_80[gain_band][path], + RTW89_BW20_SC_80M); + memcpy(h2c_gain->rpl_bias_comp_bw[tab_idx]._160M, + gain->rpl_ofst_160[gain_band][path], + RTW89_BW20_SC_160M); + } +} + +int rtw89_fw_h2c_lps_ml_cmn_info_v1(struct rtw89_dev *rtwdev, + struct rtw89_vif *rtwvif) +{ + static const u8 bcn_bw_ofst[] = {0, 0, 0, 3, 6, 9, 0, 12}; + const struct rtw89_chip_info *chip = rtwdev->chip; + struct rtw89_efuse *efuse = &rtwdev->efuse; + struct rtw89_h2c_lps_ml_cmn_info_v1 *h2c; + struct rtw89_vif_link *rtwvif_link; + const struct rtw89_chan *chan; + struct rtw89_bb_ctx *bb; + u32 len = sizeof(*h2c); + unsigned int link_id; + struct sk_buff *skb; + u8 beacon_bw_ofst; + u32 done; + int ret; + + if (chip->chip_gen != RTW89_CHIP_BE) + return 0; + + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); + if (!skb) { + rtw89_err(rtwdev, "failed to alloc skb for h2c lps_ml_cmn_info_v1\n"); + return -ENOMEM; + } + skb_put(skb, len); + h2c = (struct rtw89_h2c_lps_ml_cmn_info_v1 *)skb->data; + + h2c->fmt_id = 0x20; + + h2c->mlo_dbcc_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode); + h2c->rfe_type = efuse->rfe_type; + h2c->rssi_main = U8_MAX; + + memset(h2c->link_id, 0xfe, RTW89_BB_PS_LINK_BUF_MAX); + + rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) { + u8 phy_idx = rtwvif_link->phy_idx; + + bb = rtw89_get_bb_ctx(rtwdev, phy_idx); + chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); + + h2c->link_id[phy_idx] = phy_idx; + h2c->central_ch[phy_idx] = chan->channel; + h2c->pri_ch[phy_idx] = chan->primary_channel; + h2c->band[phy_idx] = chan->band_type; + h2c->bw[phy_idx] = chan->band_width; + + if (rtwvif_link->bcn_bw_idx < ARRAY_SIZE(bcn_bw_ofst)) { + beacon_bw_ofst = bcn_bw_ofst[rtwvif_link->bcn_bw_idx]; + h2c->dup_bcn_ofst[phy_idx] = beacon_bw_ofst; + } + + if (h2c->rssi_main > bb->ch_info.rssi_min) + h2c->rssi_main = bb->ch_info.rssi_min; + + rtw89_bb_lps_cmn_info_rx_gain_fill(rtwdev, + &h2c->rx_gain[phy_idx], + chan, phy_idx); + } + + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, + H2C_CAT_OUTSRC, H2C_CL_OUTSRC_DM, + H2C_FUNC_FW_LPS_ML_CMN_INFO, 0, 0, len); + + rtw89_phy_write32_mask(rtwdev, R_CHK_LPS_STAT_BE4, B_CHK_LPS_STAT, 0); + ret = rtw89_h2c_tx(rtwdev, skb, false); + if (ret) { + rtw89_err(rtwdev, "failed to send h2c\n"); + goto fail; + } + + ret = read_poll_timeout(rtw89_phy_read32_mask, done, done, 50, 5000, + true, rtwdev, R_CHK_LPS_STAT_BE4, B_CHK_LPS_STAT); + if (ret) + rtw89_warn(rtwdev, "h2c_lps_ml_cmn_info done polling timeout\n"); + + return 0; +fail: + dev_kfree_skb_any(skb); + + return ret; +} + #define H2C_P2P_ACT_LEN 20 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index 12e798f01df7..146403d285b4 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -2017,6 +2017,66 @@ struct rtw89_h2c_lps_ml_cmn_info { u8 dup_bcn_ofst[RTW89_PHY_NUM]; } __packed; +#define BB_RX_GAIN_TB_RSSI_COMP_NUM 3 +#define BB_RX_GAIN_CCK_RPL_BIAS_COMP_NUM 2 +#define BB_GT2_GS_IDX_NUM 11 +#define BB_GT2_WB_GIDX_ELNA_NUM 16 +#define BB_GT2_G_ELNA_NUM 2 + +enum rtw89_bb_link_rx_gain_table_type { + RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_A = 0x00, + RTW89_BB_PS_LINK_RX_GAIN_TAB_BCN_PATH_B = 0x01, + RTW89_BB_PS_LINK_RX_GAIN_TAB_NOR_PATH_A = 0x02, + RTW89_BB_PS_LINK_RX_GAIN_TAB_NOR_PATH_B = 0x03, + RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX, +}; + +enum rtw89_bb_ps_link_buf_id { + RTW89_BB_PS_LINK_BUF_0 = 0x00, + RTW89_BB_PS_LINK_BUF_1 = 0x01, + RTW89_BB_PS_LINK_BUF_2 = 0x02, + RTW89_BB_PS_LINK_BUF_MAX, +}; + +struct rtw89_bb_link_info_rx_gain { + u8 gain_ofst[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]; + __le16 rpl_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]; + u8 tb_rssi_m_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX] + [BB_RX_GAIN_TB_RSSI_COMP_NUM]; + u8 cck_gain_ofst[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]; + u8 cck_rpl_bias_comp[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX] + [BB_RX_GAIN_CCK_RPL_BIAS_COMP_NUM]; + u8 gain_err_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM]; + __le16 gain_err_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][TIA_GAIN_NUM]; + u8 op1db_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM]; + u8 op1db_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][TIA_LNA_OP1DB_NUM]; + struct { + u8 _20M[RTW89_BW20_SC_20M]; + u8 _40M[RTW89_BW20_SC_40M]; + u8 _80M[RTW89_BW20_SC_80M]; + u8 _160M[RTW89_BW20_SC_160M]; + } rpl_bias_comp_bw[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX]; + u8 wb_gs[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_GS_IDX_NUM]; + u8 bypass_lna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][LNA_GAIN_NUM]; + u8 wb_lna_tia[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_WB_GIDX_ELNA_NUM]; + u8 wb_g_elna[RTW89_BB_PS_LINK_RX_GAIN_TAB_MAX][BB_GT2_G_ELNA_NUM]; +} __packed; + +struct rtw89_h2c_lps_ml_cmn_info_v1 { + u8 fmt_id; + u8 rfe_type; + u8 rssi_main; + u8 rsvd0; + __le32 mlo_dbcc_mode; + u8 link_id[RTW89_BB_PS_LINK_BUF_MAX]; + u8 central_ch[RTW89_BB_PS_LINK_BUF_MAX]; + u8 pri_ch[RTW89_BB_PS_LINK_BUF_MAX]; + u8 bw[RTW89_BB_PS_LINK_BUF_MAX]; + u8 band[RTW89_BB_PS_LINK_BUF_MAX]; + u8 dup_bcn_ofst[RTW89_BB_PS_LINK_BUF_MAX]; + struct rtw89_bb_link_info_rx_gain rx_gain[RTW89_BB_PS_LINK_BUF_MAX]; +} __packed; + struct rtw89_h2c_trig_cpu_except { __le32 w0; } __packed; @@ -5204,6 +5264,11 @@ int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); +void rtw89_bb_lps_cmn_info_rx_gain_fill(struct rtw89_dev *rtwdev, + struct rtw89_bb_link_info_rx_gain *h2c_gain, + const struct rtw89_chan *chan, u8 phy_idx); +int rtw89_fw_h2c_lps_ml_cmn_info_v1(struct rtw89_dev *rtwdev, + struct rtw89_vif *rtwvif); int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, bool enable); struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); diff --git a/drivers/net/wireless/realtek/rtw89/ps.c b/drivers/net/wireless/realtek/rtw89/ps.c index abd8aee02b47..aad2ee7926d6 100644 --- a/drivers/net/wireless/realtek/rtw89/ps.c +++ b/drivers/net/wireless/realtek/rtw89/ps.c @@ -189,6 +189,8 @@ void rtw89_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, if (RTW89_CHK_FW_FEATURE(LPS_CH_INFO, &rtwdev->fw)) rtw89_fw_h2c_lps_ch_info(rtwdev, rtwvif); + else if (RTW89_CHK_FW_FEATURE(LPS_ML_INFO_V1, &rtwdev->fw)) + rtw89_fw_h2c_lps_ml_cmn_info_v1(rtwdev, rtwvif); else rtw89_fw_h2c_lps_ml_cmn_info(rtwdev, rtwvif); diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 895795228268..3239f358aafc 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -8620,6 +8620,7 @@ #define B_UPD_P0_EN BIT(31) #define R_EMLSR 0x0044 #define B_EMLSR_PARM GENMASK(27, 12) +#define R_CHK_LPS_STAT_BE4 0x3007C #define R_CHK_LPS_STAT 0x0058 #define B_CHK_LPS_STAT BIT(0) #define R_SPOOF_CG 0x00B4 -- cgit v1.2.3 From bcd23ebfef1c292e8965ac116bc0f88f7e7d3bbc Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Sat, 17 Jan 2026 12:41:52 +0800 Subject: wifi: rtw89: phy: update edcca log parsing for RTL8922D Before this change the rtw89_phy_edcca_log routine didn't handled RTL8922D. This update expands the logic to recognize RTL8922D EDCCA reports. Signed-off-by: Eric Huang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-5-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/phy.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 6fd903b44bdb..c9bd3b7c5489 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -7980,6 +7980,7 @@ static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *b bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80; s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80; u8 path, per20_bitmap = 0; + u8 pwdb_sel = 5; u8 pwdb[8]; u32 tmp; @@ -7991,12 +7992,14 @@ static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *b else edcca_p_regs = &edcca_regs->p[RTW89_PHY_0]; - if (rtwdev->chip->chip_id == RTL8922A) - rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, - edcca_regs->rpt_sel_be_mask, 0); - rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, edcca_p_regs->rpt_sel_mask, 0); + if (rtwdev->chip->chip_id == RTL8922A || rtwdev->chip->chip_id == RTL8922D) { + rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, + edcca_regs->rpt_sel_be_mask, 0); + per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a, + MASKBYTE0); + } tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK); flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80); @@ -8008,13 +8011,16 @@ static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *b pwdb_p20 = u32_get_bits(tmp, MASKBYTE2); pwdb_fb = u32_get_bits(tmp, MASKBYTE3); + if (rtwdev->chip->chip_id == RTL8922D) + pwdb_sel = 2; + rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, - edcca_p_regs->rpt_sel_mask, 5); + edcca_p_regs->rpt_sel_mask, pwdb_sel); tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); pwdb_s80 = u32_get_bits(tmp, MASKBYTE1); pwdb_s40 = u32_get_bits(tmp, MASKBYTE2); - if (rtwdev->chip->chip_id == RTL8922A) { + if (rtwdev->chip->chip_id == RTL8922A || rtwdev->chip->chip_id == RTL8922D) { rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, edcca_regs->rpt_sel_be_mask, 4); tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); @@ -8022,8 +8028,6 @@ static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *b pwdb[1] = u32_get_bits(tmp, MASKBYTE2); pwdb[2] = u32_get_bits(tmp, MASKBYTE1); pwdb[3] = u32_get_bits(tmp, MASKBYTE0); - per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a, - MASKBYTE0); rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, edcca_regs->rpt_sel_be_mask, 5); -- cgit v1.2.3 From 4809013c088c2e211f2c8e2560ce63924a82a43f Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Sat, 17 Jan 2026 12:41:53 +0800 Subject: wifi: rtw89: phy: add firmware element of digital TX power compensation Define and set compensation value to corresponding frequency bands. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-6-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/chan.c | 23 +++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/core.h | 12 ++++++++++++ drivers/net/wireless/realtek/rtw89/fw.c | 23 +++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/fw.h | 1 + 4 files changed, 59 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/chan.c b/drivers/net/wireless/realtek/rtw89/chan.c index 0b5509468582..c0af61992226 100644 --- a/drivers/net/wireless/realtek/rtw89/chan.c +++ b/drivers/net/wireless/realtek/rtw89/chan.c @@ -60,6 +60,28 @@ static enum rtw89_subband rtw89_get_subband_type(enum rtw89_band band, } } +static enum rtw89_tx_comp_band rtw89_get_tx_comp_band(enum rtw89_band band, + u8 center_chan) +{ + switch (band) { + default: + case RTW89_BAND_2G: + return RTW89_TX_COMP_BAND_2GHZ; + case RTW89_BAND_5G: + if (center_chan < 149) + return RTW89_TX_COMP_BAND_5GHZ_L; + else + return RTW89_TX_COMP_BAND_5GHZ_H; + case RTW89_BAND_6G: + if (center_chan < 65) + return RTW89_TX_COMP_BAND_5GHZ_H; + else if (center_chan < 193) + return RTW89_TX_COMP_BAND_6GHZ_M; + else + return RTW89_TX_COMP_BAND_6GHZ_UH; + } +} + static enum rtw89_sc_offset rtw89_get_primary_chan_idx(enum rtw89_bandwidth bw, u32 center_freq, u32 primary_freq) @@ -123,6 +145,7 @@ void rtw89_chan_create(struct rtw89_chan *chan, u8 center_chan, u8 primary_chan, chan->freq = center_freq; chan->subband_type = rtw89_get_subband_type(band, center_chan); + chan->tx_comp_band = rtw89_get_tx_comp_band(band, center_chan); chan->pri_ch_idx = rtw89_get_primary_chan_idx(bandwidth, center_freq, primary_freq); chan->pri_sb_idx = rtw89_get_primary_sb_idx(center_chan, primary_chan, diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h index 363d1bbe6869..4778957d6b2d 100644 --- a/drivers/net/wireless/realtek/rtw89/core.h +++ b/drivers/net/wireless/realtek/rtw89/core.h @@ -115,6 +115,16 @@ enum rtw89_subband { RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, }; +enum rtw89_tx_comp_band { + RTW89_TX_COMP_BAND_2GHZ, + RTW89_TX_COMP_BAND_5GHZ_L, + RTW89_TX_COMP_BAND_5GHZ_H, + RTW89_TX_COMP_BAND_6GHZ_M, + RTW89_TX_COMP_BAND_6GHZ_UH, + + RTW89_TX_COMP_BAND_NR, +}; + enum rtw89_gain_offset { RTW89_GAIN_OFFSET_2G_CCK, RTW89_GAIN_OFFSET_2G_OFDM, @@ -991,6 +1001,7 @@ struct rtw89_chan { */ u32 freq; enum rtw89_subband subband_type; + enum rtw89_tx_comp_band tx_comp_band; enum rtw89_sc_offset pri_ch_idx; u8 pri_sb_idx; }; @@ -4831,6 +4842,7 @@ struct rtw89_fw_elm_info { const struct rtw89_regd_data *regd; const struct rtw89_fw_element_hdr *afe; const struct rtw89_fw_element_hdr *diag_mac; + const struct rtw89_fw_element_hdr *tx_comp; }; enum rtw89_fw_mss_dev_type { diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index b635579e90d3..5e405b57121f 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -1382,6 +1382,26 @@ int rtw89_recognize_diag_mac_from_elm(struct rtw89_dev *rtwdev, return 0; } +static +int rtw89_build_tx_comp_from_elm(struct rtw89_dev *rtwdev, + const struct rtw89_fw_element_hdr *elm, + const union rtw89_fw_element_arg arg) +{ + struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; + struct rtw89_hal *hal = &rtwdev->hal; + u16 aid; + + aid = le16_to_cpu(elm->aid); + if (aid && aid != hal->aid) + return 1; /* ignore if aid not matched */ + else if (elm_info->tx_comp) + return 1; /* ignore if an element is existing */ + + elm_info->tx_comp = elm; + + return 0; +} + static const struct rtw89_fw_element_handler __fw_element_handlers[] = { [RTW89_FW_ELEMENT_ID_BBMCU0] = {__rtw89_fw_recognize_from_elm, { .fw_type = RTW89_FW_BBMCU0 }, NULL}, @@ -1473,6 +1493,9 @@ static const struct rtw89_fw_element_handler __fw_element_handlers[] = { [RTW89_FW_ELEMENT_ID_DIAG_MAC] = { rtw89_recognize_diag_mac_from_elm, {}, NULL, }, + [RTW89_FW_ELEMENT_ID_TX_COMP] = { + rtw89_build_tx_comp_from_elm, {}, NULL, + }, }; int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev) diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index 146403d285b4..521702f97d50 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -4262,6 +4262,7 @@ enum rtw89_fw_element_id { RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26, RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ = 27, RTW89_FW_ELEMENT_ID_DIAG_MAC = 28, + RTW89_FW_ELEMENT_ID_TX_COMP = 29, RTW89_FW_ELEMENT_ID_NUM, }; -- cgit v1.2.3 From 5fe702e4b2cdb1aca4fc6e639b1bfbefd7905347 Mon Sep 17 00:00:00 2001 From: Zong-Zhe Yang Date: Sat, 17 Jan 2026 12:41:54 +0800 Subject: wifi: rtw89: phy: update TSSI flow for RTL8922D TSSI is to do TX compensation caused by temperature. The RTL8922D defines different H2C command format. Update it accordingly. Signed-off-by: Zong-Zhe Yang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-7-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.c | 7 ++++- drivers/net/wireless/realtek/rtw89/phy.c | 46 +++++++++++++++++++++++--------- 2 files changed, 40 insertions(+), 13 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index 5e405b57121f..5f98ca592a3e 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -7291,6 +7291,7 @@ fail: int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode) { + const struct rtw89_chip_info *chip = rtwdev->chip; struct rtw89_efuse *efuse = &rtwdev->efuse; struct rtw89_hal *hal = &rtwdev->hal; struct rtw89_h2c_rf_tssi *h2c; @@ -7311,11 +7312,15 @@ int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, h2c->ch = chan->channel; h2c->bw = chan->band_width; h2c->band = chan->band_type; - h2c->hwtx_en = true; h2c->cv = hal->cv; h2c->tssi_mode = tssi_mode; h2c->rfe_type = efuse->rfe_type; + if (chip->chip_id == RTL8922A) + h2c->hwtx_en = true; + else + h2c->hwtx_en = false; + rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(rtwdev, phy_idx, chan, h2c); rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(rtwdev, phy_idx, chan, h2c); diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index c9bd3b7c5489..f3ef5673cb6a 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -4566,6 +4566,7 @@ void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, struct rtw89_h2c_rf_tssi *h2c) { + const struct rtw89_chip_info *chip = rtwdev->chip; struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; u8 ch = chan->channel; s8 trim_de; @@ -4589,9 +4590,14 @@ void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, cck_de = tssi_info->tssi_cck[i][gidx]; val = u32_get_bits(cck_de + trim_de, 0xff); - h2c->curr_tssi_cck_de[i] = 0x0; - h2c->curr_tssi_cck_de_20m[i] = val; - h2c->curr_tssi_cck_de_40m[i] = val; + if (chip->chip_id == RTL8922A) { + h2c->curr_tssi_cck_de[i] = 0x0; + h2c->curr_tssi_cck_de_20m[i] = val; + h2c->curr_tssi_cck_de_40m[i] = val; + } else { + h2c->curr_tssi_cck_de[i] = val; + } + h2c->curr_tssi_efuse_cck_de[i] = cck_de; rtw89_debug(rtwdev, RTW89_DBG_TSSI, @@ -4600,12 +4606,17 @@ void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i); val = u32_get_bits(ofdm_de + trim_de, 0xff); - h2c->curr_tssi_ofdm_de[i] = 0x0; - h2c->curr_tssi_ofdm_de_20m[i] = val; - h2c->curr_tssi_ofdm_de_40m[i] = val; - h2c->curr_tssi_ofdm_de_80m[i] = val; - h2c->curr_tssi_ofdm_de_160m[i] = val; - h2c->curr_tssi_ofdm_de_320m[i] = val; + if (chip->chip_id == RTL8922A) { + h2c->curr_tssi_ofdm_de[i] = 0x0; + h2c->curr_tssi_ofdm_de_20m[i] = val; + h2c->curr_tssi_ofdm_de_40m[i] = val; + h2c->curr_tssi_ofdm_de_80m[i] = val; + h2c->curr_tssi_ofdm_de_160m[i] = val; + h2c->curr_tssi_ofdm_de_320m[i] = val; + } else { + h2c->curr_tssi_ofdm_de[i] = val; + } + h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de; rtw89_debug(rtwdev, RTW89_DBG_TSSI, @@ -4620,10 +4631,12 @@ void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, { struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk; struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; + const struct rtw89_chip_info *chip = rtwdev->chip; const s8 *thm_up[RF_PATH_B + 1] = {}; const s8 *thm_down[RF_PATH_B + 1] = {}; u8 subband = chan->subband_type; - s8 thm_ofst[128] = {0}; + s8 thm_ofst[128] = {}; + int multiplier; u8 thermal; u8 path; u8 i, j; @@ -4687,6 +4700,11 @@ void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] tmeter tbl on subband: %u\n", subband); + if (chip->chip_id == RTL8922A) + multiplier = 1; + else + multiplier = -1; + for (path = RF_PATH_A; path <= RF_PATH_B; path++) { thermal = tssi_info->thermal[path]; rtw89_debug(rtwdev, RTW89_DBG_TSSI, @@ -4701,16 +4719,20 @@ void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, h2c->pg_thermal[path] = thermal; i = 0; - for (j = 0; j < 64; j++) + for (j = 0; j < 64; j++) { thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? thm_up[path][i++] : thm_up[path][DELTA_SWINGIDX_SIZE - 1]; + thm_ofst[j] *= multiplier; + } i = 1; - for (j = 127; j >= 64; j--) + for (j = 127; j >= 64; j--) { thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? -thm_down[path][i++] : -thm_down[path][DELTA_SWINGIDX_SIZE - 1]; + thm_ofst[j] *= multiplier; + } for (i = 0; i < 128; i += 4) { h2c->ftable[path][i + 0] = thm_ofst[i + 3]; -- cgit v1.2.3 From 9cc1a84c53d4fe9494ed13b3cdba0e23519342f3 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Sat, 17 Jan 2026 12:41:55 +0800 Subject: wifi: rtw89: mac: clear DTOP disable excluding CID7090 variant for RTL8922D The data TX FIFO operation (DTOP) is a hardware component in TMAC circuit to control TX flow, since CID7090 variant can clear DTOP by default, no need it by driver. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-8-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/mac_be.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/realtek/rtw89/mac_be.c b/drivers/net/wireless/realtek/rtw89/mac_be.c index 028fb63014eb..20a9998e3012 100644 --- a/drivers/net/wireless/realtek/rtw89/mac_be.c +++ b/drivers/net/wireless/realtek/rtw89/mac_be.c @@ -1352,6 +1352,7 @@ static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) { const struct rtw89_chip_info *chip = rtwdev->chip; + struct rtw89_hal *hal = &rtwdev->hal; u32 reg; reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx); @@ -1363,7 +1364,7 @@ static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe); } - if (chip->chip_id == RTL8922D) { + if (chip->chip_id == RTL8922D && hal->cid != RTL8922D_CID7090) { reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_COMMON_PHYINTF_CTRL_0, mac_idx); rtw89_write32_clr(rtwdev, reg, CLEAR_DTOP_DIS); } -- cgit v1.2.3 From 1945c83dc5cef50c46101c0c2abb2da8650fd3b1 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Sat, 17 Jan 2026 12:41:56 +0800 Subject: wifi: rtw89: mac: set force MBA duration to 0 Enable force MBA (Multi-user Block Ack) field to ensure trasnmiting packet of duration field of MBA in multi-user block ack request is 0 as expected. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-9-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/mac_be.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/mac_be.c b/drivers/net/wireless/realtek/rtw89/mac_be.c index 20a9998e3012..3a84cd529148 100644 --- a/drivers/net/wireless/realtek/rtw89/mac_be.c +++ b/drivers/net/wireless/realtek/rtw89/mac_be.c @@ -1328,6 +1328,9 @@ static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SPECIAL_TX_SETTING, mac_idx); rtw89_write32_clr(rtwdev, reg, B_BE_BMC_NAV_PROTECT); + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx); + rtw89_write32_set(rtwdev, reg, B_BE_WMAC_MBA_DUR_FORCE); + return 0; } -- cgit v1.2.3 From 8da7e88682d58a7c2e2c2101e49d3c9c9ac481b0 Mon Sep 17 00:00:00 2001 From: Po-Hao Huang Date: Sat, 17 Jan 2026 12:41:57 +0800 Subject: wifi: rtw89: 8922a: add digital compensation for 2GHz This fixes transmit power too low under 2GHz connection. Previously we missed the settings of 2GHz, add the according calibrated tables. Signed-off-by: Po-Hao Huang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260117044157.2392958-10-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/rtw8922a.c | 57 ++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/rtw8922a.c b/drivers/net/wireless/realtek/rtw89/rtw8922a.c index 0a3c2207dd4b..f41b66b362c4 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8922a.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8922a.c @@ -1768,6 +1768,32 @@ static int rtw8922a_ctrl_rx_path_tmac(struct rtw89_dev *rtwdev, } #define DIGITAL_PWR_COMP_REG_NUM 22 +static const u32 rtw8922a_digital_pwr_comp_2g_s0_val[][DIGITAL_PWR_COMP_REG_NUM] = { + {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320, + 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010000, 0x00000101, + 0x01010101, 0x02020201, 0x02010000, 0x03030202, 0x00000303, + 0x03020101, 0x06060504, 0x01010000, 0x06050403, 0x01000606, + 0x05040202, 0x07070706}, + {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320, + 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010100, 0x00000101, + 0x01000000, 0x01010101, 0x01010000, 0x02020202, 0x00000404, + 0x03020101, 0x04040303, 0x02010000, 0x03030303, 0x00000505, + 0x03030201, 0x05050303}, +}; + +static const u32 rtw8922a_digital_pwr_comp_2g_s1_val[][DIGITAL_PWR_COMP_REG_NUM] = { + {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320, + 0x0D05091D, 0x14D50FA0, 0x01010000, 0x01010101, 0x00000101, + 0x01010100, 0x01010101, 0x01010000, 0x02020202, 0x01000202, + 0x02020101, 0x03030202, 0x02010000, 0x05040403, 0x01000606, + 0x05040302, 0x07070605}, + {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320, + 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010100, 0x00000101, + 0x01010000, 0x02020201, 0x02010100, 0x03030202, 0x01000404, + 0x04030201, 0x05050404, 0x01010100, 0x04030303, 0x01000505, + 0x03030101, 0x05050404}, +}; + static const u32 rtw8922a_digital_pwr_comp_val[][DIGITAL_PWR_COMP_REG_NUM] = { {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A, 0x0BB80708, 0x17701194, 0x02020100, 0x03030303, 0x01000303, @@ -1782,7 +1808,7 @@ static const u32 rtw8922a_digital_pwr_comp_val[][DIGITAL_PWR_COMP_REG_NUM] = { }; static void rtw8922a_set_digital_pwr_comp(struct rtw89_dev *rtwdev, - bool enable, u8 nss, + u8 band, u8 nss, enum rtw89_rf_path path) { static const u32 ltpc_t0[2] = {R_BE_LTPC_T0_PATH0, R_BE_LTPC_T0_PATH1}; @@ -1790,14 +1816,25 @@ static void rtw8922a_set_digital_pwr_comp(struct rtw89_dev *rtwdev, u32 addr, val; u32 i; - if (nss == 1) - digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0]; - else - digital_pwr_comp = rtw8922a_digital_pwr_comp_val[1]; + if (nss == 1) { + if (band == RTW89_BAND_2G) + digital_pwr_comp = path == RF_PATH_A ? + rtw8922a_digital_pwr_comp_2g_s0_val[0] : + rtw8922a_digital_pwr_comp_2g_s1_val[0]; + else + digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0]; + } else { + if (band == RTW89_BAND_2G) + digital_pwr_comp = path == RF_PATH_A ? + rtw8922a_digital_pwr_comp_2g_s0_val[1] : + rtw8922a_digital_pwr_comp_2g_s1_val[1]; + else + digital_pwr_comp = rtw8922a_digital_pwr_comp_val[1]; + } addr = ltpc_t0[path]; for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) { - val = enable ? digital_pwr_comp[i] : 0; + val = digital_pwr_comp[i]; rtw89_phy_write32(rtwdev, addr, val); } } @@ -1806,7 +1843,7 @@ static void rtw8922a_digital_pwr_comp(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) { const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); - bool enable = chan->band_type != RTW89_BAND_2G; + u8 band = chan->band_type; u8 path; if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) { @@ -1814,10 +1851,10 @@ static void rtw8922a_digital_pwr_comp(struct rtw89_dev *rtwdev, path = RF_PATH_A; else path = RF_PATH_B; - rtw8922a_set_digital_pwr_comp(rtwdev, enable, 1, path); + rtw8922a_set_digital_pwr_comp(rtwdev, band, 1, path); } else { - rtw8922a_set_digital_pwr_comp(rtwdev, enable, 2, RF_PATH_A); - rtw8922a_set_digital_pwr_comp(rtwdev, enable, 2, RF_PATH_B); + rtw8922a_set_digital_pwr_comp(rtwdev, band, 2, RF_PATH_A); + rtw8922a_set_digital_pwr_comp(rtwdev, band, 2, RF_PATH_B); } } -- cgit v1.2.3 From ebd8a1d736eed8818f3adb2f141bf9cadbd4ee9e Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 23 Jan 2026 09:39:47 +0800 Subject: wifi: rtw89: rfk: add firmware command to do TX IQK TX IQK is a RF calibration, which driver call this H2C command to trigger the calibration. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-2-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.c | 43 ++++++++++++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/fw.h | 15 +++++++++++ drivers/net/wireless/realtek/rtw89/phy.c | 17 +++++++++++++ drivers/net/wireless/realtek/rtw89/phy.h | 4 +++ 4 files changed, 79 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index 5f98ca592a3e..fed74ad6b4bd 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -7614,6 +7614,49 @@ fail: return ret; } +int rtw89_fw_h2c_rf_txiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, + const struct rtw89_chan *chan) +{ + struct rtw89_h2c_rf_txiqk *h2c; + u32 len = sizeof(*h2c); + struct sk_buff *skb; + int ret; + + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); + if (!skb) { + rtw89_err(rtwdev, "failed to alloc skb for h2c RF TXIQK\n"); + return -ENOMEM; + } + skb_put(skb, len); + h2c = (struct rtw89_h2c_rf_txiqk *)skb->data; + + h2c->len = len; + h2c->phy = phy_idx; + h2c->txiqk_enable = true; + h2c->is_wb_txiqk = true; + h2c->kpath = RF_AB; + h2c->cur_band = chan->band_type; + h2c->cur_bw = chan->band_width; + h2c->cur_ch = chan->channel; + h2c->txiqk_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK); + + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, + H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK, + H2C_FUNC_RFK_TXIQK_OFFOAD, 0, 0, len); + + ret = rtw89_h2c_tx(rtwdev, skb, false); + if (ret) { + rtw89_err(rtwdev, "failed to send h2c\n"); + goto fail; + } + + return 0; +fail: + dev_kfree_skb_any(skb); + + return ret; +} + int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, bool rack, bool dack) diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index 521702f97d50..31402667e155 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -4718,6 +4718,7 @@ enum rtw89_rfk_offload_h2c_func { H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6, H2C_FUNC_RFK_PRE_NOTIFY = 0x8, H2C_FUNC_RFK_TAS_OFFLOAD = 0x9, + H2C_FUNC_RFK_TXIQK_OFFOAD = 0xc, }; struct rtw89_fw_h2c_rf_get_mccch { @@ -4935,6 +4936,18 @@ struct rtw89_h2c_rf_rxdck { u8 is_chl_k; } __packed; +struct rtw89_h2c_rf_txiqk { + u8 len; + u8 phy; + u8 txiqk_enable; + u8 is_wb_txiqk; + u8 kpath; + u8 cur_band; + u8 cur_bw; + u8 cur_ch; + u8 txiqk_dbg_en; +} __packed; + enum rtw89_rf_log_type { RTW89_RF_RUN_LOG = 0, RTW89_RF_RPT_LOG = 1, @@ -5235,6 +5248,8 @@ int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, bool is_chl_k); int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable); +int rtw89_fw_h2c_rf_txiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, + const struct rtw89_chan *chan); int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, bool rack, bool dack); diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index f3ef5673cb6a..fd2e9a472518 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -4119,6 +4119,23 @@ int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, } EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait); +int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev, + enum rtw89_phy_idx phy_idx, + const struct rtw89_chan *chan, + unsigned int ms) +{ + int ret; + + rtw89_phy_rfk_report_prep(rtwdev); + + ret = rtw89_fw_h2c_rf_txiqk(rtwdev, phy_idx, chan); + if (ret) + return ret; + + return rtw89_phy_rfk_report_wait(rtwdev, "TX_IQK", ms); +} +EXPORT_SYMBOL(rtw89_phy_rfk_txiqk_and_wait); + static u32 phy_tssi_get_cck_group(u8 ch) { switch (ch) { diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 0c5224780e84..9a15dbf1c318 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -1031,6 +1031,10 @@ int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, bool is_chl_k, unsigned int ms); +int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev, + enum rtw89_phy_idx phy_idx, + const struct rtw89_chan *chan, + unsigned int ms); void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, const struct rtw89_chan *chan, -- cgit v1.2.3 From 9df3575ed2bb5474df2f9bb5735a9946c2d84579 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 23 Jan 2026 09:39:48 +0800 Subject: wifi: rtw89: rfk: add to print debug log of TX IQK Add report format for TX IQK, which do calibration in firmware and send a C2H event as debug purpose. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-3-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.h | 20 ++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/phy.c | 15 ++++++++++++++- drivers/net/wireless/realtek/rtw89/phy.h | 1 + 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index 31402667e155..c3ad473a06f2 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -5069,6 +5069,26 @@ struct rtw89_c2h_rf_txgapk_rpt_log { u8 rsv1; } __packed; +struct rtw89_c2h_rf_txiqk_rpt_log { + u8 fw_txiqk_ver; + u8 rsvd; + u8 iqk_band[2]; + u8 iqk_ch[2]; + u8 iqk_bw[2]; + bool tx_iqk_fail[2]; + bool is_iqk_init; + bool txiqk_en; + bool lok_en; + bool lok_fail[2]; + u8 rsvd2; + __le32 iqk_times; + bool txiqk_nctldone[2]; + u8 rsvd3[2]; + __le32 txgain[2][6]; + __le32 tx_iqc[2][6]; + __le32 tx_xym[2][6][14]; +} __packed; + struct rtw89_c2h_rfk_report { struct rtw89_c2h_hdr hdr; u8 state; /* enum rtw89_rfk_report_state */ diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index fd2e9a472518..215864d1e1c7 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -3456,6 +3456,7 @@ static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, { struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; + struct rtw89_c2h_rf_txiqk_rpt_log *txiqk; struct rtw89_c2h_rf_dack_rpt_log *dack; struct rtw89_c2h_rf_tssi_rpt_log *tssi; struct rtw89_c2h_rf_dpk_rpt_log *dpk; @@ -3706,7 +3707,10 @@ static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, goto out; rtw89_phy_c2h_rfk_tas_pwr(rtwdev, content); - + return; + case RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK: + if (len != sizeof(*txiqk)) + goto out; return; default: break; @@ -3843,6 +3847,13 @@ rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR, "TAS"); } +static void +rtw89_phy_c2h_rfk_log_txiqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) +{ + rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, + RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK, "TXIQK"); +} + static void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) = { @@ -3853,6 +3864,7 @@ void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, [RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr, + [RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK] = rtw89_phy_c2h_rfk_log_txiqk, }; static @@ -3941,6 +3953,7 @@ bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: + case RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK: return true; default: return false; diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 9a15dbf1c318..89e3bc588494 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -150,6 +150,7 @@ enum rtw89_phy_c2h_rfk_log_func { RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4, RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR = 9, + RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK = 0xc, RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, }; -- cgit v1.2.3 From 17b75fbf9c711546a466098d4951d3eaf5f51e09 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 23 Jan 2026 09:39:49 +0800 Subject: wifi: rtw89: rfk: add firmware command to do CIM3K CIM is short for counter intermodulation products 3rd-order. Due to non-linearity in transmit path, need a calibration to yield performance for RF system. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-4-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.c | 41 ++++++++++++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/fw.h | 15 ++++++++++++ drivers/net/wireless/realtek/rtw89/phy.c | 17 +++++++++++++ drivers/net/wireless/realtek/rtw89/phy.h | 4 ++++ 4 files changed, 77 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index fed74ad6b4bd..4035ec8defa8 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -7657,6 +7657,47 @@ fail: return ret; } +int rtw89_fw_h2c_rf_cim3k(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, + const struct rtw89_chan *chan) +{ + struct rtw89_h2c_rf_cim3k *h2c; + u32 len = sizeof(*h2c); + struct sk_buff *skb; + int ret; + + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); + if (!skb) { + rtw89_err(rtwdev, "failed to alloc skb for h2c RF CIM3K\n"); + return -ENOMEM; + } + skb_put(skb, len); + h2c = (struct rtw89_h2c_rf_cim3k *)skb->data; + + h2c->len = len; + h2c->phy = phy_idx; + h2c->kpath = RF_AB; + h2c->cur_band = chan->band_type; + h2c->cur_bw = chan->band_width; + h2c->cur_ch = chan->channel; + h2c->cim3k_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK); + + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, + H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK, + H2C_FUNC_RFK_CIM3K_OFFOAD, 0, 0, len); + + ret = rtw89_h2c_tx(rtwdev, skb, false); + if (ret) { + rtw89_err(rtwdev, "failed to send h2c\n"); + goto fail; + } + + return 0; +fail: + dev_kfree_skb_any(skb); + + return ret; +} + int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, bool rack, bool dack) diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index c3ad473a06f2..2f04138148b7 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -4719,6 +4719,7 @@ enum rtw89_rfk_offload_h2c_func { H2C_FUNC_RFK_PRE_NOTIFY = 0x8, H2C_FUNC_RFK_TAS_OFFLOAD = 0x9, H2C_FUNC_RFK_TXIQK_OFFOAD = 0xc, + H2C_FUNC_RFK_CIM3K_OFFOAD = 0xe, }; struct rtw89_fw_h2c_rf_get_mccch { @@ -4948,6 +4949,18 @@ struct rtw89_h2c_rf_txiqk { u8 txiqk_dbg_en; } __packed; +struct rtw89_h2c_rf_cim3k { + u8 len; + u8 phy; + u8 su_cim3k_enable[2]; + u8 ru_cim3k_enable[2]; + u8 kpath; + u8 cur_band; + u8 cur_bw; + u8 cur_ch; + u8 cim3k_dbg_en; +} __packed; + enum rtw89_rf_log_type { RTW89_RF_RUN_LOG = 0, RTW89_RF_RPT_LOG = 1, @@ -5270,6 +5283,8 @@ int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable); int rtw89_fw_h2c_rf_txiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan); +int rtw89_fw_h2c_rf_cim3k(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, + const struct rtw89_chan *chan); int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, bool rack, bool dack); diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 215864d1e1c7..5f6854b7550d 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -4149,6 +4149,23 @@ int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev, } EXPORT_SYMBOL(rtw89_phy_rfk_txiqk_and_wait); +int rtw89_phy_rfk_cim3k_and_wait(struct rtw89_dev *rtwdev, + enum rtw89_phy_idx phy_idx, + const struct rtw89_chan *chan, + unsigned int ms) +{ + int ret; + + rtw89_phy_rfk_report_prep(rtwdev); + + ret = rtw89_fw_h2c_rf_cim3k(rtwdev, phy_idx, chan); + if (ret) + return ret; + + return rtw89_phy_rfk_report_wait(rtwdev, "CIM3k", ms); +} +EXPORT_SYMBOL(rtw89_phy_rfk_cim3k_and_wait); + static u32 phy_tssi_get_cck_group(u8 ch) { switch (ch) { diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 89e3bc588494..5e04bdcef4e9 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -1036,6 +1036,10 @@ int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, unsigned int ms); +int rtw89_phy_rfk_cim3k_and_wait(struct rtw89_dev *rtwdev, + enum rtw89_phy_idx phy_idx, + const struct rtw89_chan *chan, + unsigned int ms); void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, const struct rtw89_chan *chan, -- cgit v1.2.3 From 571f945fb91bb678827e76e6bd91595eb6fab841 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 23 Jan 2026 09:39:50 +0800 Subject: wifi: rtw89: rfk: add to print debug log of CIM3K Add calibration report of CIM3K, which does calibration in firmware and send a C2H event as debug purpose. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-5-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.h | 27 +++++++++++++++++++++++++++ drivers/net/wireless/realtek/rtw89/phy.c | 13 +++++++++++++ drivers/net/wireless/realtek/rtw89/phy.h | 1 + 3 files changed, 41 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index 2f04138148b7..4fa982cbac49 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -5102,6 +5102,33 @@ struct rtw89_c2h_rf_txiqk_rpt_log { __le32 tx_xym[2][6][14]; } __packed; +struct rtw89_c2h_rf_cim3k_rpt_log { + u8 cim3k_band[2]; + u8 cim3k_ch[2]; + u8 cim3k_bw[2]; + u8 su_path_ok[2]; + u8 ru_path_ok[2]; + u8 txagc_cim3k[2]; + u8 ther_cim3k[2]; + u8 cim3k_gs[2]; + __le16 cim3k_pwsf[2]; + bool cim3k_nctldone[2]; + u8 rsvd[2]; + __le32 cim3k_rxiqc[2]; + __le32 cim3k_su_coef[2][3]; + __le16 dc_i[2]; + __le16 dc_q[2]; + u8 corr_val[2]; + u8 corr_idx[2]; + u8 rxbb_ov[2]; + u8 cim3k_txiqc[2]; + u8 kidx[2]; + u8 fw_cim3k_ver; + bool su_cim3k_en[2]; + bool ru_cim3k_en[2]; + u8 rsvd1; +} __packed; + struct rtw89_c2h_rfk_report { struct rtw89_c2h_hdr hdr; u8 state; /* enum rtw89_rfk_report_state */ diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 5f6854b7550d..11f45e30d76d 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -3457,6 +3457,7 @@ static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; struct rtw89_c2h_rf_txiqk_rpt_log *txiqk; + struct rtw89_c2h_rf_cim3k_rpt_log *cim3k; struct rtw89_c2h_rf_dack_rpt_log *dack; struct rtw89_c2h_rf_tssi_rpt_log *tssi; struct rtw89_c2h_rf_dpk_rpt_log *dpk; @@ -3712,6 +3713,10 @@ static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, if (len != sizeof(*txiqk)) goto out; return; + case RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K: + if (len != sizeof(*cim3k)) + goto out; + return; default: break; } @@ -3854,6 +3859,13 @@ rtw89_phy_c2h_rfk_log_txiqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 l RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK, "TXIQK"); } +static void +rtw89_phy_c2h_rfk_log_cim3k(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) +{ + rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, + RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K, "CIM3K"); +} + static void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) = { @@ -3865,6 +3877,7 @@ void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, [RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr, [RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK] = rtw89_phy_c2h_rfk_log_txiqk, + [RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K] = rtw89_phy_c2h_rfk_log_cim3k, }; static diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index 5e04bdcef4e9..a587f83b8d67 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -151,6 +151,7 @@ enum rtw89_phy_c2h_rfk_log_func { RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR = 9, RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK = 0xc, + RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K = 0xe, RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, }; -- cgit v1.2.3 From 21344e7413778734988cfac9dd70a690bcbafdb9 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 23 Jan 2026 09:39:51 +0800 Subject: wifi: rtw89: rfk: update RFK report format of IQK, DACK and TXGAPK The report formats of IQK, DACK and TXGAPK are changed. Update them accordingly. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-6-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.h | 24 ++++++++++++++++-------- drivers/net/wireless/realtek/rtw89/phy.c | 30 ++++++++++++++++++++++++------ 2 files changed, 40 insertions(+), 14 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index 4fa982cbac49..e4dbcd899ddb 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -5005,12 +5005,16 @@ struct rtw89_c2h_rf_iqk_rpt_log { u8 rsvd; __le32 reload_cnt; __le32 iqk_fail_cnt; + __le32 rf_0x18[2]; __le32 lok_idac[2]; __le32 lok_vbuf[2]; - __le32 rftxgain[2][4]; - __le32 rfrxgain[2][4]; - __le32 tx_xym[2][4]; - __le32 rx_xym[2][4]; + __le32 rftxgain[2][6]; + __le32 rfrxgain[2][6]; + __le32 tx_xym[2][6]; + __le32 rx_xym[2][6]; + __le32 rx_wb_xym[2][32]; + bool is_radar; + u8 rsvd1[3]; } __packed; struct rtw89_c2h_rf_dpk_rpt_log { @@ -5053,6 +5057,7 @@ struct rtw89_c2h_rf_dack_rpt_log { u8 dack_fail; u8 wbdck_d[2]; u8 rck_d; + u8 adgaink_ex_d; } __packed; struct rtw89_c2h_rf_rxdck_rpt_log { @@ -5079,12 +5084,14 @@ struct rtw89_c2h_rf_txgapk_rpt_log { u8 is_txgapk_ok; u8 chk_id; u8 ver; - u8 rsv1; + u8 d_bnd_ok; + __le32 stage[2]; + __le16 failcode[2]; + u8 rsvd[4]; } __packed; struct rtw89_c2h_rf_txiqk_rpt_log { u8 fw_txiqk_ver; - u8 rsvd; u8 iqk_band[2]; u8 iqk_ch[2]; u8 iqk_bw[2]; @@ -5093,13 +5100,14 @@ struct rtw89_c2h_rf_txiqk_rpt_log { bool txiqk_en; bool lok_en; bool lok_fail[2]; - u8 rsvd2; + u8 rsvd[2]; __le32 iqk_times; bool txiqk_nctldone[2]; - u8 rsvd3[2]; + u8 rsvd2[2]; __le32 txgain[2][6]; __le32 tx_iqc[2][6]; __le32 tx_xym[2][6][14]; + __le32 kidx[2]; } __packed; struct rtw89_c2h_rf_cim3k_rpt_log { diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 11f45e30d76d..41a8ce3aaffc 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -3512,6 +3512,8 @@ static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, i, iqk->iqk_ch[i]); rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n", i, iqk->iqk_bw[i]); + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->rf_0x18[%d] = %x\n", + i, le32_to_cpu(iqk->rf_0x18[i])); rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n", i, le32_to_cpu(iqk->lok_idac[i])); rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n", @@ -3520,22 +3522,30 @@ static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, i, iqk->iqk_tx_fail[i]); rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n", i, iqk->iqk_rx_fail[i]); - for (j = 0; j < 4; j++) + for (j = 0; j < 6; j++) rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->rftxgain[%d][%d] = %x\n", i, j, le32_to_cpu(iqk->rftxgain[i][j])); - for (j = 0; j < 4; j++) + for (j = 0; j < 6; j++) rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->tx_xym[%d][%d] = %x\n", i, j, le32_to_cpu(iqk->tx_xym[i][j])); - for (j = 0; j < 4; j++) + for (j = 0; j < 6; j++) rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->rfrxgain[%d][%d] = %x\n", i, j, le32_to_cpu(iqk->rfrxgain[i][j])); - for (j = 0; j < 4; j++) + for (j = 0; j < 6; j++) rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->rx_xym[%d][%d] = %x\n", i, j, le32_to_cpu(iqk->rx_xym[i][j])); + + if (!iqk->iqk_xym_en) + continue; + + for (j = 0; j < 32; j++) + rtw89_debug(rtwdev, RTW89_DBG_RFK, + "[IQK] iqk->rx_wb_xym[%d][%d] = %x\n", + i, j, iqk->rx_wb_xym[i][j]); } return; case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: @@ -3691,8 +3701,16 @@ static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, le32_to_cpu(txgapk->chk_cnt)); rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n", txgapk->ver); - rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n", - txgapk->rsv1); + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt d_bnd_ok = %d\n", + txgapk->d_bnd_ok); + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt stage[0] = 0x%x\n", + le32_to_cpu(txgapk->stage[0])); + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt stage[1] = 0x%x\n", + le32_to_cpu(txgapk->stage[1])); + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]failcode[0] = 0x%x\n", + le16_to_cpu(txgapk->failcode[0])); + rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]failcode[1] = 0x%x\n", + le16_to_cpu(txgapk->failcode[1])); rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n", (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]); -- cgit v1.2.3 From c938cb4862546ee1669b3af1318570744272ffd4 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 23 Jan 2026 09:39:52 +0800 Subject: wifi: rtw89: fw: correct content of DACK H2C command The fields of command should be u8 instead of __le32. However, current firmware doesn't really use the data for now, so this mistake doesn't impact performance. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-7-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.c | 6 +++--- drivers/net/wireless/realtek/rtw89/fw.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index 4035ec8defa8..8a33a63619d5 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -7503,9 +7503,9 @@ int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, skb_put(skb, len); h2c = (struct rtw89_h2c_rf_dack *)skb->data; - h2c->len = cpu_to_le32(len); - h2c->phy = cpu_to_le32(phy_idx); - h2c->type = cpu_to_le32(0); + h2c->len = len; + h2c->phy = phy_idx; + h2c->type = 0; rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK, diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index e4dbcd899ddb..da802482c47d 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -4912,9 +4912,9 @@ struct rtw89_h2c_rf_txgapk { } __packed; struct rtw89_h2c_rf_dack { - __le32 len; - __le32 phy; - __le32 type; + u8 len; + u8 phy; + u8 type; } __packed; struct rtw89_h2c_rf_rxdck_v0 { -- cgit v1.2.3 From 69ed25f25faa46c683c194996e556e4ab1bca6da Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 23 Jan 2026 09:39:53 +0800 Subject: wifi: rtw89: phy: add PHY C2H event dummy handler for func 1-7 and 2-10 The two functions aren't implemented and hard necessary by driver. Implement dummy handler to avoid messages: rtw89_8922de 0000:03:00.0: PHY c2h class 1 func 7 not support rtw89_8922de 0000:03:00.0: PHY c2h class 2 func 10 not support Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-8-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.c | 11 +++++++++++ drivers/net/wireless/realtek/rtw89/fw.h | 1 + drivers/net/wireless/realtek/rtw89/phy.c | 4 +++- drivers/net/wireless/realtek/rtw89/phy.h | 5 ++++- 4 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index 8a33a63619d5..4c50c0166d4f 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -7783,6 +7783,17 @@ void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev) __rtw89_fw_free_all_early_h2c(rtwdev); } +void rtw89_fw_c2h_dummy_handler(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) +{ + struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(c2h); + u8 category = attr->category; + u8 class = attr->class; + u8 func = attr->func; + + rtw89_debug(rtwdev, RTW89_DBG_FW, + "C2H cate=%u cls=%u func=%u is dummy\n", category, class, func); +} + static void rtw89_fw_c2h_parse_attr(struct sk_buff *c2h) { const struct rtw89_c2h_hdr *hdr = (const struct rtw89_c2h_hdr *)c2h->data; diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h index da802482c47d..d45b6ea6ea1b 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.h +++ b/drivers/net/wireless/realtek/rtw89/fw.h @@ -5249,6 +5249,7 @@ int rtw89_fw_h2c_dctl_sec_cam_v3(struct rtw89_dev *rtwdev, void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); void rtw89_fw_c2h_work(struct wiphy *wiphy, struct wiphy_work *work); void rtw89_fw_c2h_purge_obsoleted_scan_events(struct rtw89_dev *rtwdev); +void rtw89_fw_c2h_dummy_handler(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len); int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, struct rtw89_sta_link *rtwsta_link, diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c index 41a8ce3aaffc..6c6d5f1da867 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.c +++ b/drivers/net/wireless/realtek/rtw89/phy.c @@ -3332,6 +3332,7 @@ void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, + [RTW89_PHY_C2H_FUNC_ACCELERATE_EN] = rtw89_fw_c2h_dummy_handler, }; static void @@ -3419,6 +3420,7 @@ void (* const rtw89_phy_c2h_dm_handler[])(struct rtw89_dev *rtwdev, [RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY] = rtw89_phy_c2h_lowrt_rty, [RTW89_PHY_C2H_DM_FUNC_MCC_DIG] = NULL, [RTW89_PHY_C2H_DM_FUNC_LPS] = rtw89_phy_c2h_lps_rpt, + [RTW89_PHY_C2H_DM_FUNC_ENV_MNTR] = rtw89_fw_c2h_dummy_handler, [RTW89_PHY_C2H_DM_FUNC_FW_SCAN] = rtw89_phy_c2h_fw_scan_rpt, }; @@ -4009,7 +4011,7 @@ void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, switch (class) { case RTW89_PHY_C2H_CLASS_RA: - if (func < RTW89_PHY_C2H_FUNC_RA_MAX) + if (func < ARRAY_SIZE(rtw89_phy_c2h_ra_handler)) handler = rtw89_phy_c2h_ra_handler[func]; break; case RTW89_PHY_C2H_RFK_LOG: diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h index a587f83b8d67..ab263738d212 100644 --- a/drivers/net/wireless/realtek/rtw89/phy.h +++ b/drivers/net/wireless/realtek/rtw89/phy.h @@ -139,7 +139,9 @@ enum rtw89_phy_c2h_ra_func { RTW89_PHY_C2H_FUNC_STS_RPT, RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, RTW89_PHY_C2H_FUNC_TXSTS, - RTW89_PHY_C2H_FUNC_RA_MAX, + RTW89_PHY_C2H_FUNC_ACCELERATE_EN = 0x7, + + RTW89_PHY_C2H_FUNC_RA_NUM, }; enum rtw89_phy_c2h_rfk_log_func { @@ -168,6 +170,7 @@ enum rtw89_phy_c2h_dm_func { RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, RTW89_PHY_C2H_DM_FUNC_MCC_DIG, RTW89_PHY_C2H_DM_FUNC_LPS = 0x9, + RTW89_PHY_C2H_DM_FUNC_ENV_MNTR = 0xa, RTW89_PHY_C2H_DM_FUNC_FW_SCAN = 0xc, RTW89_PHY_C2H_DM_FUNC_NUM, }; -- cgit v1.2.3 From 3b85a8948f525713e6206a28884e1f4246dbf63f Mon Sep 17 00:00:00 2001 From: Zong-Zhe Yang Date: Fri, 23 Jan 2026 09:39:54 +0800 Subject: wifi: rtw89: 8922a: configure FW version for SIM_SER_L0L1_BY_HALT_H2C After FW version 0.35.97.0, 8922A supports SIM_SER_L0L1_BY_HALT_H2C FW feature. It allows to simulate FW L0/L1 crash under PS mode. Signed-off-by: Zong-Zhe Yang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-9-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/fw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index 4c50c0166d4f..9e88fd6d735a 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -922,6 +922,7 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = { __DIS_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, WITH_RFK_PRE_NOTIFY, G), __CFG_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, RFK_PRE_NOTIFY_MCC_V1), __CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0), + __CFG_FW_FEAT(RTL8922A, ge, 0, 35, 97, 0, SIM_SER_L0L1_BY_HALT_H2C), }; static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw, -- cgit v1.2.3 From 986aa89b7613266a279748c7f632e3c2d3b818f6 Mon Sep 17 00:00:00 2001 From: Zong-Zhe Yang Date: Fri, 23 Jan 2026 09:39:55 +0800 Subject: wifi: rtw89: get designated link to replace link instance 0 Clean up some places where still to get link instance 0 directly. Since now MLSR switch is supported, it's not guaranteed to always run on link instance 0. So, prefer to get designated link in most cases. For now, the only exception is MCC (multi-channel concurrency) case. How to fill content of its H2C command depends on how to choose link instance, so cannot simply change it as above. Will handle MCC case separately afterwards. Signed-off-by: Zong-Zhe Yang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-10-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/chan.c | 8 ++++---- drivers/net/wireless/realtek/rtw89/fw.c | 7 ++----- drivers/net/wireless/realtek/rtw89/mac80211.c | 4 ++-- 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/chan.c b/drivers/net/wireless/realtek/rtw89/chan.c index c0af61992226..9b2f6f0a00fd 100644 --- a/drivers/net/wireless/realtek/rtw89/chan.c +++ b/drivers/net/wireless/realtek/rtw89/chan.c @@ -372,8 +372,8 @@ static void rtw89_normalize_link_chanctx(struct rtw89_dev *rtwdev, if (unlikely(!rtwvif_link->chanctx_assigned)) return; - cur = rtw89_vif_get_link_inst(rtwvif, 0); - if (!cur || !cur->chanctx_assigned) + cur = rtw89_get_designated_link(rtwvif); + if (unlikely(!cur) || !cur->chanctx_assigned) return; if (cur == rtwvif_link) @@ -522,8 +522,8 @@ static void rtw89_entity_recalc_mgnt_roles(struct rtw89_dev *rtwdev) } /* To be consistent with legacy behavior, expect the first active role - * which uses RTW89_CHANCTX_0 to put at position 0, and make its first - * link instance take RTW89_CHANCTX_0. (normalizing) + * which uses RTW89_CHANCTX_0 to put at position 0 and its designated + * link take RTW89_CHANCTX_0. (normalizing) */ list_for_each_entry(role, &mgnt->active_list, mgnt_entry) { for (i = 0; i < role->links_inst_valid_num; i++) { diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c index 9e88fd6d735a..f84726f04669 100644 --- a/drivers/net/wireless/realtek/rtw89/fw.c +++ b/drivers/net/wireless/realtek/rtw89/fw.c @@ -9027,12 +9027,9 @@ static void rtw89_hw_scan_set_extra_op_info(struct rtw89_dev *rtwdev, if (tmp == scan_rtwvif) continue; - tmp_link = rtw89_vif_get_link_inst(tmp, 0); - if (unlikely(!tmp_link)) { - rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, - "hw scan: no HW-0 link for extra op\n"); + tmp_link = rtw89_get_designated_link(tmp); + if (unlikely(!tmp_link)) continue; - } tmp_chan = rtw89_chan_get(rtwdev, tmp_link->chanctx_idx); *ext = (struct rtw89_hw_scan_extra_op){ diff --git a/drivers/net/wireless/realtek/rtw89/mac80211.c b/drivers/net/wireless/realtek/rtw89/mac80211.c index ba71709a9bc9..315bb0d0759f 100644 --- a/drivers/net/wireless/realtek/rtw89/mac80211.c +++ b/drivers/net/wireless/realtek/rtw89/mac80211.c @@ -1438,9 +1438,9 @@ static void rtw89_ops_channel_switch_beacon(struct ieee80211_hw *hw, BUILD_BUG_ON(RTW89_MLD_NON_STA_LINK_NUM != 1); - rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0); + rtwvif_link = rtw89_get_designated_link(rtwvif); if (unlikely(!rtwvif_link)) { - rtw89_err(rtwdev, "chsw bcn: find no link on HW-0\n"); + rtw89_err(rtwdev, "chsw bcn: find no designated link\n"); return; } -- cgit v1.2.3 From 5f93d611b33a05bd03d6843c8efe8cb6a1992620 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 23 Jan 2026 09:39:56 +0800 Subject: wifi: rtw89: pci: validate release report content before using for RTL8922DE The commit 957eda596c76 ("wifi: rtw89: pci: validate sequence number of TX release report") does validation on existing chips, which somehow a release report of SKB becomes malformed. As no clear cause found, add rules ahead for RTL8922DE to avoid crash if it happens. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-11-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/pci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c index 093960d7279f..b8135cf15d13 100644 --- a/drivers/net/wireless/realtek/rtw89/pci.c +++ b/drivers/net/wireless/realtek/rtw89/pci.c @@ -604,8 +604,10 @@ static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, void *rpp) info->parse_rpp(rtwdev, rpp, &rpp_info); - if (unlikely(rpp_info.txch == RTW89_TXCH_CH12)) { - rtw89_warn(rtwdev, "should no fwcmd release report\n"); + if (unlikely(rpp_info.txch >= RTW89_TXCH_NUM || + info->tx_dma_ch_mask & BIT(rpp_info.txch))) { + rtw89_warn(rtwdev, "should no release report on txch %d\n", + rpp_info.txch); return; } -- cgit v1.2.3 From 599b1b9fb967360bda5f8fa2c926d2519810fdfd Mon Sep 17 00:00:00 2001 From: Zong-Zhe Yang Date: Fri, 23 Jan 2026 09:39:57 +0800 Subject: wifi: rtw89: regd: update regulatory map to R73-R54 Sync Realtek Channel Plan R73 and Realtek Regulatory R54. Configure 6 GHz field of Realtek regd for the following countries. PY NA BD ID VN TN GL GP YT EH Signed-off-by: Zong-Zhe Yang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260123013957.16418-12-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/regd.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/regd.c b/drivers/net/wireless/realtek/rtw89/regd.c index c3425ed44732..28466cb35ea2 100644 --- a/drivers/net/wireless/realtek/rtw89/regd.c +++ b/drivers/net/wireless/realtek/rtw89/regd.c @@ -38,7 +38,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { COUNTRY_REGD("MX", RTW89_MEXICO, RTW89_MEXICO, RTW89_FCC, 0x0), COUNTRY_REGD("NI", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), COUNTRY_REGD("PA", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), - COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), + COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), COUNTRY_REGD("PE", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), COUNTRY_REGD("US", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x1), COUNTRY_REGD("UY", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), @@ -95,7 +95,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { COUNTRY_REGD("MK", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("MA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("MZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), - COUNTRY_REGD("NA", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("NA", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("NG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("OM", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("QA", RTW89_QATAR, RTW89_QATAR, RTW89_QATAR, 0x0), @@ -111,12 +111,12 @@ static const struct rtw89_regd rtw89_regd_map[] = { COUNTRY_REGD("AE", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("YE", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("ZW", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), - COUNTRY_REGD("BD", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("BD", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("KH", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("CN", RTW89_CN, RTW89_CN, RTW89_CN, 0x0), COUNTRY_REGD("HK", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("IN", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), - COUNTRY_REGD("ID", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("ID", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("KR", RTW89_KCC, RTW89_KCC, RTW89_KCC, 0x1), COUNTRY_REGD("MY", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("PK", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), @@ -125,7 +125,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { COUNTRY_REGD("LK", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("TW", RTW89_FCC, RTW89_FCC, RTW89_ETSI, 0x0), COUNTRY_REGD("TH", RTW89_THAILAND, RTW89_THAILAND, RTW89_THAILAND, 0x0), - COUNTRY_REGD("VN", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("VN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("AU", RTW89_ACMA, RTW89_ACMA, RTW89_ACMA, 0x0), COUNTRY_REGD("NZ", RTW89_ACMA, RTW89_ACMA, RTW89_ACMA, 0x0), COUNTRY_REGD("PG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), @@ -134,7 +134,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { COUNTRY_REGD("JM", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), COUNTRY_REGD("AN", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), COUNTRY_REGD("TT", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), - COUNTRY_REGD("TN", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("TN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("AF", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("DZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("AS", RTW89_FCC, RTW89_FCC, RTW89_NA, 0x0), @@ -187,9 +187,9 @@ static const struct rtw89_regd rtw89_regd_map[] = { COUNTRY_REGD("GM", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("GE", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("GI", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), - COUNTRY_REGD("GL", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("GL", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), - COUNTRY_REGD("GP", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("GP", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("GU", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), COUNTRY_REGD("GG", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("GN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), @@ -214,7 +214,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { COUNTRY_REGD("MQ", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("MR", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("MU", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), - COUNTRY_REGD("YT", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("YT", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("FM", RTW89_FCC, RTW89_FCC, RTW89_FCC, 0x0), COUNTRY_REGD("MD", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("MN", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), @@ -260,7 +260,7 @@ static const struct rtw89_regd rtw89_regd_map[] = { COUNTRY_REGD("UZ", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("VU", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("WF", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), - COUNTRY_REGD("EH", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), + COUNTRY_REGD("EH", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0), COUNTRY_REGD("ZM", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("CU", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), COUNTRY_REGD("IR", RTW89_ETSI, RTW89_ETSI, RTW89_NA, 0x0), -- cgit v1.2.3 From 9e1e967b4dbeb316bdffa3a6ccf14b1d6cc977ca Mon Sep 17 00:00:00 2001 From: Zong-Zhe Yang Date: Tue, 27 Jan 2026 16:50:31 +0800 Subject: wifi: rtw89: debug: rename mac/ctrl error to L0/L1 error Sync Realtek terms on SER (system error recovery) simulation. No logic is changed. Signed-off-by: Zong-Zhe Yang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260127085036.44060-2-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/debug.c | 32 +++++++++++++++--------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c index 969b9c7e35a3..56b52e780dac 100644 --- a/drivers/net/wireless/realtek/rtw89/debug.c +++ b/drivers/net/wireless/realtek/rtw89/debug.c @@ -3538,7 +3538,7 @@ out: return count; } -static int rtw89_dbg_trigger_ctrl_error_by_halt_h2c(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev) { if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) return -EBUSY; @@ -3546,7 +3546,7 @@ static int rtw89_dbg_trigger_ctrl_error_by_halt_h2c(struct rtw89_dev *rtwdev) return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE); } -static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev) { const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; struct rtw89_cpuio_ctrl ctrl_para = {0}; @@ -3554,7 +3554,7 @@ static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) int ret; if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) - return rtw89_dbg_trigger_ctrl_error_by_halt_h2c(rtwdev); + return rtw89_dbg_trigger_l1_error_by_halt_h2c(rtwdev); rtw89_leave_ps_mode(rtwdev); @@ -3576,7 +3576,7 @@ static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) return 0; } -static int rtw89_dbg_trigger_mac_error_ax(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l0_error_ax(struct rtw89_dev *rtwdev) { u16 val16; u8 val8; @@ -3598,7 +3598,7 @@ static int rtw89_dbg_trigger_mac_error_ax(struct rtw89_dev *rtwdev) return 0; } -static int rtw89_dbg_trigger_mac_error_be(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l0_error_be(struct rtw89_dev *rtwdev) { int ret; @@ -3612,7 +3612,7 @@ static int rtw89_dbg_trigger_mac_error_be(struct rtw89_dev *rtwdev) return 0; } -static int rtw89_dbg_trigger_mac_error_by_halt_h2c(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l0_error_by_halt_h2c(struct rtw89_dev *rtwdev) { if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) return -EBUSY; @@ -3620,20 +3620,20 @@ static int rtw89_dbg_trigger_mac_error_by_halt_h2c(struct rtw89_dev *rtwdev) return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE); } -static int rtw89_dbg_trigger_mac_error(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev) { const struct rtw89_chip_info *chip = rtwdev->chip; if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) - return rtw89_dbg_trigger_mac_error_by_halt_h2c(rtwdev); + return rtw89_dbg_trigger_l0_error_by_halt_h2c(rtwdev); rtw89_leave_ps_mode(rtwdev); switch (chip->chip_gen) { case RTW89_CHIP_AX: - return rtw89_dbg_trigger_mac_error_ax(rtwdev); + return rtw89_dbg_trigger_l0_error_ax(rtwdev); case RTW89_CHIP_BE: - return rtw89_dbg_trigger_mac_error_be(rtwdev); + return rtw89_dbg_trigger_l0_error_be(rtwdev); default: return -EOPNOTSUPP; } @@ -3653,8 +3653,8 @@ rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, enum rtw89_dbg_crash_simulation_type { RTW89_DBG_SIM_CPU_EXCEPTION = 1, - RTW89_DBG_SIM_CTRL_ERROR = 2, - RTW89_DBG_SIM_MAC_ERROR = 3, + RTW89_DBG_SIM_L1_ERROR = 2, + RTW89_DBG_SIM_L0_ERROR = 3, }; static ssize_t @@ -3679,11 +3679,11 @@ rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev, return -EOPNOTSUPP; sim = rtw89_fw_h2c_trigger_cpu_exception; break; - case RTW89_DBG_SIM_CTRL_ERROR: - sim = rtw89_dbg_trigger_ctrl_error; + case RTW89_DBG_SIM_L1_ERROR: + sim = rtw89_dbg_trigger_l1_error; break; - case RTW89_DBG_SIM_MAC_ERROR: - sim = rtw89_dbg_trigger_mac_error; + case RTW89_DBG_SIM_L0_ERROR: + sim = rtw89_dbg_trigger_l0_error; /* Driver SER flow won't get involved; only FW will. */ announce = false; -- cgit v1.2.3 From 6792fcf6a69128be0ee4aec51f08e9e960a3fc70 Mon Sep 17 00:00:00 2001 From: Zong-Zhe Yang Date: Tue, 27 Jan 2026 16:50:32 +0800 Subject: wifi: rtw89: debug: tweak Wi-Fi 7 SER L0/L1 simulation methods SER (system error recovery) L0/L1 simulation has two kinds of methods. How to choose them depends on FW features. But, Wi-Fi 7 misused them. Signed-off-by: Zong-Zhe Yang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260127085036.44060-3-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/debug.c | 69 +++++++++++++++++++++++++----- drivers/net/wireless/realtek/rtw89/reg.h | 4 ++ 2 files changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c index 56b52e780dac..d46691fa09bc 100644 --- a/drivers/net/wireless/realtek/rtw89/debug.c +++ b/drivers/net/wireless/realtek/rtw89/debug.c @@ -3538,7 +3538,7 @@ out: return count; } -static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l1_error_by_halt_h2c_ax(struct rtw89_dev *rtwdev) { if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) return -EBUSY; @@ -3546,6 +3546,31 @@ static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev) return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE); } +static int rtw89_dbg_trigger_l1_error_by_halt_h2c_be(struct rtw89_dev *rtwdev) +{ + if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) + return -EBUSY; + + rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR, + B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR); + + return 0; +} + +static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev) +{ + const struct rtw89_chip_info *chip = rtwdev->chip; + + switch (chip->chip_gen) { + case RTW89_CHIP_AX: + return rtw89_dbg_trigger_l1_error_by_halt_h2c_ax(rtwdev); + case RTW89_CHIP_BE: + return rtw89_dbg_trigger_l1_error_by_halt_h2c_be(rtwdev); + default: + return -EOPNOTSUPP; + } +} + static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev) { const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; @@ -3600,19 +3625,22 @@ static int rtw89_dbg_trigger_l0_error_ax(struct rtw89_dev *rtwdev) static int rtw89_dbg_trigger_l0_error_be(struct rtw89_dev *rtwdev) { + u8 val8; int ret; ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); if (ret) return ret; - rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, - B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); + val8 = rtw89_read8(rtwdev, R_BE_CMAC_FUNC_EN); + rtw89_write8(rtwdev, R_BE_CMAC_FUNC_EN, val8 & ~B_BE_TMAC_EN); + mdelay(1); + rtw89_write8(rtwdev, R_BE_CMAC_FUNC_EN, val8); return 0; } -static int rtw89_dbg_trigger_l0_error_by_halt_h2c(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l0_error_by_halt_h2c_ax(struct rtw89_dev *rtwdev) { if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) return -EBUSY; @@ -3620,23 +3648,42 @@ static int rtw89_dbg_trigger_l0_error_by_halt_h2c(struct rtw89_dev *rtwdev) return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE); } -static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev) +static int rtw89_dbg_trigger_l0_error_by_halt_h2c_be(struct rtw89_dev *rtwdev) { - const struct rtw89_chip_info *chip = rtwdev->chip; + if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) + return -EBUSY; - if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) - return rtw89_dbg_trigger_l0_error_by_halt_h2c(rtwdev); + rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, + B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); - rtw89_leave_ps_mode(rtwdev); + return 0; +} + +static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev) +{ + const struct rtw89_chip_info *chip = rtwdev->chip; + int (*sim_l0_by_halt_h2c)(struct rtw89_dev *rtwdev); + int (*sim_l0)(struct rtw89_dev *rtwdev); switch (chip->chip_gen) { case RTW89_CHIP_AX: - return rtw89_dbg_trigger_l0_error_ax(rtwdev); + sim_l0_by_halt_h2c = rtw89_dbg_trigger_l0_error_by_halt_h2c_ax; + sim_l0 = rtw89_dbg_trigger_l0_error_ax; + break; case RTW89_CHIP_BE: - return rtw89_dbg_trigger_l0_error_be(rtwdev); + sim_l0_by_halt_h2c = rtw89_dbg_trigger_l0_error_by_halt_h2c_be; + sim_l0 = rtw89_dbg_trigger_l0_error_be; + break; default: return -EOPNOTSUPP; } + + if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) + return sim_l0_by_halt_h2c(rtwdev); + + rtw89_leave_ps_mode(rtwdev); + + return sim_l0(rtwdev); } static ssize_t diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 3239f358aafc..9b2e97ed5c7d 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -4960,6 +4960,10 @@ #define R_BE_SER_L1_DBG_CNT_7 0x845C #define B_BE_SER_L1_DBG_2_MASK GENMASK(31, 0) +#define R_BE_FW_TRIGGER_IDCT_ISR 0x8508 +#define B_BE_DMAC_FW_ERR_IDCT_IMR BIT(31) +#define B_BE_DMAC_FW_TRIG_IDCT BIT(0) + #define R_BE_DMAC_ERR_IMR 0x8520 #define B_BE_DMAC_NOTX_ERR_INT_EN BIT(21) #define B_BE_DMAC_NORX_ERR_INT_EN BIT(20) -- cgit v1.2.3 From 734bb61782d4d7a7d3d4e11bbd1d2eb958c10551 Mon Sep 17 00:00:00 2001 From: Chih-Kang Chang Date: Tue, 27 Jan 2026 16:50:33 +0800 Subject: wifi: rtw89: wow: disable interrupt before swapping FW for 8922D Except for the 8852A, 8852B, 8851B, 8852BT, all subsequent chips use HAXIDMA. Therefore, interrupts need to be disabled before swapping firmware to avoid unexpected SER. Signed-off-by: Chih-Kang Chang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260127085036.44060-4-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/wow.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/wow.c b/drivers/net/wireless/realtek/rtw89/wow.c index 5d3227e2b3e4..b67ceda59e92 100644 --- a/drivers/net/wireless/realtek/rtw89/wow.c +++ b/drivers/net/wireless/realtek/rtw89/wow.c @@ -1267,15 +1267,15 @@ static int rtw89_wow_swap_fw(struct rtw89_dev *rtwdev, bool wow) enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; const struct rtw89_chip_info *chip = rtwdev->chip; bool include_bb = !!chip->bbmcu_nr; - bool disable_intr_for_dlfw = false; + bool disable_intr_for_dlfw = true; struct ieee80211_sta *wow_sta; struct rtw89_sta_link *rtwsta_link = NULL; struct rtw89_sta *rtwsta; bool is_conn = true; int ret; - if (chip_id == RTL8852C || chip_id == RTL8922A) - disable_intr_for_dlfw = true; + if (chip->chip_gen == RTW89_CHIP_AX && chip_id != RTL8852C) + disable_intr_for_dlfw = false; wow_sta = ieee80211_find_sta(wow_vif, wow_vif->cfg.ap_addr); if (wow_sta) { -- cgit v1.2.3 From 2258f2770e19d645eaa343135a67b595b1e7eddd Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Tue, 27 Jan 2026 16:50:34 +0800 Subject: wifi: rtw89: mac: set MU group membership and position to registers The WiFi 7 chips use different registers to configure MU group for beamforming. Define specific registers and refactor the common flow. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260127085036.44060-5-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/mac.c | 21 +++++++++++++++------ drivers/net/wireless/realtek/rtw89/mac.h | 6 ++++++ drivers/net/wireless/realtek/rtw89/mac_be.c | 7 +++++++ drivers/net/wireless/realtek/rtw89/reg.h | 13 +++++++++++++ 4 files changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c index 4f0f17c499fa..8472f1a63951 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.c +++ b/drivers/net/wireless/realtek/rtw89/mac.c @@ -4374,6 +4374,12 @@ static const struct rtw89_port_reg rtw89_port_base_ax = { R_AX_PORT_HGQ_WINDOW_CFG + 3}, }; +static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_ax = { + .position_en = {R_AX_GID_POSITION_EN0, R_AX_GID_POSITION_EN1}, + .position = {R_AX_GID_POSITION0, R_AX_GID_POSITION1, + R_AX_GID_POSITION2, R_AX_GID_POSITION3}, +}; + static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u8 type) { @@ -6770,6 +6776,8 @@ void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_bss_conf *conf) { + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; + const struct rtw89_mac_mu_gid_addr *addr = mac->mu_gid; struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); struct rtw89_vif_link *rtwvif_link; u8 mac_idx; @@ -6789,20 +6797,20 @@ void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif * p = (__le32 *)conf->mu_group.membership; rtw89_write32(rtwdev, - rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), + rtw89_mac_reg_by_idx(rtwdev, addr->position_en[0], mac_idx), le32_to_cpu(p[0])); rtw89_write32(rtwdev, - rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), + rtw89_mac_reg_by_idx(rtwdev, addr->position_en[1], mac_idx), le32_to_cpu(p[1])); p = (__le32 *)conf->mu_group.position; - rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[0], mac_idx), le32_to_cpu(p[0])); - rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[1], mac_idx), le32_to_cpu(p[1])); - rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[2], mac_idx), le32_to_cpu(p[2])); - rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), + rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[3], mac_idx), le32_to_cpu(p[3])); } @@ -7282,6 +7290,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { .port_base = &rtw89_port_base_ax, .agg_len_ht = R_AX_AGG_LEN_HT_0, .ps_status = R_AX_PPWRBIT_SETTING, + .mu_gid = &rtw89_mac_mu_gid_addr_ax, .muedca_ctrl = { .addr = R_AX_MUEDCA_EN, diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h index 0c8614fc3000..e71a71648ab8 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.h +++ b/drivers/net/wireless/realtek/rtw89/mac.h @@ -1015,6 +1015,11 @@ struct rtw89_mac_size_set { extern const struct rtw89_mac_size_set rtw89_mac_size; +struct rtw89_mac_mu_gid_addr { + u32 position_en[2]; + u32 position[4]; +}; + struct rtw89_mac_gen_def { u32 band1_offset; u32 filter_model_addr; @@ -1025,6 +1030,7 @@ struct rtw89_mac_gen_def { const struct rtw89_port_reg *port_base; u32 agg_len_ht; u32 ps_status; + const struct rtw89_mac_mu_gid_addr *mu_gid; struct rtw89_reg_def muedca_ctrl; struct rtw89_reg_def bfee_ctrl; diff --git a/drivers/net/wireless/realtek/rtw89/mac_be.c b/drivers/net/wireless/realtek/rtw89/mac_be.c index 3a84cd529148..dc66b1ee851a 100644 --- a/drivers/net/wireless/realtek/rtw89/mac_be.c +++ b/drivers/net/wireless/realtek/rtw89/mac_be.c @@ -62,6 +62,12 @@ static const struct rtw89_port_reg rtw89_port_base_be = { R_BE_PORT_HGQ_WINDOW_CFG + 3}, }; +static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_be = { + .position_en = {R_BE_GID_POSITION_EN0, R_BE_GID_POSITION_EN1}, + .position = {R_BE_GID_POSITION0, R_BE_GID_POSITION1, + R_BE_GID_POSITION2, R_BE_GID_POSITION3}, +}; + static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, enum rtw89_mac_hwmod_sel sel) { @@ -3170,6 +3176,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .port_base = &rtw89_port_base_be, .agg_len_ht = R_BE_AGG_LEN_HT_0, .ps_status = R_BE_WMTX_POWER_BE_BIT_CTL, + .mu_gid = &rtw89_mac_mu_gid_addr_be, .muedca_ctrl = { .addr = R_BE_MUEDCA_EN, diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 9b2e97ed5c7d..9b605617c3f0 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -6501,6 +6501,19 @@ #define BE_WMAC_RFMOD_160M 3 #define BE_WMAC_RFMOD_320M 4 +#define R_BE_GID_POSITION0 0x10070 +#define R_BE_GID_POSITION0_C1 0x14070 +#define R_BE_GID_POSITION1 0x10074 +#define R_BE_GID_POSITION1_C1 0x14074 +#define R_BE_GID_POSITION2 0x10078 +#define R_BE_GID_POSITION2_C1 0x14078 +#define R_BE_GID_POSITION3 0x1007C +#define R_BE_GID_POSITION3_C1 0x1407C +#define R_BE_GID_POSITION_EN0 0x10080 +#define R_BE_GID_POSITION_EN0_C1 0x14080 +#define R_BE_GID_POSITION_EN1 0x10084 +#define R_BE_GID_POSITION_EN1_C1 0x14084 + #define R_BE_TX_SUB_BAND_VALUE 0x10088 #define R_BE_TX_SUB_BAND_VALUE_C1 0x14088 #define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16) -- cgit v1.2.3 From af1e82232b988f8fc6d635c60609765e49221a64 Mon Sep 17 00:00:00 2001 From: Dian-Syuan Yang Date: Tue, 27 Jan 2026 16:50:35 +0800 Subject: wifi: rtw89: pci: restore LDO setting after device resume The LDO (Low Dropout Regulator) setting is missing after suspend/resume in some platforms, and it will cause card loss. Therefore, reconfigure this setting to avoid it. Signed-off-by: Dian-Syuan Yang Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260127085036.44060-6-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c index b8135cf15d13..fb4469a76bc0 100644 --- a/drivers/net/wireless/realtek/rtw89/pci.c +++ b/drivers/net/wireless/realtek/rtw89/pci.c @@ -4605,6 +4605,7 @@ static int __maybe_unused rtw89_pci_resume(struct device *dev) rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_SEL_REQ_ENTR_L1); } + rtw89_pci_hci_ldo(rtwdev); rtw89_pci_l2_hci_ldo(rtwdev); rtw89_pci_basic_cfg(rtwdev, true); -- cgit v1.2.3 From 4c1552473acf03cad828884b4e1c90b97a89b265 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Tue, 27 Jan 2026 16:50:36 +0800 Subject: wifi: rtw89: pci: warn if SPS OCP happens for RTL8922DE SPS OCP (over current protection) is a mechanism to cut off power to protect hardware. When this happens, raise an interrupt to signal driver, which prints out a message to note hardware status. Signed-off-by: Ping-Ke Shih Link: https://patch.msgid.link/20260127085036.44060-7-pkshih@realtek.com --- drivers/net/wireless/realtek/rtw89/pci.c | 10 ++++++++-- drivers/net/wireless/realtek/rtw89/pci.h | 1 + drivers/net/wireless/realtek/rtw89/pci_be.c | 2 ++ 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c index fb4469a76bc0..43c61b3dc969 100644 --- a/drivers/net/wireless/realtek/rtw89/pci.c +++ b/drivers/net/wireless/realtek/rtw89/pci.c @@ -970,6 +970,9 @@ static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev) if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_wdt_timeout)) rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT); + if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_sps_ocp)) + rtw89_warn(rtwdev, "SPS OCP alarm 0x%x\n", isrs.halt_c2h_isrs); + if (unlikely(rtwpci->under_recovery)) goto enable_intr; @@ -4005,7 +4008,8 @@ static void rtw89_pci_recovery_intr_mask_v3(struct rtw89_dev *rtwdev) struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; - rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; + rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN | + B_BE_SPSANA_OCP_INT_EN | B_BE_SPS_OCP_INT_EN; rtwpci->intrs[0] = 0; rtwpci->intrs[1] = 0; } @@ -4015,7 +4019,8 @@ static void rtw89_pci_default_intr_mask_v3(struct rtw89_dev *rtwdev) struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; - rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; + rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN | + B_BE_SPSANA_OCP_INT_EN | B_BE_SPS_OCP_INT_EN; rtwpci->intrs[0] = 0; rtwpci->intrs[1] = B_BE_PCIE_RDU_CH1_IMR | B_BE_PCIE_RDU_CH0_IMR | @@ -4657,6 +4662,7 @@ const struct rtw89_pci_isr_def rtw89_pci_isr_ax = { .isr_rdu = B_AX_RDU_INT, .isr_halt_c2h = B_AX_HALT_C2H_INT_EN, .isr_wdt_timeout = B_AX_WDT_TIMEOUT_INT_EN, + .isr_sps_ocp = 0, .isr_clear_rpq = {R_AX_PCIE_HISR00, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT}, .isr_clear_rxq = {R_AX_PCIE_HISR00, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | B_AX_RDU_INT}, diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h index b0081b694046..ccfa6d33623a 100644 --- a/drivers/net/wireless/realtek/rtw89/pci.h +++ b/drivers/net/wireless/realtek/rtw89/pci.h @@ -1331,6 +1331,7 @@ struct rtw89_pci_isr_def { u32 isr_rdu; u32 isr_halt_c2h; u32 isr_wdt_timeout; + u32 isr_sps_ocp; struct rtw89_reg2_def isr_clear_rpq; struct rtw89_reg2_def isr_clear_rxq; }; diff --git a/drivers/net/wireless/realtek/rtw89/pci_be.c b/drivers/net/wireless/realtek/rtw89/pci_be.c index 33bdd3e66bf6..114f40c6c31b 100644 --- a/drivers/net/wireless/realtek/rtw89/pci_be.c +++ b/drivers/net/wireless/realtek/rtw89/pci_be.c @@ -763,6 +763,7 @@ const struct rtw89_pci_isr_def rtw89_pci_isr_be = { .isr_rdu = B_BE_RDU_CH1_INT_V1 | B_BE_RDU_CH0_INT_V1, .isr_halt_c2h = B_BE_HALT_C2H_INT, .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, + .isr_sps_ocp = 0, .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, }; @@ -772,6 +773,7 @@ const struct rtw89_pci_isr_def rtw89_pci_isr_be_v1 = { .isr_rdu = B_BE_PCIE_RDU_CH1_INT | B_BE_PCIE_RDU_CH0_INT, .isr_halt_c2h = B_BE_HALT_C2H_INT, .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, + .isr_sps_ocp = B_BE_SPS_OCP_INT | B_BE_SPSANA_OCP_INT, .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, }; -- cgit v1.2.3