From 1476253cef9dbfc1f7f6a1bd19252ca528cd63bd Mon Sep 17 00:00:00 2001 From: "Andrew Y. Kuksov" Date: Tue, 14 Jul 2015 16:23:25 +0300 Subject: spi: imx: fix ecspi mode setup Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3 SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2 and SPI_MODE_3 requires clk high when inactive. Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data Phase Control), SCLK_POL (SPI Clock Polarity Control), SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS Polarity Select) of ECSPIx_CONFIGREG register. This patch allows driver to clear corresponding bits in these fields. Signed-off-by: Andrew Y. Kuksov Signed-off-by: Mark Brown --- drivers/spi/spi-imx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index f9deb84e4e55..0e5723ab47f0 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -336,13 +336,20 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, if (config->mode & SPI_CPHA) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); + else + cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs); if (config->mode & SPI_CPOL) { cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); + } else { + cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs); + cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs); } if (config->mode & SPI_CS_HIGH) cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); + else + cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs); writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); -- cgit v1.2.3