From 8a9071299dec817a544c0fb48f7302396fafdc4b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 26 Feb 2026 08:17:55 +0000 Subject: riscv: dts: spacemit: pcie: fix missing power regulator The PCIe port require 3.3v power regulator for device to work properly, So explicitly add it to fix the DT warning: arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dtb: pcie@ca400000 (spacemit,k1-pcie): pcie@0: 'vpcie3v3-supply' is a required property from schema $id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml Fixes: 0be016a4b5d1 ("riscv: dts: spacemit: PCIe and PHY-related updates") Reported-by: Conor Dooley Link: https://lore.kernel.org/r/20260226-k1-pcie-fix-pwr-v1-1-94b493cd27e5@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 5971605754b3..51f6c6a774b0 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -305,6 +305,7 @@ &pcie1_port { phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; }; &pcie1 { @@ -320,6 +321,7 @@ &pcie2_port { phys = <&pcie2_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; }; &pcie2 { -- cgit v1.2.3 From 108c77b34b929e6bdb7ac9613ed65c90da8bcb9f Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:04 +0800 Subject: riscv: dts: spacemit: Update PMIC supply properties for BPI-F3 and Jupiter Use per-regulator supply names in pmic "spacemit,p1" node to specify each board's power tree topology and match the updated dt-binding. Signed-off-by: Guodong Xu Reviewed-by: Alex Elder Link: https://lore.kernel.org/r/20260206-spacemit-p1-v4-3-8f695d93811e@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++-- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 12 ++++++++++-- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 51f6c6a774b0..ed88507b84e9 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -190,7 +190,15 @@ compatible = "spacemit,p1"; reg = <0x41>; interrupts = <64>; - vin-supply = <®_vcc_4v>; + vin1-supply = <®_vcc_4v>; + vin2-supply = <®_vcc_4v>; + vin3-supply = <®_vcc_4v>; + vin4-supply = <®_vcc_4v>; + vin5-supply = <®_vcc_4v>; + vin6-supply = <®_vcc_4v>; + aldoin-supply = <®_vcc_4v>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; regulators { buck1 { @@ -221,7 +229,7 @@ regulator-always-on; }; - buck5 { + buck5: buck5 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3450000>; regulator-ramp-delay = <5000>; diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 800a112d5d70..e2702a781734 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -100,7 +100,15 @@ compatible = "spacemit,p1"; reg = <0x41>; interrupts = <64>; - vin-supply = <®_vcc_4v>; + vin1-supply = <®_vcc_4v>; + vin2-supply = <®_vcc_4v>; + vin3-supply = <®_vcc_4v>; + vin4-supply = <®_vcc_4v>; + vin5-supply = <®_vcc_4v>; + vin6-supply = <®_vcc_4v>; + aldoin-supply = <®_vcc_4v>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; regulators { buck1 { @@ -131,7 +139,7 @@ regulator-always-on; }; - buck5 { + buck5: buck5 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3450000>; regulator-ramp-delay = <5000>; -- cgit v1.2.3 From ec1fb4e55df47ed043ab2ccc6787e39b9d67e49b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 26 Feb 2026 09:35:00 +0000 Subject: riscv: dts: spacemit: adapt regulator node name to preferred form The preferred node name for fixed-regulators has changed to pattern [1]: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' Adjust all SpacemiT DT regulator node names to fix this. Reviewed-by: Javier Martinez Canillas Link: https://lore.kernel.org/r/20240426215147.3138211-1-robh@kernel.org [1] Link: https://lore.kernel.org/r/20260226-02-k1-regulator-names-v1-1-e87695d50159@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 10 +++++----- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index ed88507b84e9..404b69c47b91 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -33,7 +33,7 @@ }; }; - pcie_vcc_3v3: pcie-vcc3v3 { + pcie_vcc_3v3: regulator-pcie-vcc3v3 { compatible = "regulator-fixed"; regulator-name = "PCIE_VCC3V3"; regulator-min-microvolt = <3300000>; @@ -41,7 +41,7 @@ regulator-always-on; }; - reg_dc_in: dc-in-12v { + reg_dc_in: regulator-dc-in-12v { compatible = "regulator-fixed"; regulator-name = "dc_in_12v"; regulator-min-microvolt = <12000000>; @@ -50,7 +50,7 @@ regulator-always-on; }; - reg_vcc_4v: vcc-4v { + reg_vcc_4v: regulator-vcc-4v { compatible = "regulator-fixed"; regulator-name = "vcc_4v"; regulator-min-microvolt = <4000000>; @@ -60,7 +60,7 @@ vin-supply = <®_dc_in>; }; - usb3-vbus-5v { + regulator-usb3-vbus-5v { compatible = "regulator-fixed"; regulator-name = "USB30_VBUS"; regulator-min-microvolt = <5000000>; @@ -70,7 +70,7 @@ enable-active-high; }; - usb3_hub_5v: usb3-hub-5v { + usb3_hub_5v: regulator-usb3-hub-5v { compatible = "regulator-fixed"; regulator-name = "USB30_HUB"; regulator-min-microvolt = <5000000>; diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index e2702a781734..9959c8023ece 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -21,7 +21,7 @@ stdout-path = "serial0"; }; - reg_dc_in: dc-in-12v { + reg_dc_in: regulator-dc-in-12v { compatible = "regulator-fixed"; regulator-name = "dc_in_12v"; regulator-min-microvolt = <12000000>; @@ -30,7 +30,7 @@ regulator-always-on; }; - reg_vcc_4v: vcc-4v { + reg_vcc_4v: regulator-vcc-4v { compatible = "regulator-fixed"; regulator-name = "vcc_4v"; regulator-min-microvolt = <4000000>; -- cgit v1.2.3 From 86314111f654310a69c9775e35e263c036031675 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 9 Mar 2026 11:00:00 +0800 Subject: riscv: dts: spacemit: Add 'linux,pci-domain' to PCIe nodes for K1 The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the 'linux,pci-domain' property to assign a PCI domain number to each of the controllers instead of assigning it randomly. This creates a stable sysfs path, allowing userspace scripts to reliably target specific PCIe devices (such as PCIe NICs). Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260309030000.1157040-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 529ec68e9c23..d2015201f8e5 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -1033,6 +1033,7 @@ #size-cells = <2>; dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; + pcie0: pcie@ca000000 { device_type = "pci"; compatible = "spacemit,k1-pcie"; @@ -1044,6 +1045,7 @@ "atu", "config", "link"; + linux,pci-domain = <0>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, @@ -1087,6 +1089,7 @@ "atu", "config", "link"; + linux,pci-domain = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, @@ -1130,6 +1133,7 @@ "atu", "config", "link"; + linux,pci-domain = <2>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, -- cgit v1.2.3 From 606a6b8bca570aa4f838ddd410345a2937bd98eb Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:19:39 +0000 Subject: dt-bindings: serial: 8250: spacemit: fix clock property for K3 SoC The UART of SpacemiT K3 SoC has same clock property as K1 generation which request two clock sources, fix the binding otherwise will get DT check warnings. Acked-by: Greg Kroah-Hartman Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260304-01-uart-clock-names-v1-1-338483f04a8b@kernel.org Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/serial/8250.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index 73851f19330d..e9e07c2356bc 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -63,7 +63,9 @@ allOf: properties: compatible: contains: - const: spacemit,k1-uart + enum: + - spacemit,k1-uart + - spacemit,k3-uart then: properties: clock-names: @@ -76,6 +78,7 @@ allOf: contains: enum: - spacemit,k1-uart + - spacemit,k3-uart - nxp,lpc1850-uart then: required: -- cgit v1.2.3 From 67072c8cd48c1fbb95cea39239eba5526395fcf5 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:42 +0000 Subject: riscv: dts: spacemit: k3: add clock tree Add clock support to SpacemiT K3 SoC, the clock tree consist of several blocks which are APBC, APMU, DCIU, MPUM. Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-1-50a0aa53a245@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index b69cf81b5d55..e3d7f3102fd5 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2026 Guodong Xu */ +#include #include /dts-v1/; @@ -398,6 +399,36 @@ }; }; + clocks { + vctcxo_1m: clock-1m { + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "vctcxo_1m"; + #clock-cells = <0>; + }; + + vctcxo_24m: clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "vctcxo_24m"; + #clock-cells = <0>; + }; + + vctcxo_3m: clock-3m { + compatible = "fixed-clock"; + clock-frequency = <3000000>; + clock-output-names = "vctcxo_3m"; + #clock-cells = <0>; + }; + + osc_32k: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&saplic>; @@ -406,6 +437,15 @@ dma-noncoherent; ranges; + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart0: serial@d4017000 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017000 0x0 0x100>; @@ -506,6 +546,41 @@ status = "disabled"; }; + syscon_mpmu: system-controller@d4050000 { + compatible = "spacemit,k3-syscon-mpmu"; + reg = <0x0 0xd4050000 0x0 0x10000>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + pll: clock-controller@d4090000 { + compatible = "spacemit,k3-pll"; + reg = <0x0 0xd4090000 0x0 0x10000>; + clocks = <&vctcxo_24m>; + spacemit,mpmu = <&syscon_mpmu>; + #clock-cells = <1>; + }; + + syscon_apmu: system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x0 0xd4282800 0x0 0x400>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + syscon_dciu: system-controller@d8440000 { + compatible = "spacemit,k3-syscon-dciu"; + reg = <0x0 0xd8440000 0x0 0xc000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + simsic: interrupt-controller@e0400000 { compatible = "spacemit,k3-imsics", "riscv,imsics"; reg = <0x0 0xe0400000 0x0 0x200000>; -- cgit v1.2.3 From d8944577496b5b99061d3b2020704fc86ab1f9e6 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:43 +0000 Subject: riscv: dts: spacemit: k3: add pinctrl support Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices can request pinctrl resource properly. Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-2-50a0aa53a245@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index e3d7f3102fd5..6449ab056293 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -536,6 +536,14 @@ status = "disabled"; }; + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; + clocks = <&syscon_apbc CLK_APBC_AIB>, + <&syscon_apbc CLK_APBC_AIB_BUS>; + clock-names = "func", "bus"; + }; + uart10: serial@d401f000 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd401f000 0x0 0x100>; -- cgit v1.2.3 From 20b77926864203e10b85af5276b17c2812d92ec1 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:44 +0000 Subject: riscv: dts: spacemit: k3: add GPIO support Add GPIO node in the Device Tree, so devices are able to request GPIO resource properly. Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-3-50a0aa53a245@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 6449ab056293..3683a1a65362 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -536,6 +536,24 @@ status = "disabled"; }; + gpio: gpio@d4019000 { + compatible = "spacemit,k3-gpio"; + reg = <0x0 0xd4019000 0x0 0x100>; + clocks = <&syscon_apbc CLK_APBC_GPIO>, + <&syscon_apbc CLK_APBC_GPIO_BUS>; + clock-names = "core", "bus"; + gpio-controller; + #gpio-cells = <3>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-ranges = <&pinctrl 0 0 0 32>, + <&pinctrl 1 0 32 32>, + <&pinctrl 2 0 64 32>, + <&pinctrl 3 0 96 32>; + }; + pinctrl: pinctrl@d401e000 { compatible = "spacemit,k3-pinctrl"; reg = <0x0 0xd401e000 0x0 0x1000>; -- cgit v1.2.3 From 28a7f755d7c9a4b9c41c12620fb4885f39b554ad Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:45 +0000 Subject: riscv: dts: spacemit: k3: add full resource to UART Previously the UART rely on external bootloader to initialize clock, pinctrl and reset, to solve this, explicitly adding those resource in Device Tree, so UART driver will handle them properly. Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-4-50a0aa53a245@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 24 +++++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 51 ++++++++++++++++++++++------ 3 files changed, 68 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b691304d4b74..b098dbd0e7a1 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -5,6 +5,7 @@ */ #include "k3.dtsi" +#include "k3-pinctrl.dtsi" / { model = "SpacemiT K3 Pico-ITX"; @@ -25,5 +26,7 @@ }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi new file mode 100644 index 000000000000..efb0f1572188 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026 Yixun Lan + */ + +#include + +#define K3_PADCONF(pin, func) (((pin) << 16) | (func)) + +/* Map GPIO pin to each bank's */ +#define K3_GPIO(x) (x / 32) (x % 32) + +&pinctrl { + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { + pinmux = , /* uart0 tx */ + ; /* uart0 rx */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 3683a1a65362..a3a8ceddabec 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include /dts-v1/; @@ -451,7 +452,10 @@ reg = <0x0 0xd4017000 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART0>, + <&syscon_apbc CLK_APBC_UART0_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART0>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -461,7 +465,10 @@ reg = <0x0 0xd4017100 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART2>, + <&syscon_apbc CLK_APBC_UART2_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART2>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -471,7 +478,10 @@ reg = <0x0 0xd4017200 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART3>, + <&syscon_apbc CLK_APBC_UART3_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART3>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -481,7 +491,10 @@ reg = <0x0 0xd4017300 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART4>, + <&syscon_apbc CLK_APBC_UART4_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART4>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -491,7 +504,10 @@ reg = <0x0 0xd4017400 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART5>, + <&syscon_apbc CLK_APBC_UART5_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART5>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -501,7 +517,10 @@ reg = <0x0 0xd4017500 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART6>, + <&syscon_apbc CLK_APBC_UART6_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART6>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -511,7 +530,10 @@ reg = <0x0 0xd4017600 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART7>, + <&syscon_apbc CLK_APBC_UART7_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART7>; interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -521,7 +543,10 @@ reg = <0x0 0xd4017700 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART8>, + <&syscon_apbc CLK_APBC_UART8_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART8>; interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -531,7 +556,10 @@ reg = <0x0 0xd4017800 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART9>, + <&syscon_apbc CLK_APBC_UART9_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART9>; interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -567,7 +595,10 @@ reg = <0x0 0xd401f000 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART10>, + <&syscon_apbc CLK_APBC_UART10_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART10>; interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; -- cgit v1.2.3 From eac600d5cc42b04e799fb65169b8f4060773381b Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 18 Mar 2026 18:00:00 +0800 Subject: riscv: dts: spacemit: reorder phy nodes for K1 Reorder the PHY nodes of USB and PCIe to the correct positions based on the register address. This improves the readability and maintainability of the DT. No functional change is introduced by this reordering. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260318100000.3934516-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 108 +++++++++++++++++------------------ 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index d2015201f8e5..f0bad6855c97 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -359,6 +359,60 @@ #reset-cells = <1>; }; + usbphy2: phy@c0a30000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0x0 0xc0a30000 0x0 0x200>; + clocks = <&syscon_apmu CLK_USB30>; + #phy-cells = <0>; + status = "disabled"; + }; + + combo_phy: phy@c0b10000 { + compatible = "spacemit,k1-combo-phy"; + reg = <0x0 0xc0b10000 0x0 0x1000>; + clocks = <&vctcxo_24m>, + <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names = "refclk", + "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, + <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names = "phy", + "dbi", + "mstr", + "slv"; + #phy-cells = <1>; + spacemit,apmu = <&syscon_apmu>; + status = "disabled"; + }; + + pcie1_phy: phy@c0c10000 { + compatible = "spacemit,k1-pcie-phy"; + reg = <0x0 0xc0c10000 0x0 0x1000>; + clocks = <&vctcxo_24m>; + clock-names = "refclk"; + resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie2_phy: phy@c0d10000 { + compatible = "spacemit,k1-pcie-phy"; + reg = <0x0 0xc0d10000 0x0 0x1000>; + clocks = <&vctcxo_24m>; + clock-names = "refclk"; + resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@d4010800 { compatible = "spacemit,k1-i2c"; reg = <0x0 0xd4010800 0x0 0x38>; @@ -429,60 +483,6 @@ status = "disabled"; }; - usbphy2: phy@c0a30000 { - compatible = "spacemit,k1-usb2-phy"; - reg = <0x0 0xc0a30000 0x0 0x200>; - clocks = <&syscon_apmu CLK_USB30>; - #phy-cells = <0>; - status = "disabled"; - }; - - combo_phy: phy@c0b10000 { - compatible = "spacemit,k1-combo-phy"; - reg = <0x0 0xc0b10000 0x0 0x1000>; - clocks = <&vctcxo_24m>, - <&syscon_apmu CLK_PCIE0_DBI>, - <&syscon_apmu CLK_PCIE0_MASTER>, - <&syscon_apmu CLK_PCIE0_SLAVE>; - clock-names = "refclk", - "dbi", - "mstr", - "slv"; - resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, - <&syscon_apmu RESET_PCIE0_DBI>, - <&syscon_apmu RESET_PCIE0_MASTER>, - <&syscon_apmu RESET_PCIE0_SLAVE>; - reset-names = "phy", - "dbi", - "mstr", - "slv"; - #phy-cells = <1>; - spacemit,apmu = <&syscon_apmu>; - status = "disabled"; - }; - - pcie1_phy: phy@c0c10000 { - compatible = "spacemit,k1-pcie-phy"; - reg = <0x0 0xc0c10000 0x0 0x1000>; - clocks = <&vctcxo_24m>; - clock-names = "refclk"; - resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; - reset-names = "phy"; - #phy-cells = <0>; - status = "disabled"; - }; - - pcie2_phy: phy@c0d10000 { - compatible = "spacemit,k1-pcie-phy"; - reg = <0x0 0xc0d10000 0x0 0x1000>; - clocks = <&vctcxo_24m>; - clock-names = "refclk"; - resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; - reset-names = "phy"; - #phy-cells = <0>; - status = "disabled"; - }; - syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; -- cgit v1.2.3 From c68360c0d636dae71f766b7b296ddfcf2827ccc7 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sun, 22 Mar 2026 21:25:01 +0100 Subject: riscv: dts: spacemit: drop incorrect pinctrl for combo PHY The combo PHY on the Banana Pi F3 is used for the USB 3.0 port. The high speed differential lanes are always configured as such, and do not require a pinctrl entry. The existing pinctrl entry only configures PCIe secondary pins, which are unused for USB and instead routed to the MIPI CSI1 connector. Remove this incorrect pinctrl entry. Fixes: 0be016a4b5d1b9 ("riscv: dts: spacemit: PCIe and PHY-related updates") Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260322202502.2205755-1-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 404b69c47b91..5790d927b93d 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -81,8 +81,6 @@ }; &combo_phy { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_3_cfg>; status = "okay"; }; -- cgit v1.2.3 From 74657a376960252e248089e518cfaaf813906989 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 26 Mar 2026 09:46:17 +0800 Subject: riscv: dts: spacemit: Add ethernet device for K3 Add all ethernet device nodes for K3 SoC. Signed-off-by: Inochi Amaoto Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260326014617.1011732-1-inochiama@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 20 +++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 34 ++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 117 +++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b098dbd0e7a1..504fe6bd46b2 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -3,6 +3,7 @@ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd * Copyright (c) 2026 Guodong Xu */ +#include #include "k3.dtsi" #include "k3-pinctrl.dtsi" @@ -12,6 +13,7 @@ compatible = "spacemit,k3-pico-itx", "spacemit,k3"; aliases { + ethernet0 = ð0; serial0 = &uart0; }; @@ -25,6 +27,24 @@ }; }; +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + status = "okay"; + + mdio { + phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_0_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index efb0f1572188..a7b5d10c332e 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -11,6 +11,40 @@ #define K3_GPIO(x) (x / 32) (x % 32) &pinctrl { + gmac0_rgmii_0_cfg: gmac0-rgmii-0-cfg { + gmac0-rgmii-0-pins { + pinmux = , /* gmac0_rxdv */ + , /* gmac0_rx_d0 */ + , /* gmac0_rx_d1 */ + , /* gmac0_rx_clk */ + , /* gmac0_rx_d2 */ + , /* gmac0_rx_d3 */ + , /* gmac0_tx_d0 */ + , /* gmac0_tx_d1 */ + , /* gmac0_tx_clk */ + , /* gmac0_tx_d2 */ + , /* gmac0_tx_d3 */ + , /* gmac0_tx_en */ + , /* gmac0_mdc */ + ; /* gmac0_mdio */ + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + + }; + + gmac0_phy_0_cfg: gmac0-phy-0-cfg { + gmac0-phy-0-pins { + pinmux = ; /* gmac0_int */ + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + }; + /omit-if-no-ref/ uart0_0_cfg: uart0-0-cfg { uart0-0-pins { diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index a3a8ceddabec..5f4818cd5d6d 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -438,6 +438,123 @@ dma-noncoherent; ranges; + eth0: ethernet@cac80000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac80000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, + <&syscon_apmu CLK_APMU_EMAC0_1588>, + <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, + <276 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC0>; + reset-names = "stmmaceth"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac0_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac0_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + /* max axi burst len is 256 */ + snps,blen = <256 128 64 32 16 0 0>; + }; + }; + + eth1: ethernet@cac82000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac82000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, + <&syscon_apmu CLK_APMU_EMAC1_1588>, + <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, + <277 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC1>; + reset-names = "stmmaceth"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac1_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac1_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + /* max axi burst len is 256 */ + snps,blen = <256 128 64 32 16 0 0>; + }; + }; + + eth2: ethernet@cac8e000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac8e000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, + <&syscon_apmu CLK_APMU_EMAC2_1588>, + <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, + <278 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC2>; + reset-names = "stmmaceth"; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac2_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x248 0x24c>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac2_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + /* max axi burst len is 256 */ + snps,blen = <256 128 64 32 16 0 0>; + }; + }; + syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k3-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; -- cgit v1.2.3 From 334e64abacd3df4005de80b082d0dbf02b453c76 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:29 +0100 Subject: riscv: dts: spacemit: add LEDs for Milk-V Jupiter board The Milk-V Jupiter board provides support for two LEDs through the front panel header. The "Power LED" indicates the system is running, and the "HDD LED" shows disk activity. Configure the corresponding LED triggers accordingly. Caveats: - The LEDs are driven through a 4.7k series resistor, making them quite faint. - The disk activity trigger requires a storage controller on the M.2 or PCIe interface. That said, it matches the purpose and the vendor kernel. Signed-off-by: Aurelien Jarno Reviewed-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260326183745.1370642-2-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 9959c8023ece..3cd83c5924e4 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -21,6 +21,23 @@ stdout-path = "serial0"; }; + leds { + compatible = "gpio-leds"; + + led1 { + label = "pwr-led"; + gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "on"; + }; + + led2 { + label = "hdd-led"; + gpios = <&gpio K1_GPIO(92) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + reg_dc_in: regulator-dc-in-12v { compatible = "regulator-fixed"; regulator-name = "dc_in_12v"; -- cgit v1.2.3 From 77156216f1d0f57e1cfce3452410db20468edca4 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:30 +0100 Subject: riscv: dts: spacemit: add 24c04 eeprom on Milk-V Jupiter The Milk-V Jupiter board includes a 24c04 eeprom on the i2c2 bus. The eeprom contains an ONIE TLV table, which on the board I tested only provides a product-name entry. Expose it via an onie,tlv-layout nvmem layout. The eeprom is marked as read-only since its contents are not supposed to be modified. Signed-off-by: Aurelien Jarno Reviewed-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260326183745.1370642-3-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 3cd83c5924e4..bd48208a370c 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -108,6 +108,28 @@ status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_0_cfg>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; /* EEPROM_VCC18 */ + pagesize = <16>; + read-only; + size = <512>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + product-name { + }; + }; + }; +}; + &i2c8 { pinctrl-0 = <&i2c8_cfg>; pinctrl-names = "default"; -- cgit v1.2.3 From 7af5edec73d5d69618541f91600adeb6f35b7d17 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:31 +0100 Subject: riscv: dts: spacemit: add i2c aliases on Milk-V Jupiter Add i2c aliases for i2c2 and i2c8 on Milk-V Jupiter. This is useful to keep a stable number for the /dev entries after loading the i2c-dev module. Signed-off-by: Aurelien Jarno Reviewed-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260326183745.1370642-4-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index bd48208a370c..836311c3f035 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -15,6 +15,8 @@ ethernet0 = ð0; ethernet1 = ð1; serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; }; chosen { -- cgit v1.2.3 From 2829823956f0f590f5c6b4eafed2dab7a96f69b3 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:32 +0100 Subject: riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter Add the QSPI controller node for the Milk-V Jupiter board and describe the attached SPI NOR flash (GD25Q64E). The flash supports a frequency up to 133MHz (80 MHz for reads), and the SoC supports a frequency up to 104 MHz. However tests have shown that the flash is not reliably detected above 26.5 MHz, consistent with frequency used in the vendor kernel. Therefore, use this frequency. The m25p,fast-read properties is taken from the vendor kernel, and the GD25Q64E datasheet confirms tha the fast read opcodes are supported. Add a corresponding flash partition layout, matching the layout and the names used in the vendor U-Boot. Signed-off-by: Aurelien Jarno Reviewed-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260326183745.1370642-5-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 43 ++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 836311c3f035..bac6438c6753 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -173,7 +173,7 @@ regulator-always-on; }; - buck4 { + buck4_3v3: buck4 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3300000>; regulator-ramp-delay = <5000>; @@ -256,6 +256,47 @@ }; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x0 0x10000>; + }; + private@10000 { + reg = <0x10000 0x10000>; + }; + fsbl@20000 { + reg = <0x20000 0x40000>; + }; + env@60000 { + reg = <0x60000 0x10000>; + }; + opensbi@70000 { + reg = <0x70000 0x30000>; + }; + uboot@a00000 { + reg = <0xa0000 0x760000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; -- cgit v1.2.3 From dce01d8585a22f708b5f1eb621cacd9878258ac8 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:33 +0100 Subject: riscv: dts: spacemit: enable USB 3 ports on Milk-V Jupiter Enable the DWC3 USB 3.0 controller (USB#2 port in the K1 datasheet) and its associated combo_phy (USB 3 PHY) and usbphy2 (USB 2 PHY) on the Milk-V Jupiter board. The board uses a VLI VL817 hub, providing four ports. Two are routed to the 3.0 type-A connectors, and two to the F_USB3 front USB header. The hub requires two separate 5V power supplies: one for the hub itself and one for the USB connectors. Add an always-on regulator sourcing 5V from the DC-IN input, along with two GPIO-controlled fixed regulators to manage the hub and connectors power supplies. Note that the board also provides four USB 2.0 ports (two via type-A connectors and two via the F_USB2 front USB header), but these are handled by a different controller (USB#1 port in the K1 datasheet). Signed-off-by: Aurelien Jarno Reviewed-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260326183745.1370642-6-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 62 +++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index bac6438c6753..8eeaf2631b71 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -58,6 +58,41 @@ regulator-always-on; vin-supply = <®_dc_in>; }; + + reg_vcc_5v: regulator-vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_dc_in>; + }; + + regulator-usb3-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_vcc_5v>; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb3_hub_5v: regulator-usb3-hub-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc_5v>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&combo_phy { + status = "okay"; }; ð0 { @@ -302,3 +337,30 @@ pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; + vdd-supply = <&usb3_hub_5v>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; + vdd-supply = <&usb3_hub_5v>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +}; -- cgit v1.2.3 From 2b8bd26bbfcdeb1a06127dcd8f9101080133f2a1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:34 +0100 Subject: riscv: dts: spacemit: enable PCIe ports on Milk-V Jupiter Enable the two PCIe controller along with and their associated PHY. They are routed to the M.2 M-key connector and to the PCIe x8 slot. Add an always-on regulator sourcing 3.3V from the DC-IN input, to power the PCIe ports. Signed-off-by: Aurelien Jarno Reviewed-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260326183745.1370642-7-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 8eeaf2631b71..afaad59e6bce 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -40,6 +40,16 @@ }; }; + pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "pcie_vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_dc_in>; + }; + reg_dc_in: regulator-dc-in-12v { compatible = "regulator-fixed"; regulator-name = "dc_in_12v"; @@ -291,6 +301,38 @@ }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; +}; + +&pcie1 { + vpcie3v3-supply = <&pcie_vcc_3v3>; + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; +}; + +&pcie2 { + vpcie3v3-supply = <&pcie_vcc_3v3>; + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&qspi_cfg>; -- cgit v1.2.3 From cb322cbffb1e70b4ca1be7955ed19fe486de8295 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 27 Mar 2026 11:40:40 +0000 Subject: dts: riscv: spacemit: k3: Add i2c nodes Populate all I2C devicetree nodes for SpacemiT K3 SoC. The controller of i2c3 is reserved for secure domain, and not available from Linux. The controller of i2c7 simply doesn't exist from hardware perspective, as vendor directly name the i2c controller used for PMIC as i2c8. Reviewed-by: Troy Mitchell Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-2119c0918868@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 100 +++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 5f4818cd5d6d..815debd16409 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -555,6 +555,76 @@ }; }; + i2c0: i2c@d4010800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4010800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI0>, + <&syscon_apbc CLK_APBC_TWSI0_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI0>; + status = "disabled"; + }; + + i2c1: i2c@d4011000 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4011000 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI1>, + <&syscon_apbc CLK_APBC_TWSI1_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI1>; + status = "disabled"; + }; + + i2c2: i2c@d4012000 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4012000 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI2>, + <&syscon_apbc CLK_APBC_TWSI2_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI2>; + status = "disabled"; + }; + + i2c4: i2c@d4012800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4012800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI4>, + <&syscon_apbc CLK_APBC_TWSI4_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI4>; + status = "disabled"; + }; + + i2c5: i2c@d4013800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4013800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI5>, + <&syscon_apbc CLK_APBC_TWSI5_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI5>; + status = "disabled"; + }; + syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k3-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; @@ -681,6 +751,20 @@ status = "disabled"; }; + i2c6: i2c@d4018800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4018800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI6>, + <&syscon_apbc CLK_APBC_TWSI6_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI6>; + status = "disabled"; + }; + gpio: gpio@d4019000 { compatible = "spacemit,k3-gpio"; reg = <0x0 0xd4019000 0x0 0x100>; @@ -699,6 +783,20 @@ <&pinctrl 3 0 96 32>; }; + i2c8: i2c@d401d800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd401d800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI8>, + <&syscon_apbc CLK_APBC_TWSI8_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI8>; + status = "disabled"; + }; + pinctrl: pinctrl@d401e000 { compatible = "spacemit,k3-pinctrl"; reg = <0x0 0xd401e000 0x0 0x1000>; @@ -794,6 +892,8 @@ <&cpu7_intc 3>, <&cpu7_intc 7>; }; + /* sec_i2c3: 0xf0614000, not available from Linux */ + mimsic: interrupt-controller@f1000000 { compatible = "spacemit,k3-imsics", "riscv,imsics"; reg = <0x0 0xf1000000 0x0 0x10000>; -- cgit v1.2.3 From af62a095eb0c3359d477b55ef72d2afd94c83c8f Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 27 Mar 2026 11:51:18 +0000 Subject: dts: riscv: spacemit: k3: add P1 PMIC regulator tree Add the P1 PMIC's regulator topology tree for pico-itx board. Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-9c6b374470c6@kernel.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 147 +++++++++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 ++ 2 files changed, 158 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 504fe6bd46b2..4486dc1fe114 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -25,6 +25,153 @@ device_type = "memory"; reg = <0x1 0x00000000 0x4 0x00000000>; }; + + reg_aux_vcc5v: regulator-aux-vcc5v { + compatible = "regulator-fixed"; + regulator-name = "AUX_VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; + + p1@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + vin1-supply = <®_aux_vcc5v>; + vin2-supply = <®_aux_vcc5v>; + vin3-supply = <®_aux_vcc5v>; + vin4-supply = <®_aux_vcc5v>; + vin5-supply = <®_aux_vcc5v>; + vin6-supply = <®_aux_vcc5v>; + aldoin-supply = <®_aux_vcc5v>; + dldoin1-supply = <&buck4>; + dldoin2-supply = <&buck4>; + + regulators { + buck1: buck1 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2: buck2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3: buck3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4: buck4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6: buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1: aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo3: aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4: aldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo1: dldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo2: dldo2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo3: dldo3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo4: dldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + dldo5: dldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo6: dldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo7: dldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; }; ð0 { diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index a7b5d10c332e..23899d3f308a 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -45,6 +45,17 @@ }; }; + /omit-if-no-ref/ + i2c8_cfg: i2c8-cfg { + i2c8-pins { + pinmux = , /* i2c8 scl */ + ; /* i2c8 sda */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + /omit-if-no-ref/ uart0_0_cfg: uart0-0-cfg { uart0-0-pins { -- cgit v1.2.3