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2018-10-19Merge branches 'clk-qcom-sdm845-camcc' and 'clk-mtk-unused' into clk-nextStephen Boyd1-0/+116
- Qualcomm SDM845 camera clock controller * clk-qcom-sdm845-camcc: clk: qcom: Add camera clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Camera clock bindings * clk-mtk-unused: clk: mediatek: remove unused array audio_parents
2018-10-19Merge branch 'clk-renesas' into clk-nextStephen Boyd19-93/+207
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
2018-10-19Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', ↵Stephen Boyd2-0/+12
'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 * clk-spdx: clk: mvebu: use SPDX-License-Identifier clk: renesas: Convert to SPDX identifiers clk: renesas: use SPDX identifier for Renesas drivers clk: s2mps11,s3c64xx: Add SPDX license identifiers clk: max77686: Add SPDX license identifiers * clk-qcom-dfs: clk: qcom: Allocate space for NULL terimation in DFS table clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845 clk: qcom: Add support for RCG to register for DFS * clk-smp2s11-include: clk: s2mps11: Use existing defines from bindings for clock IDs * clk-qcom-8996-missing: clk: qcom: Add some missing gcc clks for msm8996 * clk-qcom-qspi: clk: qcom: Add qspi (Quad SPI) clocks for sdm845 clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
2018-10-17clk: qcom: Add MSM8960/APQ8064's HFPLLsStephen Boyd1-0/+2
Describe the HFPLLs present on MSM8960 and APQ8064 devices. Acked-by: Rob Herring <robh@kernel.org> (bindings) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: imx6q: add mmdc0 ipg clockAnson Huang1-1/+2
i.MX6Q has MMDC0 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: imx6sl: add mmdc ipg clocksAnson Huang1-1/+3
i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: imx6sll: add mmdc1 ipg clockAnson Huang1-1/+2
i.MX6SLL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: imx6sx: add mmdc1 ipg clockAnson Huang1-1/+2
i.MX6SX has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: imx6ul: add mmdc1 ipg clockAnson Huang1-1/+2
i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: at91: add new DT lookup functionAlexandre Belloni1-0/+15
Add a new DT lookup function to lookup for PMC clocks. Note that the #ifndef AT91_PMC_MOSCS section will be removed once all the platforms are converted. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17dt-bindings: clock: Add jz4725b-cgu.h headerPaul Cercueil1-0/+35
This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4725b-cgu driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: qcom: gcc: Add global clock controller driver for QCS404Shefali Jain1-0/+165
Add the clocks supported in global clock controller which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Co-developed-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> [bamse, vkoul: rebase and tidyup for upstream] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Lowercase hex] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: qcom: Add Global Clock controller (GCC) driver for SDM660Taniya Das1-0/+156
Add support for the global clock controller found on SDM660 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. Signed-off-by: Taniya Das <tdas@codeaurora.org> [craig: rename parents to fit upstream, and other cleanups] Signed-off-by: Craig Tatlor <ctatlor97@gmail.com> Acked-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of defines to avoid duplicates] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17dt-bindings: clk: hisilicon: Add bindings for Hi3670 clkManivannan Sadhasivam1-0/+348
Add devicetree bindings for HiSilicon Hi3670 clock controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17dt-bindings: reset: Add binding constants for Actions Semi S900 RMUManivannan Sadhasivam1-0/+65
Add device tree binding constants for Actions Semi S900 SoC Reset Management Unit (RMU). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17dt-bindings: reset: Add binding constants for Actions Semi S700 RMUManivannan Sadhasivam1-0/+34
Add device tree binding constants for Actions Semi S700 SoC Reset Management Unit (RMU). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-15dt-bindings: thermal: samsung: Add SPDX license identifierKrzysztof Kozlowski1-11/+1
Replace GPL license statement with SPDX license identifier (GPL-2.0+). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2018-10-15dt-bindings: clock: samsung: Add SPDX license identifiersKrzysztof Kozlowski11-50/+17
Replace GPL license statements with SPDX license identifiers (GPL-2.0). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2018-10-11clk: rockchip: add clock-id for HCLK_HDMI on rk3066Heiko Stuebner1-1/+2
RK3066 and RK3188 share most of the clock controller but the rk3066 does have an internal hdmi encoder and associated clock. Therefore add a clock-id so that this clock can be used. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-10-10Merge tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx ↵Arnd Bergmann1-0/+116
into next/drivers arm64: zynqmp: SoC CLK changes for v4.20 This patchset adds CCF compliant clock driver for ZynqMP. Clock driver queries supported clock information from firmware and regiters pll and output clocks with CCF. * tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx: drivers: clk: Add ZynqMP clock driver dt-bindings: clock: Add bindings for ZynqMP clock driver firmware: xilinx: Add zynqmp IOCTL API for device control Documentation: xilinx: Add documentation for eemi APIs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-10Merge tag 'reset-for-4.20' of git://git.pengutronix.de/git/pza/linux into ↵Arnd Bergmann1-0/+20
next/drivers Reset controller changes for v4.20 This adds a new driver for the PDC Global (Power Domain Controller) reset controller found on Qualcomm SDM845 SoCs, fixes a potential use-after-free issue in reset_controller_dev.of_xlate() callbacks from __of_reset_control_get(), and trivially fixes a documentation grammar issue. * tag 'reset-for-4.20' of git://git.pengutronix.de/git/pza/linux: reset: Fix potential use-after-free in __of_reset_control_get() reset: qcom: PDC Global (Power Domain Controller) reset controller dt-bindings: reset: Add PDC Global binding for SDM845 SoCs reset: Grammar s/more then once/more than once/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-10Merge tag 'sh-pfc-for-v4.20-tag3' of ↵Linus Walleij1-0/+141
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.20 (take three) - Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033) SoCs, - Add INTC-EX pin groups on R-Car E3.
2018-10-09dt-bindings: clock: Add bindings for ZynqMP clock driverRajan Vaja1-0/+116
Add documentation to describe Xilinx ZynqMP clock driver bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-08dt-bindings: net: vsc8531: add two additional LED modes for VSC8584Quentin Schulz1-0/+2
The VSC8584 (and most likely other PHYs in the same generation) has two additional LED modes that can be picked, so let's add them. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-06dt-bindings: add constants for Microsemi Ocelot SerDes driverQuentin Schulz1-0/+12
The Microsemi Ocelot has multiple SerDes and requires that the SerDes be muxed accordingly to the hardware representation. Let's add a constant for each SerDes available in the Microsemi Ocelot. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-05dt-bindings: clock: samsung: Add SPDX license identifiersKrzysztof Kozlowski11-50/+17
Replace GPL license statements with SPDX license identifiers (GPL-2.0). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
2018-10-05clk: samsung: Remove obsolete code for Exynos4412 ISP clocksMarek Szyprowski1-30/+0
Exynos4412 ISP clock are provided by separate Exynos4412 ISP clock driver, so support for them in Exynos4-clk driver can be removed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
2018-10-05reset: imx7: Add PCIE_CTRL_APPS_TURNOFFLeonard Crestez1-1/+3
This is required for the imx pci driver to send the PME_Turn_Off TLP. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org>
2018-10-05dt-bindings: reset: Add PDC Global binding for SDM845 SoCsSibi Sankar1-0/+20
Add PDC Global (Power Domain Controller) binding for SDM845 SoCs. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-10-03dt-bindings: clock: dra7xx: add clkctrl indices for new data layoutTero Kristo1-68/+258
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03dt-bindings: clock: am43xx: add clkctrl indices for new data layoutTero Kristo1-0/+132
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03dt-bindings: clock: am33xx: add clkctrl indices for new data layoutTero Kristo1-0/+119
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-02dt-bindings: pinctrl: renesas,rzn1-pinctrl: documentationPhil Edworthy1-0/+141
The Renesas RZ/N1 device family PINCTRL node description. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-10-02Merge tag 'actions-arm64-dt-for-4.20' of ↵Arnd Bergmann1-0/+23
git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/dt Actions Semi arm64 based SoC DT for v4.20 This updates SPDX headers for remaining files. For S900 it adds clock, pinctrl, i2c and dma nodes. S900 SPS is added via topic branch (shared with driver). For S700 it adds clock nodes. * tag 'actions-arm64-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions: arm64: dts: actions: s700: Set UART clock references from CMU arm64: dts: actions: s700: Add Clock Management Unit arm64: dts: actions: s900: Add DMA Controller arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2 arm64: dts: actions: s900: Add I2C controller nodes arm64: dts: actions: s900-bubblegum-96: Add gpio line names arm64: dts: actions: s900: Add gpio properties to pinctrl node arm64: dts: actions: s900: Add pinctrl node arm64: dts: actions: s900: Add SPS node arm64: dts: actions: s900: Source CMU clock for UARTs arm64: dts: actions: s900: Add Clock Management Unit nodes dt-bindings: power: Add Actions Semi S900 SPS arm64: dts: actions: Convert to new-style SPDX license identifiers Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02Merge tag 'actions-drivers+s900-sps-for-4.20' of ↵Arnd Bergmann1-0/+23
git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/drivers Actions Semi SoC drivers for v4.20 #2 The SPS power domain driver is extended for S900 SoC. This required merging a topic branch for the new bindings header. * tag 'actions-drivers+s900-sps-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions: soc: actions: sps: Add S900 power domains dt-bindings: power: Add Actions Semi S900 SPS soc: actions: Update SPS help text for S700 soc: actions: Convert to SPDX license identifiers Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-30dt-bindings: power: Add Actions Semi S900 SPSManivannan Sadhasivam1-0/+23
Define power domains for Actions Semi S900 SoC Smart Power System (SPS). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-28Merge tag 'renesas-drivers-for-v4.20' of ↵Arnd Bergmann3-0/+80
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Renesas ARM Based SoC Drivers Updates for v4.20 * Convert to SPDX identifiers * R-Car V3M (r8a77970) and V3H (r8a77980): Document Timer Unit (TMU) bindings * RZ/G1N (r8a7744) and RZ/G1C (r8a77470) SoCs: - Document APMU and SMP enable method * RZ/G2M (r8a74a1), RZ/G1N (r8a7744) and RZ/G2E (r8a774c0) SoCs: - Add reset support - Add sysc support * RZ/G2M (r8a774a1), RZ/G2E (r8a774c0) and RZ/A2M (r7s9210) SoCs: - Add support for identifying SoC * RZ/A2M (r7s9210) SoC: - Add basic SoC setup support * tag 'renesas-drivers-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits) dt-bindings: apmu: Document r8a7744 support dt-bindings: timer: renesas: tmu: document R8A779{7|8}0 bindings dt-bindings: apmu: Document r8a77470 support soc: renesas: rcar-rst: Add support for RZ/G1N dt-bindings: reset: rcar-rst: Document r8a7744 reset module soc: renesas: rcar-sysc: Add r8a7744 support dt-bindings: power: rcar-sysc: Add r8a7744 power domain index macros dt-bindings: power: rcar-sysc: Document r8a7744 SYSC binding soc: renesas: rcar-rst: Add support for RZ/G2E dt-bindings: reset: rcar-rst: Document r8a774c0 rst soc: renesas: rcar-sysc: Add r8a774c0 support dt-bindings: power: rcar-sysc: Document r8a774c0 sysc dt-bindings: power: Add r8a774c0 SYSC power domain definitions soc: renesas: Identify RZ/G2E soc: renesas: convert to SPDX identifiers soc: renesas: rcar-rst: Add support for RZ/G2M soc: renesas: rcar-sysc: Add r8a774a1 support dt-bindings: power: Add r8a774a1 SYSC power domain definitions soc: renesas: identify RZ/A2 ARM: shmobile: Add basic RZ/A2 SoC support ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-20dt-bindings: connector: Add support for USB-PD PPS APDOs to bindingsAdam Thomson1-0/+26
Add support for PPS APDOs to connector bindings so a port controller can specify support for PPS, as per existing FIXED/BATT/VAR PDOs. Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-19clk: renesas: Add r8a774c0 CPG Core Clock DefinitionsFabrizio Castro1-0/+60
Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2g ("List of Clocks [RZ/G2E]") of the RZ/G2 Hardware User's Manual. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19clk: renesas: Add r8a7744 CPG Core Clock DefinitionsBiju Das1-0/+39
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's Manual. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19dt-bindings: clock: renesas: Convert to SPDX identifiersKuninori Morimoto15-93/+30
This patch updates license to use SPDX-License-Identifier instead of verbose license text on Renesas related headers. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-17dt-bindings: power: rcar-sysc: Add r8a7744 power domain index macrosBiju Das1-0/+24
Add power domain indices for RZ/G1N (R8A7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-14dt-bindings: power: Add r8a774c0 SYSC power domain definitionsFabrizio Castro1-0/+25
This patch adds power domain indices for RZ/G2E. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-14Merge tag 'iio-for-4.20a' of ↵Greg Kroah-Hartman1-10/+115
git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next Jonathan writes: 1st round of IIO new device support, features and cleanups in the 4.20 cycle. There is a merge commit in here to pull in regmap support for repeatedly reading the same register (to read out FIFOs). Used by the adxl372 driver. This will find uses elsewhere once we tidy up various drivers that are effectively doing this and relying on not enabling regcache. New device support * Analog devices ADXL372 accelerometer - new driver for this accelerometer including fifo and and interrupt support. Follow up patches enforce trigger validation, add sampling frequency control and filter bandwidth control. A later series added i2c support to the existing SPI support. * ST lsm6dsx - rework and add support fo the LSM6DSO 6 axis mems sensor. * Linear LTC 1660 DAC - new driver supporting the LTC 1660 and LTC 1665 SPI DACs. * Microchip mcp3911 ADC. - new driver for this integrated analog front end and ADC. * Qualcomm SPMI PMIC5 adc driver - using the spmi framework, new driver and bindings for this ADC. Follow up patch adds some missing channels. Features * ad5758 - support hard reset using a gpio (if provided). * mpu6050 - Regulator support * qcom-spmi-adc5 - Sanity check the channel numbers provided by DT to make sure the driver actually knows about them. * sc27xx - give raw data for channel 20 as it's used on all known boards for the headset which needs a custom converstion function. If it turns out someone builds a board where this isn't true we will deal with it when it happens. - add ADC scale calibration. * tsl2772 - support device tree binding to set the proximity led settings. - regulator supprot. - binding for apds9930 - trivial addition as register compatible with tsl2772. Cleanups / Minor fixes * adxl345 - supress a static checker warning but explicitly checking if the id object is null. * bh1750 - avoid CONFIG_PM_SLEEP checks. - SPDX. * bme680 - spelling mistake - use clamp rather than open coding. - white space and other similar fixes. - rename MSK to MASK for clarifty and use GENMASK to specify them. - use the FIELD_GET macro rather than a very odd accessor of dividing by 16 to get the shift. - rework to share handing for oversampling of the various channels in a unified way. - check explicitly for val2 in write_raw function to ensure it is 0. - drop some field defines that don't add anything. * dpot-adc - SPDX * envelope detector - SPDX * isl29501 - fix an ancient compiler warning mostly because it results in much nicer code. * max30102 - mark switch fall throughs. * max44000 - drop an unused variable. * max512 - avoid CONFIG_PM_SLEEP checks. * max5481 - use of_device_get_match_data rather than open coding it. * max5821 - avoid CONFIG_PM_SLEEP checks. * max9611 - explicity cast an enum to an integer to make it totally clear that this is intended. * mcp4018 - fix an inconsistent MODULE_LICENSE. - use of_device_get_match_data rather than open coding it. * mcp4531 - use of_device_get_match_data rather than open coding it. - SPDX * mcp4725 - avoid CONFIG_PM_SLEEP checks. * mcp4922 - Fix error handling and prevent writing a negative to when setting the output voltage. * ms5611 - drop deprecated compatible strings without manufacturer from being explicitly listed. They are handled anyway. - SPDX * multiplexer - SPDX * qcom-vadc - fix inconsistent documentation for reg. * ti-dac5571 - provide and of_match_table. * treewide - update Michael Hennerich's email address. - Use %pOFn rather than device_node.name. * documentation. - tidy up a wrong kernel version for the introduction of the position_relative ABI.
2018-09-12dt-bindings: power: Add r8a774a1 SYSC power domain definitionsBiju Das1-0/+31
This patch adds power domain indices for RZ/G2M. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt1-0/+20
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module Standby. The Module Standby HW in the RZ/A series is very close to R-Car HW, except for how the registers are laid out. The MSTP registers are only 8-bits wide, there are no status registers (MSTPSR), and the register offsets are a little different. Since the RZ/A hardware manuals refer to these registers as the Standby Control Registers, we'll use that name to distinguish the RZ/A type from the R-Car type. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Rob Herring <robh@kernel.org> # DT bits Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-10dt-bindings: Add binding for atmel-usart in SPI modeRadu Pirea1-0/+17
This patch moves the bindings for serial from serial/atmel-usart.txt to mfd/atmel-usart.txt and adds bindings for USART in SPI mode. Signed-off-by: Radu Pirea <radu.pirea@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-09-05dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macroJagan Teki1-0/+1
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent. Include the macro on dt-bindings so-that the same can be used while defining CCU clock phandles. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-31dt-bindings: clock: Introduce QCOM Camera clock bindingsAmit Nischal1-0/+116
Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-29pinctrl: Add compatibles for Amlogic Meson G12A pin controllersYixun Lan1-0/+114
Add new compatible name for Amlogic's Meson-G12A pin controllers, add a dt-binding header file which document the detail pin names. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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