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2020-10-24Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+14
Pull ARM Devicetree updates from Olof Johansson: "As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits) ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users arm64: dts: lg: Fix SP805 clocks ARM: mstar: Fix up the fallout from moving the dts/dtsi files ARM: mstar: Add mstar prefix to all of the dtsi/dts files ARM: mstar: Add interrupt to pm_uart ARM: mstar: Add interrupt controller to base dtsi ARM: dts: meson8: remove two invalid interrupt lines from the GPU node arm64: dts: ti: k3-j7200-common-proc-board: Add USB support arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function arm64: dts: ti: k3-j7200-main: Add USB controller arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC ARM: dts: hisilicon: add SD5203 dts ARM: dts: hisilicon: fix the system controller compatible nodes arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 arm64: dts: zynqmp: Remove undocumented u-boot properties arm64: dts: zynqmp: Remove additional compatible string for i2c IPs arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml ...
2020-10-20Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', ↵Stephen Boyd7-2/+165
'clk-qcom', 'clk-prima2' and 'clk-bcm' into clk-next - Support qcom SM8150/SM8250 video and display clks - Change how qcom's display port clks work * clk-ingenic: clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL clk: ingenic: Use readl_poll_timeout instead of custom loop clk: ingenic: Use to_clk_info() macro for all clocks * clk-at91: clk: at91: sam9x60: support only two programmable clocks clk: at91: clk-sam9x60-pll: remove unused variable clk: at91: clk-main: update key before writing AT91_CKGR_MOR clk: at91: remove the checking of parent_name * clk-kconfig: clk: Restrict CLK_HSDK to ARC_SOC_HSDK * clk-imx: clk: imx8mq: Fix usdhc parents order clk: imx: imx21: Remove clock driver clk: imx: gate2: Fix a few typos clk: imx: Fix and update kerneldoc clk: imx: fix i.MX7D peripheral clk mux flags clk: imx: fix composite peripheral flags clk: imx: Correct the memrepair clock on imx8mp clk: imx: Correct the root clk of media ldb on imx8mp clk: imx: vf610: Add CRC clock clk: imx: Explicitly include bits.h clk: imx8qxp: Support building i.MX8QXP clock driver as module clk: imx8m: Support module build clk: imx: Add clock configuration for ARMv7 platforms clk: imx: Support building i.MX common clock driver as module clk: composite: Export clk_hw_register_composite() clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits * clk-qcom: clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on clk: qcom: Add display clock controller driver for SM8150 and SM8250 dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings clk: qcom: add video clock controller driver for SM8250 clk: qcom: add video clock controller driver for SM8150 dt-bindings: clock: add SM8250 QCOM video clock bindings dt-bindings: clock: add SM8150 QCOM video clock bindings dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs clk/qcom: fix spelling typo clk: qcom: gcc-sdm660: Fix wrong parent_map clk: qcom: dispcc: Update DP clk ops for phy design clk: qcom: gcc-msm8939: remove defined but not used variables clk: qcom: ipq8074: make pcie0_rchng_clk_src static * clk-prima2: clk: clk-prima2: fix return value check in prima2_clk_init() * clk-bcm: clk: bcm2835: add missing release if devm_clk_hw_register fails clk: bcm: rpi: Add register to control pixel bvb clk
2020-10-20Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and ↵Stephen Boyd2-0/+132
'clk-mediatek' into clk-next - Small non-critical fixes for TI clk driver - Support Mediatek MT8167 clks * clk-simplify: clk: mediatek: fix platform_no_drv_owner.cocci warnings clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init * clk-ti: clk: ti: dra7: add missing clkctrl register for SHA2 instance clk: ti: clockdomain: fix static checker warning clk: ti: autoidle: add checks against NULL pointer reference clk: keystone: sci-clk: add 10% slack to set_rate clk: keystone: sci-clk: cache results of last query rate operation clk: keystone: sci-clk: fix parsing assigned-clock data during probe * clk-tegra: clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate() * clk-rockchip: clk: rockchip: Initialize hw to error to avoid undefined behavior clk: rockchip: rk3399: Support module build clk: rockchip: fix the clk config to support module build clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: rk3308: drop unused mux_timer_src_p * clk-mediatek: clk: mediatek: Add MT8167 clock support dt-bindings: clock: mediatek: add bindings for MT8167 clocks clk: mediatek: add UART0 clock support
2020-10-20Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner', 'clk-samsung', ↵Stephen Boyd4-1/+148
'clk-doc' and 'clk-unused' into clk-next - Remove various unused variables in clk drivers * clk-renesas: clk: renesas: rcar-gen3: Update description for RZ/G2 clk: renesas: cpg-mssr: Add support for R-Car V3U clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0 dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions dt-bindings: power: Add r8a779a0 SYSC power domain definitions clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) clk: renesas: r8a7742: Add clk entry for VSPR * clk-amlogic: clk: meson: make shipped controller configurable clk: meson: g12a: mark fclk_div2 as critical clk: meson: axg-audio: fix g12a tdmout sclk inverter clk: meson: axg-audio: separate axg and g12a regmap tables clk: meson: add sclk-ws driver * clk-allwinner: clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL clk: sunxi-ng: add support for the Allwinner A100 CCU dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU * clk-samsung: clk: s2mps11: initialize driver via module_platform_driver clk: samsung: Use cached clk_hws instead of __clk_lookup() calls clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions clk: samsung: Add clk ID definitions for the CPU parent clocks clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d clk: samsung: Keep top BPLL mux on Exynos542x enabled * clk-doc: clk: davinci: add missing kerneldoc clk: fixed: add missing kerneldoc * clk-unused: clk: socfpga: agilex: Remove unused variable 'cntr_mux' clk: si5341: drop unused 'err' variable clk: mmp: pxa1928: drop unused 'clk' variable clk: at91: drop unused at91sam9g45_pcr_layout
2020-10-14dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindingsJonathan Marek2-0/+67
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8150 and SM8250 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-2-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14dt-bindings: clock: add SM8250 QCOM video clock bindingsJonathan Marek1-0/+34
Add device tree bindings for video clock controller for SM8250 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200923160635.28370-4-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14dt-bindings: clock: add SM8150 QCOM video clock bindingsJonathan Marek1-0/+25
Add device tree bindings for video clock controller for SM8150 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200923160635.28370-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCsKonrad Dybcio1-0/+36
This change adds GDSCs, resets and most of the missing clocks to the msm8994 GCC driver. The remaining ones are of local_vote_clk and gate_clk type, which are not yet supported upstream. Also reorder them to match the original downstream driver. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20201005145855.149206-1-konradybcio@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14dt-bindings: clock: mediatek: add bindings for MT8167 clocksFabien Parent1-0/+131
Add binding documentation for topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys on MT8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200918132303.2831815-1-fparent@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-26Merge tag 'tegra-for-5.10-arm64-dt' of ↵Olof Johansson1-0/+14
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Changes for v5.10-rc1 This set of changes fixes some minor issues in existing device trees and adds ID EEPROMs on the Jetson Xavier NX. All ID EEPROMs are now labelled to allow them to be detected by software. It also adds support for the Tegra234 VDK board, which is a pre-silicon platform for the upcoming Orin SoC. * tag 'tegra-for-5.10-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Initial Tegra234 VDK support arm64: tegra: Populate EEPROMs for Jetson Xavier NX arm64: tegra: Add label properties for EEPROMs arm64: tegra: Add DT binding for AHUB components arm64: tegra: Enable ACONNECT, ADMA and AGIC on Jetson Nano arm64: tegra: Properly size register regions for GPU on Tegra194 arm64: tegra: Use valid PWM period for VDD_GPU on Tegra210 arm64: tegra: Describe display controller outputs for Tegra210 arm64: tegra: Disable SD card write-protection on Jetson Nano arm64: tegra: Add VBUS supply for micro USB port on Jetson Nano arm64: tegra: Wire up pinctrl states for all DPAUX controllers arm64: tegra: Add ID EEPROMs on Jetson AGX Xavier Link: https://lore.kernel.org/r/20200918150303.3938852-5-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-22clk: ti: dra7: add missing clkctrl register for SHA2 instanceTero Kristo1-0/+1
DRA7 SoC has two SHA instances. Add the clkctrl entry for the second one. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907082600.454-4-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-18arm64: tegra: Initial Tegra234 VDK supportThierry Reding1-0/+14
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-17clk: samsung: Add clk ID definitions for the CPU parent clocksSylwester Nawrocki2-1/+8
Add clock ID definitions for the CPU parent clocks for SoCs which don't have such definitions yet. This will allow us to reference the parent clocks directly by cached struct clk_hw pointers in the clock provider, rather than doing clk lookup by name. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200826171529.23618-1-s.nawrocki@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-09-17clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3dSylwester Nawrocki1-0/+1
This patch adds ID for the mout_sw_aclk_g3d (SW_CLKMUX_ACLK_G3D) clock, mostly for internal use in the CMU driver. It will allow to avoid the __clk_lookup() call when setting up the clock during the clock provider initialization. Link: https://lore.kernel.org/r/20200811151251.31613-1-s.nawrocki@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-09-10dt-bindings: clock: Add r8a779a0 CPG Core Clock DefinitionsYoshihiro Shimoda1-0/+55
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V3U (R8A779A0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599657211-17504-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-08-31clk: imx: Correct the root clk of media ldb on imx8mpJacky Bai1-1/+1
The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref, so correct it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-25clk: sunxi-ng: add support for the Allwinner A100 CCUYangtao Li2-0/+139
Add support for a100 in the sunxi-ng CCU framework. Signed-off-by: Yangtao Li <frank@allwinnertech.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1eb41bf6c966a0e54820200650d27a5d4f2ac160.1595572867.git.frank@allwinnertech.com
2020-08-23clk: imx: vf610: Add CRC clockKrzysztof Kozlowski1-1/+2
Add the clock for CRC block allowing it to be enabled by consumers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-12Merge tag 'clk-for-linus' of ↵Linus Torvalds9-72/+181
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: "Here's some more updates that missed the last pull request because I happened to tag the tree at an earlier point in the history of clk-next. I must have fat fingered it and checked out an older version of clk-next on this second computer I'm using. This time it actually includes more code for Qualcomm SoCs, the AT91 major updates, and some Rockchip SoC clk driver updates as well. I've corrected this flow so this shouldn't happen again" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs clk: drop unused function __clk_get_flags clk: hsdk: Fix bad dependency on IOMEM dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: mmp: avoid missing prototype warning clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file clk: qoriq: add LS1021A core pll mux options clk: clk-atlas6: fix return value check in atlas6_clk_init() clk: tegra: pll: Improve PLLM enable-state detection clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset ...
2020-08-07Merge tag 'clk-for-linus' of ↵Linus Torvalds12-1/+220
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "It looks like a smaller batch of clk updates this time around. In the core framework we just have some minor tweaks and a debugfs feature, so not much to see there. The driver updates are fairly well split between AT91 and Qualcomm clk support. Adding those two drivers together equals about 50% of the diffstat. Otherwise, the big amount of work this time was on supporting Broadcom's Raspberry Pi firmware clks. Highlights: Core: - Document clk_hw_round_rate() so it gets some more use - Remove unused __clk_get_flags() - Add a prepare/enable debugfs feature similar to rate setting New Drivers: - Add support for SAMA7G5 SoC clks - Enable CPU clks on Qualcomm IPQ6018 SoCs - Enable CPU clks on Qualcomm MSM8996 SoCs - GPU clk support for Qualcomm SM8150 and SM8250 SoCs - Audio clks on Qualcomm SC7180 SoCs - Microchip Sparx5 DPLL clk - Add support for the new Renesas RZ/G2H (R8A774E1) SoC Updates: - Make defines for bcm63xx-gate clks to use in DT - Support BCM2711 SoC firmware clks - Add HDMI clks for BCM2711 SoCs - Add RTC related clks on Ingenic SoCs - Support USB PHY clks on Ingenic SoCs - Support gate clks on BCM6318 SoCs - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs - Use poll_timeout functions in Rockchip clk driver - Support Rockchip rk3288w SoC variant - Mark mac_lbtest critical on Rockchip rk3188 - Add CAAM clock support for i.MX vf610 driver - Add MU root clock support for i.MX imx8mp driver - Amlogic g12: add neural network accelerator clock sources - Amlogic meson8: remove critical flag for main PLL divider - Amlogic meson8: add video decoder clock gates - Convert one more Renesas DT binding to json-schema - Enhance critical clock handling on Renesas platforms to only consider clocks that were enabled at boot time" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (79 commits) clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845 ipq806x: gcc: add support for child probe clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static clk: qcom: ipq8074: Add correct index for PCIe clocks clk: <linux/clk-provider.h>: drop a duplicated word clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: Drop duplicate selection in Kconfig clk: qcom: smd: Add support for MSM8992/4 rpm clocks clk: qcom: ipq8074: Add missing clocks for pcie dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe Replace HTTP links with HTTPS ones: Common CLK framework clk: qcom: Add CPU clock driver for msm8996 dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996 soc: qcom: Separate kryo l2 accessors from PMU driver clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: qcom: Fix return value check in apss_ipq6018_probe() clk: bcm: dvp: Add missing module informations clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 ...
2020-08-05Merge tag 'timers-core-2020-08-04' of ↵Linus Torvalds1-0/+12
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer updates from Thomas Gleixner: "Time, timers and related driver updates: - Prevent unnecessary timer softirq invocations by extending the tracking of the next expiring timer in the timer wheel beyond the existing NOHZ functionality. The tracking overhead at enqueue time is within the noise, but on sensitive workloads the avoidance of the soft interrupt invocation is a measurable improvement. - The obligatory new clocksource driver for Ingenic X100 OST - The usual fixes, improvements, cleanups and extensions for newer chip variants all over the driver space" * tag 'timers-core-2020-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (28 commits) timers: Recalculate next timer interrupt only when necessary clocksource/drivers/ingenic: Add support for the Ingenic X1000 OST. dt-bindings: timer: Add Ingenic X1000 OST bindings. clocksource/drivers: Replace HTTP links with HTTPS ones clocksource/drivers/nomadik-mtu: Handle 32kHz clock clocksource/drivers/sh_cmt: Use "kHz" for kilohertz clocksource/drivers/imx: Add support for i.MX TPM driver with ARM64 clocksource/drivers/ingenic: Add high resolution timer support for SMP/SMT. timers: Lower base clock forwarding threshold timers: Remove must_forward_clk timers: Spare timer softirq until next expiry timers: Expand clk forward logic beyond nohz timers: Reuse next expiry cache after nohz exit timers: Always keep track of next expiry timers: Optimize _next_timer_interrupt() level iteration timers: Add comments about calc_index() ceiling work timers: Move trigger_dyntick_cpu() to enqueue_timer() timers: Use only bucket expiry for base->next_expiry value timers: Preserve higher bits of expiration on index calculation clocksource/drivers/timer-atmel-tcb: Add sama5d2 support ...
2020-08-04Merge tag 'arm-newsoc-5.9' of ↵Linus Torvalds1-0/+23
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new ARM SoC support from Arnd Bergmann: "There are three SoC families newly dded to the 32-bit and 64-bit Arm architecture code in the kernel this time: - Daniel Palmer adds initial support for two chips made by MStar, a taiwanese SoC manufacturer that became part of Mediatek in 2012. For now, the added support is fairly minimal, with just two of its Cortex-A7 based 32-bit camera chips getting support for a limited set of on-chip peripherals. - Lars Povlsen from Microchip adds support for their new Sparx5 family of ethernet switch chips using 64-bit Cortex-A53 cores. These are descended from earlier VSC7xxx SparX and Ocelot chips using 32-bit MIPS cores. - Daniele Alessandrelli from Intel adds support for the new Keem Bay SoC for computer vision, built around a Movidius VPU with Linux running on Arm Cortex-A53 cores" * tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) ARM: mstar: Correct the compatible string for pmsleep dt-bindings: arm: mstar: remove the binding description for mstar,pmsleep dt-bindings: mfd: syscon: add compatible string for mstar,msc313-pmsleep ARM: mstar: Add reboot support ARM: mstar: Add "pmsleep" node to base dtsi ARM: mstar: Add PMU ARM: mstar: Adjust IMI size for infinity3 ARM: mstar: Adjust IMI size for mercury5 ARM: mstar: Adjust IMI size of infinity ARM: mstar: Add IMI SRAM region dt-bindings: arm: mstar: Move existing MStar binding descriptions dt-bindings: arm: mstar: Add binding details for mstar, pmsleep ARM: mstar: Fix dts filename for 70mai midrive d08 ARM: mstar: Add dts for 70mai midrive d08 ARM: mstar: Add dts for msc313(e) based BreadBee boards ARM: mstar: Add mercury5 series dtsis ARM: mstar: Add infinity/infinity3 family dtsis ARM: mstar: Add Armv7 base dtsi ARM: mstar: Add binding details for mstar,l3bridge ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs ...
2020-08-04Merge branches 'clk-microchip', 'clk-mmp', 'clk-unused' and 'clk-at91' into ↵Stephen Boyd1-0/+23
clk-next - Add support for SAMA7G5 SoC clks - Microchip Sparx5 DPLL clk * clk-microchip: clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file * clk-mmp: clk: mmp: avoid missing prototype warning * clk-unused: clk: drop unused function __clk_get_flags * clk-at91: clk: at91: sama7g5: add clock support for sama7g5 clk: at91: clk-utmi: add utmi support for sama7g5 clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs clk: at91: add macro for pll ids mask clk: at91: clk-programmable: add mux_table option clk: at91: clk-peripheral: add support for changeable parent rate clk: at91: clk-master: add master clock support for SAMA7G5 clk: at91: clk-generated: add mux_table option clk: at91: clk-generated: pass the id of changeable parent at registration clk: at91: replace conditional operator with double logical not clk: at91: sckc: register slow_rc with accuracy option clk: at91: sam9x60: fix main rc oscillator frequency clk: at91: sam9x60-pll: use frac when setting frequency clk: at91: sam9x60-pll: check fcore against ranges clk: at91: sam9x60-pll: use logical or for range check clk: at91: clk-sam9x60-pll: fix mul mask clk: at91: clk-generated: check best_rate against ranges clk: at91: clk-generated: continue if __clk_determine_rate() returns error clk: at91: fix possible dead lock in new drivers
2020-08-04Merge branches 'clk-fallthru', 'clk-ingenic', 'clk-tegra', 'clk-sirf' and ↵Stephen Boyd3-71/+77
'clk-qoriq' into clk-next - Add RTC related clks on Ingenic SoCs - Support USB PHY clks on Ingenic SoCs * clk-fallthru: clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword * clk-ingenic: clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. * clk-tegra: clk: tegra: pll: Improve PLLM enable-state detection * clk-sirf: clk: clk-atlas6: fix return value check in atlas6_clk_init() * clk-qoriq: clk: qoriq: add LS1021A core pll mux options
2020-08-04Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and ↵Stephen Boyd1-1/+6
'clk-debugfs' into clk-next - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs * clk-actions: MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs clk: actions: Add Actions S500 SoC Reset Management Unit support dt-bindings: reset: Add binding constants for Actions S500 RMU clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC clk: actions: Fix h_clk for Actions S500 SoC * clk-rockchip: clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" clk: rockchip: use separate compatibles for rk3288w-cru dt-bindings: clocks: add rk3288w variant compatible clk: rockchip: Handle clock tree for rk3288w variant clk: rockchip: convert rk3036 pll type to use internal lock status clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout * clk-iproc: clk: iproc: round clock rate to the closest * clk-intel: clk: intel: Avoid unnecessary memset by improving code clk: intel: Improve locking in the driver clk: intel: Use devm_clk_hw_register() instead of clk_hw_register() * clk-debugfs: clk: Add support for enabling/disabling clocks from debugfs
2020-08-04Merge branches 'clk-https', 'clk-renesas', 'clk-kconfig', 'clk-amlogic' and ↵Stephen Boyd3-1/+63
'clk-imx' into clk-next * clk-https: Replace HTTP links with HTTPS ones: Common CLK framework * clk-renesas: clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: renesas: Add r8a774e1 CPG Core Clock Definitions dt-bindings: power: Add r8a774e1 SYSC power domain definitions clk: renesas: rzg2: Mark RWDT clocks as critical clk: renesas: rcar-gen3: Mark RWDT clocks as critical clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot dt-bindings: clock: renesas: cpg: Convert to json-schema * clk-kconfig: clk: hsdk: Fix bad dependency on IOMEM clk: Specify IOMEM dependency for HSDK pll driver clk: Drop duplicate selection in Kconfig clk: AST2600: Add mux for EMMC clock clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER * clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs * clk-imx: clk: imx: vf610: add CAAM clock clk: imx8mp: add mu root clk
2020-08-04Merge branches 'clk-socfpga', 'clk-doc', 'clk-qcom', 'clk-vc5' and 'clk-bcm' ↵Stephen Boyd15-0/+313
into clk-next - Enable CPU clks on Qualcomm IPQ6018 SoCs - Enable CPU clks on Qualcomm MSM8996 SoCs - GPU clk support for Qualcomm SM8150 and SM8250 SoCs - Audio clks on Qualcomm SC7180 SoCs - Make defines for bcm63xx-gate clks to use in DT - Support gate clks on BCM6318 SoCs - Add HDMI clks for BCM2711 SoCs - Support BCM2711 SoC firmware clks * clk-socfpga: clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK * clk-doc: clk: Clean up kernel-doc errors clk: <linux/clk-provider.h>: drop a duplicated word clk: add function documentation for clk_hw_round_rate() * clk-qcom: (38 commits) dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset clk: qcom: lpass: Add support for LPASS clock controller for SC7180 clk: qcom: gcc: Add support for GCC LPASS clock for SC7180 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180 clk: qcom: gdsc: Add support to enable retention of GSDCR clk: qcom: Export gdsc_gx_do_nothing_enable() to modules clk: qcom: Add graphics clock controller driver for SM8250 clk: qcom: Add graphics clock controller driver for SM8150 clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers dt-bindings: clock: add SM8250 QCOM Graphics clock bindings dt-bindings: clock: add SM8150 QCOM Graphics clock bindings dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc clk: qcom: gcc: remove unnecessary vco_table from SM8150 clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL clk: qcom: gcc: fix sm8150 GPU and NPU clocks dt-bindings: clock: Fix qcom,msm8996-apcc yaml syntax ... * clk-vc5: clk: vc5: use a dedicated struct to describe the output drivers dt-bindings: clk: versaclock5: convert to yaml MAINTAINERS: take over IDT VersaClock 5 clock driver dt-bindings: clk: versaclock5: fix 'idt' prefix typos clk: vc5: Add memory check to prevent oops clk: vc5: fix use of memory after it has been kfree'd clk: vc5: Enable addition output configurations of the Versaclock dt: Add additional option bindings for IDT VersaClock clk: vc5: Allow Versaclock driver to support multiple instances * clk-bcm: (44 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs dt-bindings: arm: bcm: Add a select to the RPI Firmware binding clk: bcm: dvp: Add missing module informations clk: bcm: rpi: Remove the quirks for the CPU clock clk: bcm2835: Don't cache the PLLB rate clk: bcm2835: Allow custom CCF flags for the PLLs Revert "clk: bcm2835: remove pllb" clk: bcm: rpi: Give firmware clocks a name clk: bcm: rpi: Discover the firmware clocks clk: bcm: rpi: Add an enum for the firmware clocks clk: bcm: rpi: Add DT provider for the clocks clk: bcm: rpi: Make the PLLB registration function return a clk_hw clk: bcm: rpi: Split pllb clock hooks clk: bcm: rpi: Rename is_prepared function clk: bcm: rpi: Pass the clocks data to the firmware function clk: bcm: rpi: Add clock id to data clk: bcm: rpi: Create a data structure for the clocks clk: bcm: rpi: Use CCF boundaries instead of rolling our own clk: bcm: rpi: Make sure the clkdev lookup is removed clk: bcm: rpi: Switch to clk_hw_register_clkdev ...
2020-07-29dt-bindings: clock: sparx5: Add bindings include fileLars Povlsen1-0/+23
The Sparx5 support 9 different clock outputs. This include file has defines for each supported clock ordinal. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200727084211.6632-8-lars.povlsen@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-28dt-bindings: clock: Add tabs to align code.周琰杰 (Zhou Yanjie)1-72/+72
The "JZ4780_CLK_LCD0PIXCLK" and the "JZ4780_CLK_LCD1PIXCLK" in the "jz4780.h" and the new added "JZ4780_CLK_EXCLK_DIV512" in the previous patch is too long, add tabs to other lines to align them. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200725051136.58220-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-28dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)3-0/+6
Add RTC related clocks bindings for the JZ4780 SoC, the X1000 SoC, and the X1830 SoC from Ingenic. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200725051136.58220-2-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-28clk: qcom: gcc-sdm660: Add missing modem resetKonrad Dybcio1-0/+1
This will be required in order to support the modem upstream. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200726111215.22361-2-konradybcio@gmail.com Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180Taniya Das2-0/+30
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1595606878-2664-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24dt-bindings: clock: add SM8250 QCOM Graphics clock bindingsJonathan Marek1-0/+34
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8250 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-9-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24dt-bindings: clock: add SM8150 QCOM Graphics clock bindingsJonathan Marek1-0/+33
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8150 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-8-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-23Merge tag 'timers-v5.9' of ↵Thomas Gleixner1-0/+12
https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clock event/surce driver changes from Daniel Lezcano: - Add sama5d2 support and rework the 32kHz clock handling (Alexandre Belloni) - Add the high resolution support for SMP/SMT on the Ingenic timer (Zhou Yanjie) - Add support for i.MX TPM driver with ARM64 (Anson Huang) - Fix typo by replacing KHz to kHz (Geert Uytterhoeven) - Add 32kHz support by setting the minimum ticks to 5 on Nomadik MTU (Linus Walleij) - Replace HTTP links with HTTPS ones for security reasons (Alexander A. Klimov) - Add support for the Ingenic X1000 OST (Zhou Yanjie)
2020-07-23dt-bindings: timer: Add Ingenic X1000 OST bindings.周琰杰 (Zhou Yanjie)1-0/+12
Add the OST bindings for the X1000 SoC from Ingenic. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200722171804.97559-2-zhouyanjie@wanyeetech.com
2020-07-22dt-bindings: clock: sparx5: Add bindings include fileLars Povlsen1-0/+23
The Sparx5 support 9 different clock outputs. This include file has defines for each supported clock ordinal. Link: https://lore.kernel.org/r/20200615133242.24911-8-lars.povlsen@microchip.com Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22Merge tag 'imx-dt-5.9' of ↵Arnd Bergmann1-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX device tree update for 5.9: - New board support: Protonic PRTI6Q/WD2/VT7/RVT and MYiR MYS-6ULX SBC. - Update IIM, OCOTP and SD/MMC device node name to match .yaml bindings. - Make tempmon node as child of anatop node according to hardware architecture. - The vf610-zii device update: configure fiber port to 1000BaseX, add switch watchdog, MDIO speed and preamble. - A series from Fabio Estevam to update imx6qdl-sabresd and imx6q-tbs2910 for using MDIO node and reset-assert-us. - Align L2 cache-controller device node name with .yaml schema. - Enable SATA support for imx6qp-sabreauto and imx6qp-sabresd board. - A series of patches from Shengjiu Wang to enable various audio support on i.MX6 devices. - Add Gateworks System Controller support for imx6qdl-gw devices. - Change default #pwm-cells setting to <3> in the SoC dtsi files. - Other small random changes. * tag 'imx-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (43 commits) ARM: dts: vf610-zii-ssmb-spu3: Add node for switch watchdog ARM: dts: vf610-zii-ssmb-dtu: Add no-sdio/no-sd properties ARM: dts: imx6q-tbs2910: Pass reset-assert-us ARM: dts: imx6q-tbs2910: Add an mdio node ARM: dts: imx6qdl-sabresd: Pass reset-assert-us ARM: dts: imx6qdl-sabresd: Add an mdio node ARM: dts: imx6qdl-gw: add Gateworks System Controller support ARM: dts: imx6ull: add MYiR MYS-6ULX SBC ARM: dts: vf610-zii-spb4: Add node for switch watchdog ARM: dts: colibri-imx6: remove pinctrl-names orphan ARM: dts: imx: default to #pwm-cells = <3> in the SoC dtsi files ARM: dts: vf610-zii-scu4-aib: Configure fibre ports to 1000BaseX ARM: dts: vf610-zii-dev-rev-c: Configure fiber port to 1000BaseX ARM: dts: ZII: update MDIO speed and preamble ARM: dts: vfxxx: Add node for CAAM ARM: dts: imx6qp-sabresd: enable sata ARM: dts: imx6qp-sabreauto: enable sata ARM: dts: add Protonic RVT board ARM: dts: add Protonic VT7 board ARM: dts: add Protonic WD2 board ... Link: https://lore.kernel.org/r/20200720085536.24138-3-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-21dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoCCristian Ciocaltea1-1/+6
Add the missing APB, DMAC and GPIO clock bindings constants for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Link: https://lore.kernel.org/r/67112af4f5bc0cc5e70ce8410feb369cc72972b8.1593788312.git.cristian.ciocaltea@gmail.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-21Merge branch 'clk-imx' into clk-nextStephen Boyd1-1/+2
* clk-imx: clk: imx: vf610: add CAAM clock clk: imx8mp: add mu root clk
2020-07-21Merge branch 'clk-amlogic' into clk-nextStephen Boyd1-0/+2
* clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
2020-07-21Merge branch 'clk-renesas' into clk-nextStephen Boyd1-0/+59
* clk-renesas: clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: renesas: Add r8a774e1 CPG Core Clock Definitions dt-bindings: power: Add r8a774e1 SYSC power domain definitions
2020-07-21Merge branch 'clk-qcom' into clk-nextStephen Boyd1-3/+3
* clk-qcom: clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845 ipq806x: gcc: add support for child probe clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static clk: qcom: ipq8074: Add correct index for PCIe clocks
2020-07-21clk: qcom: ipq8074: Add correct index for PCIe clocksSivaprakash Murugesan1-3/+3
The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC, GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group. Move them to the gcc clock group. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1594877570-9280-1-git-send-email-sivaprak@codeaurora.org Fixes: e7fb524cfcca ("dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-13clk: renesas: Add r8a774e1 CPG Core Clock DefinitionsMarian-Cristian Rotariu1-0/+59
Add all RZ/G2H Clock Pulse Generator Core Clock Outputs, as listed in Table 11.2 ("List of Clocks [RZ/G2H]") of the RZ/G2H Hardware User's Manual. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594138692-16816-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-07-11Merge branch 'clk-qcom' into clk-nextStephen Boyd2-0/+8
* clk-qcom: clk: qcom: smd: Add support for MSM8992/4 rpm clocks clk: qcom: ipq8074: Add missing clocks for pcie dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
2020-07-11clk: qcom: smd: Add support for MSM8992/4 rpm clocksKonrad Dybcio1-0/+4
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992, MSM8994 (and APQ variants) for clients to vote on. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623230018.303776-1-konradybcio@gmail.com [sboyd@kernel.org: Fixed up binding numbers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIeSivaprakash Murugesan1-0/+4
Add missing clock bindings for PCIe port0 of ipq8074. Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1593940680-2363-4-git-send-email-sivaprak@codeaurora.org [sboyd@kernel.org: Clean up commit text subject] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-26Merge branch 'clk-bcm' into clk-nextStephen Boyd7-0/+183
- Make defines for bcm63xx-gate clks to use in DT - Support gate clks on BCM6318 SoCs - Add HDMI clks for BCM2711 SoCs - Support BCM2711 SoC firmware clks * clk-bcm: (42 commits) clk: bcm: dvp: Add missing module informations clk: bcm: rpi: Remove the quirks for the CPU clock clk: bcm2835: Don't cache the PLLB rate clk: bcm2835: Allow custom CCF flags for the PLLs Revert "clk: bcm2835: remove pllb" clk: bcm: rpi: Give firmware clocks a name clk: bcm: rpi: Discover the firmware clocks clk: bcm: rpi: Add an enum for the firmware clocks clk: bcm: rpi: Add DT provider for the clocks clk: bcm: rpi: Make the PLLB registration function return a clk_hw clk: bcm: rpi: Split pllb clock hooks clk: bcm: rpi: Rename is_prepared function clk: bcm: rpi: Pass the clocks data to the firmware function clk: bcm: rpi: Add clock id to data clk: bcm: rpi: Create a data structure for the clocks clk: bcm: rpi: Use CCF boundaries instead of rolling our own clk: bcm: rpi: Make sure the clkdev lookup is removed clk: bcm: rpi: Switch to clk_hw_register_clkdev clk: bcm: rpi: Remove pllb_arm_lookup global pointer clk: bcm: rpi: Make sure pllb_arm is removed ...
2020-06-23clk: imx: vf610: add CAAM clockAndrey Smirnov1-1/+2
According to Vybrid Security RM, CCM_CCGR11[CG176] can be used to gate CAAM ipg clock. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-imx@nxp.com Tested-by: Chris Healy <cphealy@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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