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2007-10-12[MIPS] R1: Fix hazard barriers to make kernels work on R2 also.Ralf Baechle1-1/+53
2007-10-12[MIPS] Kill num_online_cpus() loops.Ralf Baechle1-2/+2
2007-10-12[MIPS] SMP: Implement smp_call_function_mask().Ralf Baechle1-0/+9
2007-10-12[MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle1-0/+3
2007-10-12[MIPS] Convert list of CPU types from #define to enum.Ralf Baechle1-70/+49
2007-10-12[MIPS] Optimize get_unaligned / put_unaligned implementations.Ralf Baechle1-6/+21
2007-10-12[MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle67-1726/+1726
2007-10-12[MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle26-467/+467
2007-10-12[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle1-1/+4
2007-10-12[MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.cYoichi Yuasa1-7/+0
2007-10-12[MIPS] Cobalt: Move UART base definition to arch/mips/cobalt/console.cYoichi Yuasa1-2/+0
2007-10-12[MIPS] Cobalt: Move PCI definitions to arch/mips/pci/fixup-cobalt.c.Yoichi Yuasa1-24/+2
2007-10-12[MIPS] Optimize __alloc_zeroed_user_highpage implementation.Ralf Baechle1-1/+1
2007-10-12[MIPS] i8253 PIT clocksource and clockevent driversRalf Baechle1-0/+30
2007-10-12[MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle3-6/+8
2007-10-12[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.Ralf Baechle1-8/+8
2007-10-12[MIPS] Switch from to_tm to rtc_time_to_tmRalf Baechle1-7/+0
2007-10-12[MIPS] Deforest the function pointer jungle in the time code.Ralf Baechle2-10/+4
2007-10-12[MIPS] ARC: Get rid of mips_machgroupRalf Baechle1-27/+3
2007-10-12[MIPS] Split up war.hRalf Baechle24-97/+625
2007-10-12[MIPS] Add gpio support to the BCM47XX platformAurelien Jarno1-0/+59
2007-10-12[MIPS] Move ARC code into arch/mips/fw/arcAurelien Jarno4-4/+4
2007-10-12[MIPS] Move CFE code into arch/mips/fw/cfeAurelien Jarno2-0/+270
2007-10-12[MIPS] Remove IP27 specific structures from struct cpuinfo_mipsRalf Baechle3-21/+21
2007-10-12[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle4-22/+19
2007-10-12[MIPS] Add GT641xx IRQ routines.Yoichi Yuasa3-26/+118
2007-10-12[MIPS] GT64120: Remove unused definitionsYoichi Yuasa2-10/+0
2007-10-12[MIPS] i8295 cleanups.Yoichi Yuasa2-10/+2
2007-10-12[MIPS] Define known MIPS ISA overrides for Sibyte and Excite boards.Thiemo Seufer2-1/+11
2007-10-12[MIPS] floppy: Rewrite fd_cacheflush() to use dma_cache_sync().Ralf Baechle1-1/+3
2007-10-12[MIPS] PCI: Always enable CONFIG_PCI_DOMAINSRalf Baechle1-4/+0
2007-10-12[MIPS] tx4927: Cleanup unused macros and non-standard IO accessors.Atsushi Nemoto3-4622/+2
2007-10-12[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno3-2/+43
2007-10-12[MIPS] JAZZ fixesThomas Bogendoerfer3-30/+21
2007-10-12[MIPS] Add back support for LASAT platformsBrian Murphy10-0/+697
2007-10-12[MIPS] fix ABI check in include/asm-mips/arv/hinv.hYoichi Yuasa1-1/+2
2007-10-12[MIPS] remove unused include/asm-mips/ip32/machine.hYoichi Yuasa1-20/+0
2007-10-12[MIPS] Rename CONFIG_BUILD_ELF64 into KBUILD_64BIT_SYM32Franck Bui-Huu3-8/+8
2007-10-12[MIPS] Automatically set CONFIG_BUILD_ELF64Franck Bui-Huu1-1/+1
2007-10-12[MIPS] IRQ Affinity Support for SMTC on Malta PlatformKevin D. Kissell2-2/+66
2007-10-03[MIPS] Terminally fix local_{dec,sub}_if_positiveRalf Baechle1-68/+0
2007-10-03[MIPS] Type proof reimplementation of cmpxchg.Ralf Baechle3-260/+109
2007-10-01[MIPS] Fix value of O_TRUNCRalf Baechle1-0/+1
2007-09-28[MIPS] Fix CONFIG_BUILD_ELF64 kernels with symbols in CKSEG0.Ralf Baechle1-1/+1
2007-09-24[MIPS] SMTC: Make ack_bad_irq() safe with no IM backstop.Ralf Baechle1-8/+24
2007-09-19[MIPS] cpu-bugs64.c: GCC 3.3 constraint workaroundMaciej W. Rozycki1-1/+3
2007-09-14[MIPS] No ide_default_io_base() if PCI IDE was not foundAtsushi Nemoto1-0/+31
2007-09-12BCM1480 serial build fixThiemo Seufer1-0/+5
2007-09-11[MIPS] Ocelot: remove remaining bitsYoichi Yuasa1-30/+0
2007-09-11[MIPS] Provide empty irq_enable_hazard definition for legacy and R1 cores.Ralf Baechle1-0/+1
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