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2026-03-24drm/xe/pf: Add FLR_PREPARE state to VF control flowPiotr Piórkowski6-16/+91
Our xe-vfio-pci component relies on the confirmation from the PF that VF FLR processing has finished, but due to the notification latency on the HW/FW side, PF might be unaware yet of the already triggered VF FLR. Update VF state machine with new FLR_PREPARE state that indicate imminent VF FLR notification and treat that as a begin of the FLR sequence. Also introduce function that xe-vfio-pci should call to guarantee correct synchronization. v2: move PREPARE into WIP, update commit msg (Michal) Signed-off-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Co-developed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Link: https://patch.msgid.link/20260309152449.910636-2-piotr.piorkowski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2026-03-24gpio: drop unneeded Kconfig dependencies on OF_GPIOBartosz Golaszewski1-36/+17
OF_GPIO is selected automatically on all OF systems. Any symbols it controls also provide stubs so there's really no reason to select it explicitly. Remove all Kconfig dependencies/selects for GPIO drivers. For those that have no other dependencies: convert it to requiring CONFIG_OF instead to avoid new symbols popping up in make config. Link: https://patch.msgid.link/20260316-gpio-of-kconfig-v2-3-de2f4b00a0e4@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-03-24accel/ivpu: Add disable clock relinquish workaround for NVL-A0Karol Wachowski2-2/+5
Turn on disable clock relinquish workaround for Nova Lake A0. Without this workaround NPU may not power off correctly after inference, leading to unexpected system behavior. Fixes: 550f4dd2cedd ("accel/ivpu: Add support for Nova Lake's NPU") Cc: <stable@vger.kernel.org> # v6.19+ Reviewed-by: Lizhi.hou <lizhi.hou@amd.com> Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com> Link: https://patch.msgid.link/20260323095029.64613-1-karol.wachowski@linux.intel.com
2026-03-24drm/imagination: Implement handling of context reset notificationAlexandru Dadu4-0/+136
The firmware will send the context reset notification message as part of handling hardware recovery (HWR) events deecoding the message and printing via drm_info(). This eliminates the "Unknown FWCCB command" message that was previously printed. Co-developed-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-3-1a66049a9a65@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-03-24drm/imagination: Switch reset_reason fields from enum to u32Alexandru Dadu2-3/+11
Update the reset_reason fwif structure fields from enum to u32 to remove any ambiguity from the interface (enum is not a fixed size thus is unfit for the purpose of the data type). Fixes: a26f067feac1f ("drm/imagination: Add FWIF headers") Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-2-1a66049a9a65@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-03-24drm/imagination: Add missing rogue context reset reasonsAlexandru Dadu1-0/+12
Update the context reset reason enum with the missing reset reasons in the 6-11 value gap: - CDM Mission/safety checksum mismatch; - TRP checksum mismatch; - GPU ECC error (corrected, OK); - GPU ECC error (uncorrected, HWR); - FW ECC error (corrected, OK); - FW ECC error (uncorrected, ERR); Co-developed-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com> Reviewed-by: Matt Coster <matt.coster@imgtec.com> Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-1-1a66049a9a65@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
2026-03-24drm/i915/lt_phy: Replace crtc compute clockMika Kahola1-24/+1
The existing DPLL compute clock callback for the XE3PLPD platform (`xe3plpd_crtc_compute_clock`) was specific to that platform. Replace it with the more generic Haswell (`hsw_crtc_compute_clock`) implementation so that the compute clock path does not rely on the XE3PLPD hook. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-25-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Enable dpll framework for xe3plpdMika Kahola4-35/+6
xe3plpd platform is supported by dpll framework remove a separate check for hw comparison and rely solely on dpll framework hw comparison. Finally, all required hooks are now in place so initialize PLL manager for xe3plpd platform and remove the redirections to the legacy code paths for clock enable/disable as well as state mismatch checks that are no longer needed. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312101415.2669387-1-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Remove LT PHY specific state verificationMika Kahola4-45/+13
Remove LT PHY specific state verification as DPLL framework has state verification check. v2: Reuse intel_lt_phy_pll_compare_hw_state() as only config[0] and config[0] parameters are reliable with LT PHY (Suraj) v3: Rephrase handling of LT PHY case when verifying the state (CI) v4: Fix checkpatch warning of line length exceeding 100 columns Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-23-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd Thunderbolt PLL hooksMika Kahola3-2/+33
Add the PLL hooks for the TBT PLL on xe3plpd. These are simple stubs similar to the TBT PLL on earlier platforms, since this PLL is always on from the display POV - so no PLL enable/disable programming is required as opposed to the non-TBT PLLs - and the clocks for different link rates are enabled/disabled at a different level, via the intel_encoder::enable_clock()/disable_clock() interface. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-22-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Get encoder configuration for xe3plpd platformMika Kahola1-16/+4
Reuse mtl_ddi_*_get_config functions now that all hooks are in place. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-21-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Readout lane countMika Kahola3-4/+9
Readout lane count back from HW. Reuse existing function for Cx0 for LT PHY case with minor modification to add lanes as function parameters. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-20-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Dump lane count for HW stateMika Kahola1-2/+2
To increase debuggability add lane count as part of HW state dump. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-19-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add .disable_clock hook on DDIMika Kahola2-1/+13
Add new pll_disable_clock functions so that they can be hooked up to dpll->disable. This is just a wrapper over the exitisting intel_xe3plpd_pll_disable to make it compatible With dpll->disable function v2: Revise commit message (Suraj) Drop wrapper for TBT clock disabling and reuse intel_mtl_pll_disable_clock() for DDI clock disabling hook (Suraj) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-18-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add .enable_clock hook on DDIMika Kahola4-21/+34
Enable PLL clock on DDI by moving part of the PLL enabling sequence into a DDI clock enabling function. v2: Reuse intel_mtl_pll_enable_clock for DDI clock enabling Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-17-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .crtc_get_dpllMika Kahola1-0/+1
Add .crtc_get_dpll function pointer to support xe3plpd platform. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-16-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .get_freq hookMika Kahola1-0/+13
Add .get_freq function hook to support dpll framework for xe3plpd platform. v2: Restore port clock calculation (Suraj) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-15-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .get_hw_state hookMika Kahola4-8/+21
Add .get_hw_state hook to xe3plpd platform for dpll framework and update intel_lt_phy_pll_readout_hw_state() function accordingly to support dpll framework. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-14-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .compare_hw_state hookMika Kahola1-0/+10
Add .compare_hw_state function pointer for xe3plpd platform to support dpll framework. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-13-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .dump_hw_state hookMika Kahola4-12/+19
Add .dump_hw_state function pointer for xe3plpd platform to support dpll framework. While at it, switch to use drm_printer structure to print hw state information. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-12-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hookMika Kahola1-0/+1
Add .update_dpll_ref_clks function pointer to xe3plpd platform to support dpll framework. Reuse ICL function pointer. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-11-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .update_active_dpll hookMika Kahola1-0/+1
Add .update_active_dpll function pointer to support dpll framework for xe3plpd platform. Reuse ICL function pointer. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-10-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .put_dplls hookMika Kahola1-0/+1
Add .put_dplls function pointer to support xe3plpd platform on dpll framework. Reuse ICL function pointer. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-9-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .get_dplls hookMika Kahola1-0/+1
Add .get_dplls function pointer for xe3plpd platforms to support dpll framework. Reuse the ICL function pointer. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-8-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add xe3plpd .compute_dplls hookMika Kahola4-9/+78
Add compute dpll hook for xe3plpd platform and bring PLL state calculation to support PLL framework. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-7-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add lane_count to PLL stateMika Kahola2-4/+6
Cache lane count as part of PLL state. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-6-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL stateMika Kahola1-21/+46
The LT PHY implementation currently pulls PLL and port_clock information directly from the CRTC state. This ties the PHY programming logic too tightly to the CRTC state and makes it harder to clearly express the PHY’s own PLL configuration. Introduce an explicit "struct intel_lt_phy_pll_state" argument for the PHY functions and update callers accordingly. No functional change is intended — this is a preparatory cleanup for to bring LT PHY PLL handling as part of PLL framework. v2: DP, HDMI 2.0, and HDMI FRL modes are port of the VDR configuration 0 register. These modes are defined by bits 2:0. Decode these to differentiate DP and HDMI modes when programming PLL's. (Imre, Suraj) v3: Pass port_clock as argument instead of recalculating it (Suraj) v4: Fix checkpatch warning of line length exceeding 100 columns BSpec: 744921 Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-5-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add PLL information for xe3plpdMika Kahola1-0/+19
Start bringing in xe3plpd as part of dpll framework. The work is started by adding PLL information and related function hooks. v2: Fix xe3plpd type (Suraj) Remove empty line between BSpec link and Signed-off-by (Suraj) BSpec: 74304 Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-4-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Add check if PLL is enabledMika Kahola1-0/+11
Add check for PLL enabling and return early if PLL is not enabled. v2: Use PCLK PLL ACK bit to check if PLL is enabled (Suraj) v3: Check only if PCLK PLL ACK bit for lane 0 is enabled (Suraj) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-3-mika.kahola@intel.com
2026-03-24drm/i915/lt_phy: Dump missing PLL state parametersMika Kahola1-1/+3
Dump missing PLL structure members ssc_enabled and tbt_mode in order to enhance debugging. v2: Drop addr_lsb and addr_msb printouts Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260312080657.2648265-2-mika.kahola@intel.com
2026-03-24PCI: sky1: Fix missing cleanup of ECAM config on probe failureFelix Gu1-1/+3
When devm_kzalloc() for reg_off fails, the code returns -ENOMEM without freeing pcie->cfg, which was allocated earlier by pci_ecam_create(). Add the missing pci_ecam_free() call to properly release the allocated ECAM configuration window on this error path. Fixes: a0d9f2c08f45 ("PCI: sky1: Add PCIe host support for CIX Sky1") Signed-off-by: Felix Gu <ustc.gu@gmail.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Hans Zhang <18255117159@163.com> Link: https://patch.msgid.link/20260324-sky1-v1-1-6a00cb2776b6@gmail.com
2026-03-24gpu: nova-core: gsp: move Cmdq's DMA handle to a struct memberAlexandre Courbot2-12/+16
The command-queue structure has a `dma_handle` method that returns the DMA handle to the memory segment shared with the GSP. This works, but is not ideal for the following reasons: - That method is effectively only ever called once, and is technically an accessor method since the handle doesn't change over time, - It feels a bit out-of-place with the other methods of `Cmdq` which only deal with the sending or receiving of messages, - The method has `pub(crate)` visibility, allowing other driver code to access this highly-sensitive handle. Address all these issues by turning `dma_handle` into a struct member with `pub(super)` visibility. This keeps the method space focused, and also ensures the member is not visible outside of the modules that need it. Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Reviewed-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260319-b4-cmdq-dma-handle-v1-1-57840b4a4f90@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-24clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()Shuwei Wu1-1/+1
Fix inverted condition that skips frequency change trigger, causing kernel panics during cpufreq scaling. Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260305-k1-clk-fix-v1-1-abca85d6e266@mailbox.org Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-03-24drm/i915/dp_tunnel: Fix error handling when clearing stream BW in atomic stateImre Deak3-11/+28
Clearing the DP tunnel stream BW in the atomic state involves getting the tunnel group state, which can fail. Handle the error accordingly. This fixes at least one issue where drm_dp_tunnel_atomic_set_stream_bw() failed to get the tunnel group state returning -EDEADLK, which wasn't handled. This lead to the ctx->contended warn later in modeset_lock() while taking a WW mutex for another object in the same atomic state, and thus within the same already contended WW context. Moving intel_crtc_state_alloc() later would avoid freeing saved_state on the error path; this stable patch leaves that simplification for a follow-up. Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: <stable@vger.kernel.org> # v6.9+ Fixes: a4efae87ecb2 ("drm/i915/dp: Compute DP tunnel BW during encoder state computation") Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/7617 Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260320092900.13210-1-imre.deak@intel.com (cherry picked from commit fb69d0076e687421188bc8103ab0e8e5825b1df1) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2026-03-24drm/xe: Send 'none' recovery method for XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESETRaag Jadav1-1/+8
XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET is intended for debugging hangs, so wedge the device with 'none' recovery method and have it available to the user for debugging. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260305130720.3685754-4-raag.jadav@intel.com
2026-03-24drm: Update log for 'none' recovery methodRaag Jadav1-1/+1
Update log for 'none' recovery method for wedged event where driver wants to hint "no recovery" without resetting the device from driver context. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260305130720.3685754-3-raag.jadav@intel.com
2026-03-24Merge tag 'xsa482-7.0-tag' of ↵Linus Torvalds1-3/+70
git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip Pull xen fixes from Juergen Gross: "Restrict the xen privcmd driver in unprivileged domU to only allow hypercalls to target domain when using secure boot" * tag 'xsa482-7.0-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip: xen/privcmd: add boot control for restricted usage in domU xen/privcmd: restrict usage in unprivileged domU
2026-03-24clk: qcom: dispcc-sc7180: Add missing MDSS resetsKonrad Dybcio1-0/+8
The MDSS resets have so far been left undescribed. Fix that. Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Tested-by: Val Packett <val@packett.cool> # sc7180-ecs-liva-qc710 Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-2-0b1b442156c3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-24soc: qcom: ocmem: return -EPROBE_DEFER is ocmem is not availableDmitry Baryshkov1-4/+3
If OCMEM is declared in DT, it is expected that it is present and handled by the driver. The GPU driver will ignore -ENODEV error, which typically means that OCMEM isn't defined in DT. Let ocmem return -EPROBE_DEFER if it supposed to be used, but it is not probed (yet). Fixes: 88c1e9404f1d ("soc: qcom: add OCMEM driver") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260323-ocmem-v1-3-ad9bcae44763@oss.qualcomm.com [bjorn: s/ERR_PTR(dev_err_probe)/dev_err_ptr_probe/ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-24soc: qcom: ocmem: register reasons for probe deferralsDmitry Baryshkov1-4/+4
Instead of printing messages to the dmesg, let the message be recorded as a reason for the OCMEM client deferral. Fixes: 88c1e9404f1d ("soc: qcom: add OCMEM driver") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260323-ocmem-v1-2-ad9bcae44763@oss.qualcomm.com [bjorn: s/ERR_PTR(dev_err_probe)/dev_err_ptr_probe/ Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-24soc: qcom: ocmem: make the core clock optionalDmitry Baryshkov1-1/+1
OCMEM's core clock (aka RPM bus 2 clock) is being handled internally by the interconnect driver. Corresponding clock has been dropped from the SMD RPM clock driver. The users of the ocmem will vote on the ocmemnoc interconnect paths, making sure that ocmem is on. Make the clock optional, keeping it for compatibility with older DT. Fixes: d6edc31f3a68 ("clk: qcom: smd-rpm: Separate out interconnect bus clocks") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260323-ocmem-v1-1-ad9bcae44763@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-24clk: qcom: rcg2: expand frac table for mdss_pixel_clk_srcPengyu Luo1-0/+2
Recently, when testing 10-bit dsi C-PHY panel, clks are different from the usual. (dsi0_phy_pll_out_dsiclk's parent is dsi0_pll_bit_clk now (dsiclk_sel = 0)) And we failed to set dsiclk's children. dsi_link_clk_set_rate_6g: Set clk rates: pclk=172992000, byteclk=108120000 byteclk was set first to 108120000, so the vco rate was set to 108120000 * 7 * 1 * 1 = 756840000. When we was trying to set 172992000 on mdss_pixel_clk_src later. Since there was no matched ratio, we failed to set it. And dsiclk divider ratio was set to 15:1 (wrong cached register value 0xf and didn't update), we finally got 50455997, apparently wrong. dsi0vco_clk 1 1 0 756839941 dsi0_pll_out_div_clk 1 1 0 756839941 dsi0_pll_post_out_div_clk 0 0 0 216239983 dsi0_pll_bit_clk 2 2 0 756839941 dsi0_phy_pll_out_dsiclk 2 2 0 50455997 disp_cc_mdss_pclk1_clk_src 1 1 0 50455997 dsi0_pll_by_2_bit_clk 0 0 0 378419970 dsi0_phy_pll_out_byteclk 2 2 0 108119991 disp_cc_mdss_byte1_clk_src 2 2 0 108119991 Downstream clk_summary shows the mdss_pixel_clk_src support the ratio(35:16) dsi0_phy_pll_out_dsiclk 2 2 0 378420000 disp_cc_mdss_pclk1_clk_src 1 1 0 172992000 dsi0_phy_pll_out_byteclk 2 2 0 108120000 disp_cc_mdss_byte1_clk_src 2 2 0 108120000 After checking downstream source, 15:4 also seems to be supported, add them two. Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260321095029.2259489-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-03-24net: enetc: fix the output issue of 'ethtool --show-ring'Wei Fang1-0/+2
Currently, enetc_get_ringparam() only provides rx_pending and tx_pending, but 'ethtool --show-ring' no longer displays these fields. Because the ringparam retrieval path has moved to the new netlink interface, where rings_fill_reply() emits the *x_pending only if the *x_max_pending values are non-zero. So rx_max_pending and tx_max_pending to are added to enetc_get_ringparam() to fix the issue. Note that the maximum tx/rx ring size of hardware is 64K, but we haven't added set_ringparam() to make the ring size configurable. To avoid users mistakenly believing that the ring size can be increased, so set the *x_max_pending to priv->*x_bd_count. Fixes: e4a1717b677c ("ethtool: provide ring sizes with RINGS_GET request") Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260320094222.706339-1-wei.fang@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-24bnxt_en: Resize RSS contexts on channel count changeBjörn Töpel1-7/+28
bnxt_set_channels() previously rejected channel changes that alter the RSS table size when RSS contexts exist, because non-default context sizes were locked at creation. Replace the rejection with the new resize helpers. RSS table size only changes on P5 chips with older firmware; newer firmware always uses the largest table size. Signed-off-by: Björn Töpel <bjorn@kernel.org> Link: https://patch.msgid.link/20260320085826.1957255-4-bjorn@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-24ethtool: Track user-provided RSS indirection table sizeBjörn Töpel2-11/+13
Track the number of indirection table entries the user originally provided (context 0/default as well!). Replace IFF_RXFH_CONFIGURED with rss_indir_user_size: the flag is redundant now that user_size captures the same information. Add ethtool_rxfh_indir_lost() for drivers that must reset the indirection table. Convert bnxt and mlx5 to use it. Signed-off-by: Björn Töpel <bjorn@kernel.org> Link: https://patch.msgid.link/20260320085826.1957255-2-bjorn@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-24team: use netdev_from_priv()Qingfang Deng1-35/+42
Use the new netdev_from_priv() helper to access the net device from struct team. Signed-off-by: Qingfang Deng <dqfext@gmail.com> Link: https://patch.msgid.link/20260320075605.490832-2-dqfext@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-03-24crypto: sm3 - Remove 'struct sm3_state'Eric Biggers1-2/+2
Update one driver that used sizeof(struct sm3_state) to use sizeof(struct sm3_ctx) instead. Then, remove struct sm3_state and SM3_STATE_SIZE. This completes the replacement of struct sm3_state with struct sm3_ctx. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260321040935.410034-13-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-03-24crypto: sm3 - Replace with wrapper around libraryEric Biggers1-2/+2
Reimplement the "sm3" crypto_shash on top of the SM3 library, closely mirroring the other hash algorithms (e.g. SHA-*). The result, after later commits migrate the architecture-optimized SM3 code into the library as well, is that crypto/sm3.c will be the single point of integration between crypto_shash and the actual SM3 implementations, simplifying the code. Note: to see the diff from crypto/sm3_generic.c to crypto/sm3.c, view this commit with 'git show -M10'. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260321040935.410034-7-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-03-24crypto: sm3 - Rename CRYPTO_SM3_GENERIC to CRYPTO_SM3Eric Biggers2-2/+2
The kconfig options for generic crypto API modules have traditionally *not* had a "_GENERIC" suffix. Also, the "_GENERIC" suffix will make even less sense once the architecture-optimized SM3 code is moved into lib/crypto/ and the "sm3" crypto_shash is reimplemented on top of that. Thus, rename CRYPTO_SM3_GENERIC to CRYPTO_SM3. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260321040935.410034-4-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-03-24net: b44: always select CONFIG_FIXED_PHYArnd Bergmann1-1/+1
When CONFIG_FIXED_PHY=m but CONFIG_B44=y, the kernel fails to link: ld.lld: error: undefined symbol: fixed_phy_unregister >>> referenced by b44.c >>> drivers/net/ethernet/broadcom/b44.o:(b44_remove_one) in archive vmlinux.a ld.lld: error: undefined symbol: fixed_phy_register_100fd >>> referenced by b44.c >>> drivers/net/ethernet/broadcom/b44.o:(b44_register_phy_one) in archive vmlinux.a The fixed phy support is small enough that just always enabling it for b44 is the simplest solution, and it avoids adding ugly #ifdef checks. Fixes: 10d2f15afba2 ("net: b44: register a fixed phy using fixed_phy_register_100fd if needed") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20260320154927.674555-1-arnd@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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