Age | Commit message (Expand) | Author | Files | Lines |
2017-04-12 | clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock | Robin van der Gracht | 1 | -4/+5 |
2017-04-12 | Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/g... | Michael Turquette | 14 | -253/+699 |
2017-04-12 | cs-2000-cp: keep Reserved bit on each register | Kuninori Morimoto | 1 | -3/+22 |
2017-04-12 | clk: qcom: msm8996: Fix the vfe1 powerdomain name | Rajendra Nayak | 1 | -1/+1 |
2017-04-12 | clk: stm32f4: fix timeout management for pll and ready gate | Gabriel Fernandez | 1 | -14/+29 |
2017-04-12 | clk: iproc: Remove redundant check | Ray Jui | 1 | -1/+1 |
2017-04-12 | Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/... | Michael Turquette | 7 | -238/+253 |
2017-04-12 | Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/... | Michael Turquette | 6 | -78/+299 |
2017-04-12 | Merge branch 'clk-fixes' into clk-next | Stephen Boyd | 1 | -3/+10 |
2017-04-12 | clk: stm32f4: fix: exclude values 0 and 1 for PLLQ | Gabriel Fernandez | 1 | -3/+10 |
2017-04-12 | Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-... | Stephen Boyd | 20 | -522/+501 |
2017-04-12 | clk: hi6220: add debug APB clock | Leo Yan | 1 | -0/+1 |
2017-04-04 | clk: tegra: Don't reset PLL-CX if it is already enabled | Jon Hunter | 1 | -4/+4 |
2017-04-04 | clk: tegra: Add missing Tegra210 clocks | Peter De Schrijver | 3 | -0/+19 |
2017-04-04 | clk: tegra: Propagate clk_out_x rate to parent | Alex Frid | 1 | -2/+4 |
2017-03-30 | clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 | Geert Uytterhoeven | 1 | -11/+27 |
2017-03-30 | clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 | Geert Uytterhoeven | 1 | -50/+151 |
2017-03-30 | clk: renesas: cpg-mssr: Add support for fixing up clock tables | Geert Uytterhoeven | 2 | -0/+72 |
2017-03-24 | Merge tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/... | Stephen Boyd | 5 | -3/+12 |
2017-03-22 | clk: rockchip: add pll_wait_lock for pll_enable | Elaine Zhang | 1 | -0/+3 |
2017-03-22 | clk: rockchip: rename RK1108 to RV1108 | Andy Yan | 3 | -222/+222 |
2017-03-21 | clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0 | Geert Uytterhoeven | 1 | -0/+24 |
2017-03-21 | clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init() | Geert Uytterhoeven | 4 | -4/+6 |
2017-03-21 | clk: renesas: r8a7796: Reformat core clock table | Geert Uytterhoeven | 1 | -6/+6 |
2017-03-21 | clk: renesas: r8a7795: Reformat core clock table | Geert Uytterhoeven | 1 | -10/+10 |
2017-03-21 | clk: renesas: r8a7796: Correct name of watchdog clock | Geert Uytterhoeven | 1 | -1/+1 |
2017-03-21 | clk: renesas: r8a7795: Correct name of watchdog clock | Geert Uytterhoeven | 1 | -1/+1 |
2017-03-21 | clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs | Geert Uytterhoeven | 1 | -2/+2 |
2017-03-20 | clk: tegra: Fix build warnings on Tegra20/Tegra30 | Thierry Reding | 2 | -2/+2 |
2017-03-20 | clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on | Peter De Schrijver | 1 | -0/+2 |
2017-03-20 | clk: tegra: Add SATA seq input control | Peter De Schrijver | 1 | -0/+25 |
2017-03-20 | clk: tegra: Add Tegra210 special resets | Peter De Schrijver | 1 | -0/+85 |
2017-03-20 | clk: tegra: Rework pll_u | Peter De Schrijver | 2 | -197/+272 |
2017-03-20 | clk: tegra: Implement reset control reset | Mikko Perttunen | 1 | -0/+16 |
2017-03-20 | clk: tegra: Fix disable unused for clocks sharing enable bit | Peter De Schrijver | 1 | -0/+3 |
2017-03-20 | clk: tegra: Handle UTMIPLL IDDQ | Peter De Schrijver | 1 | -0/+26 |
2017-03-20 | clk: tegra: Add aclk | Peter De Schrijver | 1 | -0/+10 |
2017-03-20 | clk: tegra: Add super clock mux/divider | Peter De Schrijver | 2 | -5/+89 |
2017-03-20 | clk: tegra: Define Tegra210 DMIC clocks | Peter De Schrijver | 3 | -1/+28 |
2017-03-20 | clk: tegra: Fix constness for peripheral clocks | Peter De Schrijver | 2 | -4/+4 |
2017-03-20 | clk: tegra: Define Tegra210 DMIC sync clocks | Peter De Schrijver | 3 | -24/+73 |
2017-03-20 | clk: tegra: Add CEC clock | Peter De Schrijver | 6 | -0/+6 |
2017-03-20 | clk: tegra: Fix type for m field | Peter De Schrijver | 1 | -1/+1 |
2017-03-20 | clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation | Peter De Schrijver | 1 | -1/+7 |
2017-03-20 | clk: tegra: Don't warn for PLL defaults unnecessarily | Peter De Schrijver | 1 | -6/+12 |
2017-03-20 | clk: tegra: Remove non-existing pll_m_out1 clock | Peter De Schrijver | 1 | -5/+0 |
2017-03-20 | clk: tegra: Correct afi clock parent | Peter De Schrijver | 1 | -1/+1 |
2017-03-20 | clk: tegra: Fix ISP clock modelling | Peter De Schrijver | 3 | -2/+11 |
2017-03-20 | clk: tegra: Fix pll_a1 iddq register, add pll_a1 | Peter De Schrijver | 1 | -1/+2 |
2017-03-20 | clk: sunxi-ng: fix recalc_rate formula of NKMP clocks | Icenowy Zheng | 1 | -1/+1 |