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2021-02-12net: fix dev_ifsioc_locked() race conditionCong Wang2-7/+5
dev_ifsioc_locked() is called with only RCU read lock, so when there is a parallel writer changing the mac address, it could get a partially updated mac address, as shown below: Thread 1 Thread 2 // eth_commit_mac_addr_change() memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); // dev_ifsioc_locked() memcpy(ifr->ifr_hwaddr.sa_data, dev->dev_addr,...); Close this race condition by guarding them with a RW semaphore, like netdev_get_name(). We can not use seqlock here as it does not allow blocking. The writers already take RTNL anyway, so this does not affect the slow path. To avoid bothering existing dev_set_mac_address() callers in drivers, introduce a new wrapper just for user-facing callers on ioctl and rtnetlink paths. Note, bonding also changes slave mac addresses but that requires a separate patch due to the complexity of bonding code. Fixes: 3710becf8a58 ("net: RCU locking for simple ioctl()") Reported-by: "Gong, Sishuai" <sishuai@purdue.edu> Cc: Eric Dumazet <eric.dumazet@gmail.com> Cc: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Cong Wang <cong.wang@bytedance.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: fix interrupt mask/unmask skip conditionStefan Chulski1-2/+2
The condition should be skipped if CPU ID equal to nthreads. The patch doesn't fix any actual issue since nthreads = min_t(unsigned int, num_present_cpus(), MVPP2_MAX_THREADS). On all current Armada platforms, the number of CPU's is less than MVPP2_MAX_THREADS. Fixes: e531f76757eb ("net: mvpp2: handle cases where more CPUs are available than s/w threads") Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: ti: am65-cpsw-nuss: Add switchdev supportVignesh Raghavendra4-1/+587
J721e, J7200 and AM64 have multi port switches which can work in multi mac mode and in switch mode. Add support for configuring this HW in switch mode using devlink and switchdev notifiers. Support is similar to existing CPSW switchdev implementation of TI's 32 bit platform like AM33/AM43/AM57. To enable switch mode: devlink dev param set platform/8000000.ethernet name switch_mode value true cmode runtime All configuration is implemented via switchdev API and notifiers. Supported: - SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS - SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS - SWITCHDEV_ATTR_ID_PORT_STP_STATE - SWITCHDEV_OBJ_ID_PORT_VLAN - SWITCHDEV_OBJ_ID_PORT_MDB - SWITCHDEV_OBJ_ID_HOST_MDB Hence AM65 CPSW switchdev driver supports: - FDB offloading - MDB offloading - VLAN filtering and offloading - STP Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: ti: am65-cpsw-nuss: Add netdevice notifiersVignesh Raghavendra2-1/+133
Register netdevice notifiers in order to receive notification when individual MAC ports are added to the HW bridge. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: ti: am65-cpsw-nuss: Add devlink supportVignesh Raghavendra3-18/+377
AM65 NUSS ethernet switch on K3 devices can be configured to work either in independent mac mode where each port acts as independent network interface (multi mac) or switch mode. Add devlink hooks to provide a way to switch b/w these modes. Rationale to use devlink instead of defaulting to bridge mode is that SoC use cases require to support multiple independent MAC ports with no switching so that users can use software bridges with multi-mac configuration (e.g: to support LAG, HSR/PRP, etc). Also, switching between multi mac and switch mode requires significant Port and ALE reconfiguration, therefore is easier to be made as part of mode change devlink hooks. It also allows to keep user interface similar to what was implemented for the previous generation of TI CPSW IP (on AM33/AM43/AM57 SoCs). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: broadcom: bcm4908_enet: fix endianness in xmit codeRafał Miłecki1-1/+1
Use le32_to_cpu() for reading __le32 struct field filled by hw. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: broadcom: bcm4908_enet: fix received skb lengthRafał Miłecki1-1/+1
Use ETH_FCS_LEN instead of magic value and drop incorrect + 2 Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: broadcom: bcm4908_enet: fix minor typosRafał Miłecki1-5/+5
1. Fix "ensable" typo noticed by Andrew 2. Fix chipset name in the struct net_device_ops variable Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: broadcom: bcm4908_enet: drop "inline" from C functionsRafał Miłecki1-12/+7
It seems preferred to let compiler optimize code if applicable. While at it drop unused enet_umac_maskset(). Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: broadcom: bcm4908_enet: drop unneeded memset()Rafał Miłecki1-2/+0
dma_alloc_coherent takes care of zeroing allocated memory Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: broadcom: rename BCM4908 driver & update DT bindingRafał Miłecki4-111/+112
compatible string was updated to match normal naming convention so update driver as well Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernDavid S. Miller12-92/+448
el/git/bluetooth/bluetooth-next Johan Hedberg says: ==================== pull request: bluetooth-next 2021-02-11 Here's the main bluetooth-next pull request for 5.12: - Add support for advertising monitor offliading using Microsoft vendor extensions - Add firmware download support for MediaTek MT7921U USB devices - Suspend-related fixes for Qualcomm devices - Add support for Intel GarfieldPeak controller - Various other smaller fixes & cleanups Please let me know if there are any issues pulling. Thanks. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10k: MAC internal loopback supportHariprasad Kelam6-6/+61
MAC on CN10K silicon support loopback for selftest or debug purposes. This patch does necessary configuration to loopback packets upon receiving request from LMAC mapped RVU PF's netdev via mailbox. Also MAC (CGX) on OcteonTx2 silicon variants and MAC (RPM) on OcteonTx3 CN10K are different and loopback needs to be configured differently. Upper layer interface between RVU AF and PF netdev is kept same. Based on silicon variant appropriate fn() pointer is called to config the MAC. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10k: Add RPM Rx/Tx stats supportHariprasad Kelam8-26/+227
RPM supports below list of counters as an extension to existing counters * class based flow control pause frames * vlan/jabber/fragmented packets * fcs/alignment/oversized error packets This patch adds support to display supported RPM counters via debugfs and define new mbox rpm_stats to read all support counters. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10k: Add RPM LMAC pause frame supportRakesh Babu6-23/+201
Flow control configuration is different for CGX(Octeontx2) and RPM(CN10K) functional blocks. This patch adds the necessary changes for RPM to support 802.3 pause frames configuration on cn10k platforms. Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-pf: cn10k: Get max mtu supported from admin functionHariprasad Kelam7-18/+97
CN10K supports max MTU of 16K on LMAC links and 64k on LBK links and Octeontx2 silicon supports 9K mtu on both links. Get the same from nix_get_hw_info mbox message in netdev probe. This patch also calculates receive buffer size required based on the MTU set. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10K: Add MTU configurationHariprasad Kelam11-12/+138
OcteonTx3 CN10K silicon supports bigger MTU when compared to 9216 MTU supported by OcteonTx2 silicon variants. Lookback interface supports upto 64K and RPM LMAC interfaces support upto 16K. This patch does the necessary configuration and adds support for PF/VF drivers to retrieve max packet size supported via mbox This patch also configures tx link credit by considering supported fifo size and max packet length for Octeontx3 silicon. This patch also removes platform specific name from the driver name. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10k: Add support for programmable channelsSubbaraya Sundeep11-17/+359
NIX uses unique channel numbers to identify the packet sources/sinks like CGX,LBK and SDP. The channel numbers assigned to each block are hardwired in CN9xxx silicon. The fixed channel numbers in CN9xxx are: 0x0 | a << 8 | b - LBK(0..3)_CH(0..63) 0x0 | a << 8 - Reserved 0x700 | a - SDP_CH(0..255) 0x800 | a << 8 | b << 4 | c - CGX(0..7)_LMAC(0..3)_CH(0..15) All the channels in the above fixed enumerator(with maximum number of blocks) are not required since some chips have less number of blocks. For CN10K silicon the channel numbers need to be programmed by software in each block with the base channel number and range of channels. This patch calculates and assigns the channel numbers to efficiently distribute the channel number range(0-4095) among all the blocks. The assignment is made based on the actual number of blocks present and also contiguously leaving no holes. The channel numbers remaining after the math are used as new CPT replay channels present in CN10K. Also since channel numbers are not fixed the transmit channel link number needed by AF consumers is calculated by AF and sent along with nix_lf_alloc mailbox response. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10k: Add RPM MAC supportHariprasad Kelam11-106/+478
OcteonTx2's next gen platform the CN10K has RPM MAC which has a different serdes when compared to CGX MAC. Though the underlying HW is different, the CSR interface has been designed largely inline with CGX MAC, with few exceptions though. So we are using the same CGX driver for RPM MAC as well and will have a different set of APIs for RPM where ever necessary. This patch adds initial support for CN10K's RPM MAC i.e. the driver registration, communication with firmware etc. For communication with firmware, RPM provides a different IRQ when compared to CGX. The CGX and RPM blocks support different features. Currently few features like ptp, flowcontrol and higig are not supported by RPM. This patch adds new mailbox message "CGX_FEATURES_GET" to get the list of features supported by underlying MAC. RPM has different implementations for RX/TX stats. Unlike CGX, bar offset of stat registers are different. This patch adds support to access the same and dump the values in debugfs. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-pf: cn10k: Use LMTST lines for NPA/NIX operationsGeetha sowjanya10-135/+328
This patch adds support to use new LMTST lines for NPA batch free and burst SQE flush. Adds new dev_hw_ops structure to hold platform specific functions and create new files cn10k.c and cn10k.h. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-pf: cn10k: Map LMTST regionGeetha sowjanya3-4/+100
On CN10K platform transmit/receive buffer alloc and free from/to hardware had changed to support burst operation. Whereas pervious silicon's only support single buffer free at a time. To Support the same firmware allocates a DRAM region for each PF/VF for storing LMTLINES. These LMTLINES are used for NPA batch free and for flushing SQE to the hardware. PF/VF LMTST region is accessed via BAR4. PFs LMTST region is followed by its VFs mbox memory. The size of region varies from 2KB to 256KB based on number of LMTLINES configured. This patch adds support for - Mapping PF/VF LMTST region. - Reserves 0-71 (RX + TX + XDP) LMTST lines for NPA batch free operation. - Reserves 72-512 LMTST lines for NIX SQE flush. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-pf: cn10k: Initialise NIX contextGeetha sowjanya2-31/+80
On CN10K platform NIX RQ and SQ context structure got changed. This patch uses new mbox message "NIX_CN10K_AQ_ENQ" for NIX context initialization on CN10K platform. This patch also updates the nix_rx_parse_s and nix_sqe_sg_s structures to add packet steering bit feilds. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10k: Update NIX and NPA context in debugfsGeetha sowjanya1-2/+175
On CN10K platform NPA and NIX context structure bit fields had changed to support new features like bandwidth steering etc. This patch dumps approprate context for CN10K platform. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10k: Update NIX/NPA context structureGeetha sowjanya3-424/+223
NIX hardware context structure got changed to accommodate new features like bandwidth steering, L3/L4 outer/inner checksum enable/disable etc., on CN10K platform. This patch defines new mbox message NIX_CN10K_AQ_INST for new NIX context initialization. This patch also updates the NPA context structures to accommodate bit field changes made for CN10K platform. This patch also removes Big endian bit fields from existing structures as its support got deprecated in current and upcoming silicons. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-pf: cn10k: Add mbox support for CN10KSubbaraya Sundeep6-27/+73
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitate communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. The patch also adds new hw_cap flag to setting hw features like TSO etc and removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms This patch also removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12octeontx2-af: cn10k: Add mbox support for CN10K platformSubbaraya Sundeep6-36/+191
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitates communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. This patch also adds CN10K PTP subsystem and device IDs to ptp driver id table. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add TX FC firmware checkStefan Chulski2-7/+33
Patch check that TX FC firmware is running in CM3. If not, global TX FC would be disabled. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: set 802.3x GoP Flow Control modeStefan Chulski1-1/+1
This patch fix GMAC TX flow control autoneg. Flow control autoneg wrongly were disabled with enabled TX flow control. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add PPv23 RX FIFO flow controlStefan Chulski2-0/+68
New FIFO flow control feature was added in PPv23. PPv2 FIFO polled by HW and trigger pause frame if FIFO fill level is below threshold. FIFO HW flow control enabled with CM3 RXQ&BM flow control with ethtool. Current FIFO thresholds is: 9KB for port with maximum speed 10Gb/s port 4KB for port with maximum speed 5Gb/s port 2KB for port with maximum speed 1Gb/s port Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add BM protection underrun feature supportStefan Chulski2-0/+34
The PP2v23 hardware supports a feature allowing to double the size of BPPI by decreasing number of pools from 16 to 8. Increasing of BPPI size protect BM drop from BPPI underrun. Underrun could occurred due to stress on DDR and as result slow buffer transition from BPPE to BPPI. New BPPI threshold recommended by spec is: BPPI low threshold - 640 buffers BPPI high threshold - 832 buffers Supported only in PPv23. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add ethtool flow control configuration supportStefan Chulski2-0/+111
This patch add ethtool flow control configuration support. Tx flow control retrieved correctly by ethtool get function. FW per port ethtool configuration capability added. Patch also takes care about mtu change procedure, if PPv2 switch BM pools during mtu change. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add RXQ flow control configurationsStefan Chulski2-1/+150
This patch adds RXQ flow control configurations. Flow control disabled by default. Minimum ring size limited to 1024 descriptors. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: enable global flow controlStefan Chulski2-4/+37
This patch enables global flow control in FW and in the phylink validate mask. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add FCA RXQ non occupied descriptor thresholdStefan Chulski2-7/+40
The firmware needs to monitor the RX Non-occupied descriptor bits for flow control to move to XOFF mode. These bits need to be unmasked to be functional, but they will not raise interrupts as we leave the RX exception summary bit in MVPP2_ISR_RX_TX_MASK_REG clear. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add FCA periodic timer configurationsStefan Chulski2-0/+58
Flow Control periodic timer would be used if port in XOFF to transmit periodic XOFF frames. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: increase BM pool and RXQ sizeStefan Chulski1-4/+4
BM pool and RXQ size increased to support Firmware Flow Control. Minimum depletion thresholds to support FC are 1024 buffers. BM pool size increased to 2048 to have some 1024 buffers space between depletion thresholds and BM pool size. Jumbo frames require a 9888B buffer, so memory requirements for data buffers increased from 7MB to 24MB. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add PPv23 version definitionStefan Chulski2-15/+24
This patch add PPv23 version definition. PPv23 is new packet processor in CP115. Everything that supported by PPv22, also supported by PPv23. No functional changes in this stage. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: always compare hw-version vs MVPP21Stefan Chulski1-19/+19
Currently we have PP2v1 and PP2v2 hw-versions, with some different handlers depending upon condition hw_version = MVPP21/MVPP22. In a future there will be also PP2v3. Let's use now the generic "if equal/notEqual MVPP21" for all cases instead of "if MVPP22". This patch does not change any functionality. It is not intended to introduce PP2v3. It just modifies MVPP21/MVPP22 check-condition bringing it to generic and unified form correct for new-code introducing and PP2v3 net-next generation. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: mvpp2: add CM3 SRAM memory mapStefan Chulski2-0/+27
This patch adds CM3 memory map. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12xen/events: link interdomain events to associated xenbus deviceJuergen Gross6-30/+37
In order to support the possibility of per-device event channel settings (e.g. lateeoi spurious event thresholds) add a xenbus device pointer to struct irq_info() and modify the related event channel binding interfaces to take the pointer to the xenbus device as a parameter instead of the domain id of the other side. While at it remove the stale prototype of bind_evtchn_to_irq_lateeoi(). Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Wei Liu <wei.liu@kernel.org> Reviewed-by: Paul Durrant <paul@xen.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12xen/netback: fix spurious event detection for common event caseJuergen Gross1-3/+5
In case of a common event for rx and tx queue the event should be regarded to be spurious if no rx and no tx requests are pending. Unfortunately the condition for testing that is wrong causing to decide a event being spurious if no rx OR no tx requests are pending. Fix that plus using local variables for rx/tx pending indicators in order to split function calls and if condition. Fixes: 23025393dbeb3b ("xen/netback: use lateeoi irq binding") Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Wei Liu <wl@xen.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12Merge tag 'mlx5-for-upstream-2021-02-10' of ↵David S. Miller8-10/+16
git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5-for-upstream-2021-02-10 Misc cleanups and trivial fixes for net-next 1) spelling mistakes 2) error path checks fixes 3) unused includes and struct fields cleanup 4) build error when MLX5_ESWITCH=no ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12r8169: disable detection of bogus xid's 308/388Heiner Kallweit1-3/+6
Several years ago these two entries have been added, but it's not clear why. There's no trace that there has ever been such a chip version, and not even the r8101 vendor driver knows these id's. So let's disable detection, and if nobody complains remove them completely later. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12bonding: 3ad: Print an error for unknown speedsIdo Schimmel1-4/+4
The bond driver needs to be patched to support new ethtool speeds. Currently it emits a single warning [1] when it encounters an unknown speed. As evident by the two previous patches, this is not explicit enough. Instead, promote it to an error. [1] bond10: (slave swp1): unknown ethtool speed (200000) for port 1 (set it to 0) v2: * Use pr_err_once() instead of WARN_ONCE() Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Nikolay Aleksandrov <nikolay@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12bonding: 3ad: add support for 400G speedNikolay Aleksandrov1-0/+9
In order to be able to use 3ad mode with 400G devices we need to extend the supported speeds. Signed-off-by: Nikolay Aleksandrov <nikolay@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12bonding: 3ad: add support for 200G speedNikolay Aleksandrov1-0/+9
In order to be able to use 3ad mode with 200G devices we need to extend the supported speeds. Signed-off-by: Nikolay Aleksandrov <nikolay@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12qede: preserve per queue stats across up/down of interfaceBhaskar Upadhaya3-7/+48
Here we do the initialization of coalescing values on load. per queue coalesce values are also restored across up/down of ethernet interface. Signed-off-by: Bhaskar Upadhaya <bupadhaya@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12qede: add per queue coalesce support for qede driverBhaskar Upadhaya1-0/+124
per queue coalescing allows better and more finegrained control over interrupt rates. Signed-off-by: Bhaskar Upadhaya <bupadhaya@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12qede: add netpoll support for qede driverBhaskar Upadhaya1-1/+2
handle netpoll case when qede_poll is called by netpoll layer with budget 0 Signed-off-by: Bhaskar Upadhaya <bupadhaya@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12net: hns3: fix return of random stack valueGustavo A. R. Silva1-2/+1
Currently, a random stack value is being returned because variable _ret_ is not properly initialized. This variable is actually not used anymore and it should be removed. Fix this by removing all instances of variable ret and return 0. Fixes: 64749c9c38a9 ("net: hns3: remove redundant return value of hns3_uninit_all_ring()") Addresses-Coverity-ID: 1501700 ("Uninitialized scalar variable") Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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