| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-01-27 | Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner... | Stephen Boyd | 15 | -104/+929 |
| 2018-01-27 | Merge branches 'clk-remove-asm-clkdev', 'clk-debugfs-fixes', 'clk-renesas' an... | Stephen Boyd | 21 | -163/+1276 |
| 2018-01-27 | Merge branch 'clk-divider-container' into clk-next | Stephen Boyd | 8 | -12/+14 |
| 2018-01-27 | Merge branches 'clk-iproc', 'clk-mvebu' and 'clk-qcom-a53' into clk-next | Stephen Boyd | 10 | -102/+737 |
| 2018-01-27 | Merge branches 'clk-at91', 'clk-imx7ulp', 'clk-axigen', 'clk-si5351' and 'clk... | Stephen Boyd | 7 | -41/+146 |
| 2018-01-27 | Merge branches 'clk-spreadtrum', 'clk-mvebu-dvfs', 'clk-qoriq', 'clk-imx' and... | Stephen Boyd | 29 | -81/+7213 |
| 2018-01-27 | Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' ... | Stephen Boyd | 15 | -5241/+918 |
| 2018-01-27 | clk: aspeed: Handle inverse polarity of USB port 1 clock gate | Benjamin Herrenschmidt | 1 | -3/+12 |
| 2018-01-27 | clk: aspeed: Fix return value check in aspeed_cc_init() | Wei Yongjun | 1 | -1/+1 |
| 2018-01-27 | clk: aspeed: Add reset controller | Joel Stanley | 1 | -1/+81 |
| 2018-01-27 | clk: aspeed: Register gated clocks | Joel Stanley | 1 | -0/+130 |
| 2018-01-27 | clk: aspeed: Add platform driver and register PLLs | Joel Stanley | 1 | -0/+130 |
| 2018-01-27 | clk: aspeed: Register core clocks | Joel Stanley | 1 | -0/+177 |
| 2018-01-27 | clk: Add clock driver for ASPEED BMC SoCs | Joel Stanley | 3 | -0/+154 |
| 2018-01-11 | clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built | Sean Wang | 3 | -9/+2 |
| 2018-01-11 | clk: fix reentrancy of clk_enable() on UP systems | David Lechner | 1 | -1/+9 |
| 2018-01-11 | clk: meson-axg: fix potential NULL dereference in axg_clkc_probe() | weiyongjun (A) | 1 | -0/+2 |
| 2018-01-11 | clk: Simplify debugfs registration | Stephen Boyd | 1 | -6/+2 |
| 2018-01-11 | clk: Fix debugfs_create_*() usage | Geert Uytterhoeven | 1 | -19/+17 |
| 2018-01-11 | clk: Show symbolic clock flags in debugfs | Geert Uytterhoeven | 1 | -2/+55 |
| 2018-01-05 | clk: renesas: r8a7796: Add FDP clock | ABE Hiroshige | 1 | -0/+1 |
| 2018-01-05 | clk: Move __clk_{get,put}() into private clk.h API | Stephen Boyd | 1 | -0/+4 |
| 2018-01-05 | clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks | Stephen Boyd | 6 | -47/+44 |
| 2018-01-04 | clk: Improve flags doc for of_clk_detect_critical() | Geert Uytterhoeven | 1 | -1/+1 |
| 2018-01-03 | clk: sunxi-ng: a83t: Add M divider to TCON1 clock | Jernej Škrabec | 1 | -2/+2 |
| 2018-01-03 | Merge tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson into... | Stephen Boyd | 1 | -1/+1 |
| 2018-01-03 | clk: Prepare to remove asm-generic/clkdev.h | Stephen Boyd | 1 | -1/+1 |
| 2018-01-02 | clk: qcom: Add APCS clock controller support | Georgi Djakov | 3 | -0/+150 |
| 2018-01-02 | clk: qcom: Add regmap mux-div clocks support | Georgi Djakov | 3 | -0/+276 |
| 2018-01-02 | clk: qcom: Add A53 PLL support | Georgi Djakov | 3 | -0/+118 |
| 2017-12-29 | clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU | Icenowy Zheng | 1 | -3/+3 |
| 2017-12-29 | clk: sunxi-ng: add support for Allwinner H3 DE2 CCU | Icenowy Zheng | 1 | -0/+47 |
| 2017-12-29 | clk: divider: fix incorrect usage of container_of | Jerome Brunet | 7 | -11/+12 |
| 2017-12-29 | clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO() | Gomonovych, Vasyl | 1 | -4/+1 |
| 2017-12-29 | clk: iproc: Minor tidy up of iproc pll data structures | Lori Hikichi | 1 | -47/+36 |
| 2017-12-29 | clk: iproc: Allow plls to do minor rate changes without reset | Lori Hikichi | 1 | -0/+47 |
| 2017-12-29 | clk: iproc: Fix error in the pll post divider rate calculation | Lori Hikichi | 1 | -16/+17 |
| 2017-12-29 | clk: iproc: Allow iproc pll to runtime calculate vco parameters | Lori Hikichi | 3 | -35/+92 |
| 2017-12-28 | clk: si5351: _si5351_clkout_reset_pll() can be static | Wu Fengguang | 1 | -1/+1 |
| 2017-12-28 | clk: pxa: unbreak lookup of CLK_POUT | Igor Grinberg | 1 | -1/+5 |
| 2017-12-28 | clk: meson-axg: make local symbol axg_gp0_params_table static | weiyongjun (A) | 1 | -1/+1 |
| 2017-12-28 | clk: meson-axg: fix return value check in axg_clkc_probe() | weiyongjun (A) | 1 | -1/+1 |
| 2017-12-27 | clk: mediatek: Fix all warnings for missing struct clk_onecell_data | Sean Wang | 1 | -0/+1 |
| 2017-12-24 | clk: meson: mpll: use 64-bit maths in params_from_rate | Martin Blumenstingl | 1 | -1/+1 |
| 2017-12-22 | clk: si5351: Do not enable parent clocks on probe | Sergej Sawazki | 1 | -26/+9 |
| 2017-12-22 | clk: si5351: Rename internal plls to avoid name collisions | Sergej Sawazki | 1 | -1/+1 |
| 2017-12-22 | clk: si5351: Apply PLL soft reset before enabling the outputs | Sergej Sawazki | 1 | -0/+29 |
| 2017-12-22 | clk: si5351: Add DT property to enable PLL reset | Sergej Sawazki | 1 | -0/+3 |
| 2017-12-22 | clk: si5351: implement remove handler | Alexey Khoroshilov | 1 | -0/+13 |
| 2017-12-22 | clk: axi-clkgen: Round closest in round_rate() and recalc_rate() | Lars-Peter Clausen | 1 | -3/+7 |
