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2014-03-12pinctrl: mvebu: silence WARN to dev_warnSebastian Hesselbarth1-1/+2
Pinctrl will WARN on missing DT resources, which is a little bit too noisy. Use dev_warn with FW_BUG instead. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12pinctrl: msm: drop wake_irqs bitmapJosh Cartwright1-13/+1
Currently, the wake_irqs bitmap is used to track whether there are any gpio's which are configured as wake irqs, and uses this to determine whether or not to call enable_irq_wake()/disable_irq_wake() on the summary interrupt. However, the genirq core already handles this case, by maintaining a 'wake_count' per irq_desc, and only calling into the controlling irq_chip when wake_count transitions 0 <-> 1. Drop this bitmap, and unconditionally call irq_set_irq_wake() on the summary interrupt. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-11pinctrl-baytrail: add function mux checking in gpio pin requestChew, Kean Ho1-3/+39
The requested gpio pin must has the func_pin_mux field set to GPIO function by BIOS/FW in advanced. Else, the gpio pin request would fail. This is to ensure that we do not expose any gpio pins which shall be used for alternate functions, for eg: wakeup pin, I/O interfaces for LPSS, etc. Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Reviewed-by: Darren Hart <dvhart@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-11pinctrl: tegra: fix some typos and inconsistenciesStephen Warren2-29/+17
drive_dev3_pins in pinctrl-tegra114.c wasn't used; delete it. pinctrl-tegra124.c had quite a few typos. Fix those. pinctrl-tegra124.c had a few mismatches between the *_groups[] ararys and the function lists in tegra124_groups[]. Fix those. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05pinctrl: sh-pfc: r8a7791: Add alternative MSIOF pin groupsGeert Uytterhoeven1-0/+469
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05pinctrl: sh-pfc: r8a7790: Add alternative MSIOF pin groupsGeert Uytterhoeven1-0/+129
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-03Merge branch 'pinctrl-mvebu' into develLinus Walleij10-290/+1291
2014-03-01Merge tag 'tags/for-mvebu-pinctrl-3xx' into mvebu/pinctrlJason Cooper4-0/+931
Sign for-mvebu/pinctrl-3xx
2014-02-26pinctrl: mvebu: dove: use global register regmapSebastian Hesselbarth1-66/+58
Now that we have a regmap for global registers, get rid of the last remaining hardcoded physical addresses. While at it, also remove DOVE_ prefix from those macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-26pinctrl: mvebu: dove: use remapped pmu_mpp registersSebastian Hesselbarth1-5/+7
Now that we have ioremapped pmu_mpp registers, get rid of hardcoded physical addresses. While at it, also remove DOVE_ prefix from those macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-26pinctrl: mvebu: dove: use remapped mpp4 registerSebastian Hesselbarth1-26/+27
Now that we have an ioremapped mpp4 register, get rid of hardcoded physical addresses. While at it, also remove DOVE_ prefix from those macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-26pinctrl: mvebu: dove: use remapped mpp base registersSebastian Hesselbarth1-13/+14
Now that we have ioremapped mpp base registers, get rid of hardcoded physical addresses. While at it, also remove DOVE_ prefix from those macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-26pinctrl: mvebu: dove: request syscon regmap for global registersSebastian Hesselbarth2-0/+28
Dove pinctrl uses some global config registers to control pins. This patch requests a syscon regmap for those registers. As this changes DT to driver requirements, fallback to a self-registered regmap with hardcoded resources, if the corresponding syscon DT node is missing. Also, WARN about old DT binding usage to encourage users to update their DTBs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-26pinctrl: mvebu: dove: request additional resourcesSebastian Hesselbarth1-3/+42
Dove pinctrl also requires additional registers to control all pins. This patch requests resources for mpp4 and pmu-mpp register ranges. As this changes DT to driver requirements, fallback to hardcoded resources, if the corresponding DT regs have not been set. Also, WARN about old DT binding usage to encourage users to update their DTBs. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385Thomas Petazzoni3-0/+467
The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375Thomas Petazzoni3-0/+464
The Marvell Armada 375 is a new ARM SoC from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2014-02-25pinctrl: mvebu: dove: reuse mpp_{set,get} in pmu callbacksSebastian Hesselbarth1-20/+17
Dove has pins that can be switched between normal and pmu functions. Rework pmu_mpp callbacks to reuse default mpp ctrl helpers. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25pinctrl: mvebu: dove: consolidate auto-numbered pmu mpp rangesSebastian Hesselbarth1-16/+1
Passing a NULL name for pin ranges will auto-generate standard names for each pin. With common pinctrl driver now checking NULL name correctly, consolidate mpp pins 0-15. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25pinctrl: mvebu: remove MPP_REG_CTRL macroThomas Petazzoni1-16/+3
Now that each per-SoC pinctrl driver must implement its own get/set functions, there is no point in keeping the MPP_REG_CTRL macro, whose purpose was to let the core pinctrl mvebu driver use default get/set functions. While at it also update the comment about mvebu_mpp_ctrl. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25pinctrl: mvebu: remove common get/set functionsSebastian Hesselbarth1-47/+2
With every SoC always providing its own get/set callbacks, we can now remove the generic ones, remove the obsolete base address, and always use the provided callbacks. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25pinctrl: mvebu: move resource allocation to SoC specific driversSebastian Hesselbarth5-16/+33
The way that mvebu pinctrl is designed, requesting mpp registers in common pinctrl driver does not allow SoC specific drivers to access this resource. Move resource allocation in each SoC pinctrl driver and enable already provided mpp_{set,get} callbacks. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25pinctrl: mvebu: armada-xp: provide generic mpp callbacksSebastian Hesselbarth1-0/+12
We want to get rid of passing register addresses to common pinctrl driver, so provide set/get callbacks that use generic mpp pins helper and will be used later. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25pinctrl: mvebu: armada-370: provide generic mpp callbacksSebastian Hesselbarth1-0/+12
We want to get rid of passing register addresses to common pinctrl driver, so provide set/get callbacks that use generic mpp pins helper and will be used later. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25pinctrl: mvebu: kirkwood: provide generic mpp callbacksSebastian Hesselbarth1-0/+12
We want to get rid of passing register addresses to common pinctrl driver, so provide set/get callbacks that use generic mpp pins helper and will be used later. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch>
2014-02-25pinctrl: mvebu: dove: provide generic mpp callbacksSebastian Hesselbarth1-14/+22
We want to get rid of passing register addresses to common pinctrl driver, so provide set/get callbacks that use generic mpp pins helper and will be used later. While at it, also make use of globally defined MPP macros. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-25pinctrl: mvebu: add common mpp reg helper to mvebu pinctrl includeSebastian Hesselbarth1-0/+28
This adds some defines and helper functions for the common mpp reg layout to mvebu pinctrl include. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch>
2014-02-25pinctrl: mvebu: remove passing mvebu_mpp_ctrl to callbacksSebastian Hesselbarth3-45/+32
The only valuable information a special callback can derive from mvebu_mpp_ctrl passed to it, is the pin id. Instead of passing the struct, pass the pid directly. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25pinctrl: mvebu: identify generic controls by nameSebastian Hesselbarth1-14/+16
We treat unnamed controls as generic mvebu mpp register controls but we identify them by not being special controls. Flip the logic and use the name pointer as identification instead. While at it, add some comments explaining the not so obvious treatment. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25pinctrl: mvebu: remove obsolete per-control name buffer allocationSebastian Hesselbarth1-9/+0
With the introduction of a global name buffer, we can now remove the allocation and preparation of per-control name buffers. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25pinctrl: mvebu: count unnamed controls and allocate name bufferSebastian Hesselbarth1-5/+19
pinctrl-mvebu allows SoCs to pass unnamed controls that will get an auto-generated name of "mpp<PIN#>". Currently, we are allocating name buffers on a per-control basis while looping over passed controls. This counts the total number of unnamed controls and allocates a global name buffer instead. The new buffer is then used while assigning controls to pinctrl groups later. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-02-25pinctrl: pfc: r8a7791: add mux data for IIC(B) coresWolfram Sang1-0/+64
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: at91: implement get_directionRichard Genoud1-0/+12
This is needed for gpiod_get_direction(). Otherwise, it returns -EINVAL. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: imx: Fix pin name in debug message.Martin Fuzzey1-1/+1
The wrong index counter was being used, causing the debug message to show an incorrect pin name. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl-sunxi: Fix sun5i-a13 port F multiplexingHans de Goede1-6/+6
The correct value for selecting the mmc0 function on port F pins is 2 not 4, as per the data-sheet: http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: pinctrl-adi: combine multiple groups of one function togetherSonic Zhang4-147/+139
The data pins of some peripheral are different if connecting to different devices in one pinmux function. In the PPI case, data pins can be used in 8, 16 and 24 pin groups individually. Add these groups into one ppi function. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: sirf: update copyright years to 2014Barry Song3-3/+6
Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: nomadik: Convert to modern pm_opsUlf Hansson1-8/+9
Use the SIMPLE_DEV_PM_OPS macro and convert to the modern pm ops. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: nomadik: Silence compiler warn for !CONFIG_PMUlf Hansson1-1/+3
The static suspend/resume functions were not being used while !CONFIG_PM. Fix it and convert to CONFIG_PM_SLEEP. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: sh-pfc: r8a7790: Add QSPI pin groupsGeert Uytterhoeven1-0/+33
A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl-msm: Add SPI8 pin definitionsIvan T. Ivanov1-4/+9
Add pin, group and function definitions for SPI#8 controller. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-24pinctrl: Quiet logging about missing DT nodes when not using DTMark Brown1-1/+3
On systems which were not booted using DT it is entirely unsurprising that device nodes don't have any DT information and this is going to happen for every single device in the system. Make pinctrl be less chatty about this situation by only logging in the case where we have DT. Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUSMagnus Damm1-0/+9
Create a new group for the USB0 OVC/VBUS pin by itself. This allows us to monitor PWEN as GPIO on the Lager board. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11pinctrl: exynos: add exynos5260 SoC specific dataYoung-Gun Jang3-0/+85
Adds pinctrl support for all platforms based on EXYNOS5260 SoC. Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11pinctrl-msm: Support output-{high,low} configurationBjorn Andersson1-0/+27
Add support for configuring pins as output with value as from the pinconf-generic interface. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl: sirf: add pin group for USP0 for atlas6Rongjun Ying1-0/+43
USP0 has multiple functions, and has RX and TX frame sync signals, for some scenarios like audio PCM, we don't need both of them. so here we add two possibilities for USP0 only holding one of TX and RX frame sync. commit 8385af02bad only added this group for prima2, and missed atlas6. This patch fixes it. Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl: single: add low power mode supportChao Xie1-0/+3
For some silicons, the pin configuration register can control the output of the pin when the pad including the pin enter low power mode. For example, the pin can be "Drive 1", "Drive 0", "Float" when the pad including the pin enter low power mode. It is very useful when you want to control the power leakeage when the SOC enter low power mode, and can save more power for the low power mode. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl-adi2: fix coding style issueSonic Zhang1-1/+1
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl-adi2: change irq_base from usigned int to intSonic Zhang1-1/+1
Negative irq_base means this gpio port doens't support interrupts. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl: Move pint PM storage structure out of blackfin architecture.Sonic Zhang1-1/+14
It is better to keep this structure in the pinctrl-adi2 driver. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl: at91: use gpiolib API to mark a GPIO used as an IRQJean-Jacques Hiblot1-0/+27
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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