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path: root/drivers/spi/spi-sun4i.c
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2016-10-29spi: sun4i: Allow transfers larger than FIFO sizeAlexandru Gagniuc1-8/+67
SPI transfers were limited to one FIFO depth, which is 64 bytes. This was an artificial limitation, however, as the hardware can handle much larger bursts. To accommodate this, we enable the interrupt when the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt handler. The 3/4 ratio was chosen arbitrarily, with the intention to reduce the potential number of interrupts. Since the SUN4I_CTL_TP bit is set, the hardware will pause transmission whenever the FIFO is full, so there is no risk of losing data if we can't service the interrupt in time. For the Tx side, enable and use the Tx FIFO 3/4 empty interrupt to replenish the FIFO on large SPI bursts. This requires more care in when the interrupt is left enabled, as this interrupt will continually trigger when the FIFO is less than 1/4 full, even though we acknowledge it. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-07-25Merge remote-tracking branches 'spi/topic/spidev', 'spi/topic/sunxi', ↵Mark Brown1-0/+8
'spi/topic/ti-qspi', 'spi/topic/topcliff-pch' and 'spi/topic/txx9' into spi-next
2016-06-27spi: sunxi: set maximum and minimum speed of SPI masterMichal Suchanek1-0/+2
The speed limits are unset in the sun4i and sun6i SPI drivers. The maximum speed of SPI master is used when maximum speed of SPI slave is not specified. Also the __spi_validate function should check that transfer speeds do not exceed the master limits. The user manual for A10 and A31 specifies maximum speed of the SPI clock as 100MHz and minimum as 3kHz. Setting the SPI clock to out-of-spec values can lock up the SoC. Signed-off-by: Michal Suchanek <hramrach@gmail.com> -- v2: new patch v3: fix constant style Signed-off-by: Mark Brown <broonie@kernel.org>
2016-06-14spi: sunxi: fix transfer timeoutMichal Suchanek1-1/+9
The trasfer timeout is fixed at 1000 ms. Reading a 4Mbyte flash over 1MHz SPI bus takes way longer than that. Calculate the timeout from the actual time the transfer is supposed to take and multiply by 2 for good measure. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2016-06-14spi: sun4i: fix FIFO limitMichal Suchanek1-3/+10
When testing SPI without DMA I noticed that filling the FIFO on the spi controller causes timeout. Always leave room for one byte in the FIFO. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2016-06-14spi: sunxi: expose maximum transfer size limitMichal Suchanek1-0/+6
The sun4i spi hardware can trasfer at most 63 bytes of data without DMA support so report the limitation. Same for sun6i. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-01-11Merge remote-tracking branches 'spi/topic/sun4i', 'spi/topic/topcliff-pch' ↵Mark Brown1-4/+4
and 'spi/topic/zynq' into spi-next
2016-01-07spi: sun4i: Prevent chip-select from being activated twice before a transferMarcus Weseloh1-3/+3
The SPI core calls set_cs before a transfer, but the SUN4I_CTL_CS_MANUAL flag is only set in transfer_one. This leads to the following pattern on the chip-select line (with runtime power-management on every transfer, without it only on the first one): activate, deactivate, activate, transfer, deactivate Moving the configuration of the SUN4I_CTL_CS_MANUAL flag from transfer_one to set_cs removes the double activation. Signed-off-by: Marcus Weseloh <mweseloh42@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-18spi: sun4i: allow transfers to set transmission speedMarcus Weseloh1-4/+4
Allow transfers to set the transmission speed rather than using the device max_speed_hz value. The SPI core makes sure that the speed_hz value is always set on the transfer. Signed-off-by: Marcus Weseloh <mweseloh42@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20spi: drop owner assignment from platform_driversWolfram Sang1-1/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-04-14spi: Remove unneeded include of linux/workqueue.hAxel Lin1-1/+0
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-03-04spi: sun4i: Set bits_per_word_mask to only support 8 bits word lengthAxel Lin1-0/+1
This controller only supports 8 bits word length. Set bits_per_word_mask so spi core will reject transfers that attempt to use an unsupported bits_per_word value. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-23spi: sunxi: Add Allwinner A10 SPI controller driverMaxime Ripard1-0/+477
The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI controller. Unfortunately, this SPI controller, even though quite similar, is significantly different from the recently supported A31 SPI controller (different registers offset, split/merged registers, etc.). Supporting both controllers in a single driver would be unreasonable, hence the addition of a new driver. Like its more recent counterpart, it supports DMA, but the driver only does PIO until we have a dmaengine driver for this platform. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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