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2023-01-06soc: qcom: dcc: Fix unsigned comparison with less than zeroYang Li1-1/+2
The return value from the call to kstrtouint_from_user() is int. However, the return value is being assigned to an unsigned int variable 'ret', so making 'ret' an int. Eliminate the following warning: ./drivers/soc/qcom/dcc.c:815:5-8: WARNING: Unsigned expression compared with zero: ret < 0 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3638 Fixes: 4cbe60cf5ad6 ("soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)") Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106011710.2827-1-yang.lee@linux.alibaba.com
2023-01-06soc: qcom: apr: Make qcom,protection-domain optional againStephan Gerhold1-1/+2
APR should not fail if the service device tree node does not have the qcom,protection-domain property, since this functionality does not exist on older platforms such as MSM8916 and MSM8996. Ignore -EINVAL (returned when the property does not exist) to fix a regression on 6.2-rc1 that prevents audio from working: qcom,apr remoteproc0:smd-edge.apr_audio_svc.-1.-1: Failed to read second value of qcom,protection-domain qcom,apr remoteproc0:smd-edge.apr_audio_svc.-1.-1: Failed to add apr 3 svc Fixes: 6d7860f5750d ("soc: qcom: apr: Add check for idr_alloc and of_property_read_string_index") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229151648.19839-3-stephan@gerhold.net
2023-01-05firmware: xilinx: Remove kernel-doc marking in the codeMichal Simek1-1/+1
Trivial fix. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f4c61cd5e45fab345c366a15766101408fbc3bcd.1670502727.git.michal.simek@amd.com
2023-01-05driver: soc: xilinx: fix memory leak in xlnx_add_cb_for_notify_event()Gaosheng Cui1-1/+3
The kfree() should be called when memory fails to be allocated for cb_data in xlnx_add_cb_for_notify_event(), otherwise there will be a memory leak, so add kfree() to fix it. Fixes: 05e5ba40ea7a ("driver: soc: xilinx: Add support of multiple callbacks for same event in event management driver") Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221129010146.1026685-1-cuigaosheng1@huawei.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-01-02soc: imx8m: Fix incorrect check for of_clk_get_by_name()Miaoqian Lin1-2/+2
of_clk_get_by_name() returns error pointers instead of NULL. Use IS_ERR() checks the return value to catch errors. Fixes: 836fb30949d9 ("soc: imx8m: Enable OCOTP clock before reading the register") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-01-02soc: amlogic: meson-pwrc: Add NNA power domain for A311DTomeu Vizoso1-0/+17
Based on power initialization sequence in downstream driver. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20221202115223.39051-4-tomeu.vizoso@collabora.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-01soc: imx: imx93-src: No need to set device_driver ownerDeepak R Varma1-1/+0
There is no need to exclusively set the .owner member of the struct device_driver when defining the platform_driver struct. The Linux core takes care of setting the .owner member as part of the call to module_platform_driver() helper function. Issue identified using the platform_no_drv_owner.cocci Coccinelle semantic patch. Signed-off-by: Deepak R Varma <drv@mailo.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-01-01soc: imx: imx93-pd: No need to set device_driver ownerDeepak R Varma1-1/+0
There is no need to exclusively set the .owner member of the struct device_driver when defining the platform_driver struct. The Linux core takes care of setting the .owner member as part of the call to module_platform_driver() helper function. Issue identified using the platform_no_drv_owner.cocci Coccinelle semantic patch. Signed-off-by: Deepak R Varma <drv@mailo.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-01-01soc: imx: imx8m-blk-ctrl: set LCDIF panic read hurry levelLucas Stach1-6/+21
When the LCDIF block signals a panic condition due to the display FIFO falling below the threshold, the priority at the NoC level is boosted to the value set in the LCDIF_ARCACHE_CTRL register of i.MX8MP mediamix blk-ctrl. Same as all other blk-ctrl registers this register is reset when the domain is powered down. Initialize the panic hurry levels for both LCIF interfaces to the maximium priority (same as downstream TF-A and proven to work with the other priorities set in the interconnect driver) when coming back from power down. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-01-01soc: imx: imx8mp-blk-ctrl: don't set power device nameLucas Stach1-1/+0
Setting the device name after it has been registered confuses the sysfs cleanup paths. This has already been fixed for the imx8m-blk-ctrl driver in b64b46fbaa1d ("Revert "soc: imx: imx8m-blk-ctrl: set power device name""), but the same problem exists in imx8mp-blk-ctrl. Fixes: 556f5cf9568a ("soc: imx: add i.MX8MP HSIO blk-ctrl") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-01-01soc: imx: imx8mp-blk-ctrl: expose high performance PLL clockLucas Stach2-0/+99
Expose the high performance PLL as a regular Linux clock, so the PCIe PHY can use it when there is no external refclock provided. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Lukas F. Hartmann <lukas@mntre.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-01-01soc: imx: imx8mp-blk-ctrl: add instance specific probe functionLucas Stach1-0/+7
Allow the specific blk-ctrl instance to define a function, which will be called during probe to provide device specific extensions. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Lukas F. Hartmann <lukas@mntre.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-01-01soc: imx: add Kconfig symbols for blk-ctrl driversLucas Stach2-3/+13
Currently the dependencies of the blk-ctrl drivers are not fully described in Kconfig, which can trip over the compile tests on platforms where those drivers are not usually enabled. Add a non user-selectable symbol to be describe those dependencies. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-12-31soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PDLucas Stach1-2/+4
NXP internal information shows that the PHY refclk is gated by the GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the LCDIF being already active, tie this bit to the HDMI_TX_PHY power domain. Fixes: e3442022f543 ("soc: imx: add i.MX8MP HDMI blk-ctrl") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-12-29soc: qcom: socinfo: Add support for new fields in revision 16Naman Jain1-0/+16
Add support for new fields coming with socinfo structure under v16 to get SKU information, product code and name and type of different parts present in the SoC. Also, add debugfs nodes to read feature and product codes to allow user to get SKU and other SoC details. Support for SoC parts name and type parsing will be added separately. Details of fields added: * feature_code: mapped to qcom internal and external SKU IDs * pcode: product code * npartnamemap_offset: parts name map array offset from socinfo base ptr * nnum_partname_mapping: number of part mappings Signed-off-by: Naman Jain <quic_namajain@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221125103533.2960-1-quic_namajain@quicinc.com
2022-12-28soc: qcom: ramp_controller: Include linux/bitfield.hBjorn Andersson1-0/+1
Building ramp_controller under x86_64 results in the following build error: error: implicit declaration of function 'FIELD_PREP' is invalid in C99 Include linux/bitfield.h to ensure FIELD_PREP() is declared. Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2022-12-28soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)Souradeep Chowdhury3-0/+1308
The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the dcc sram. In case of a system crash or a manual software trigger by the user through the debugfs interface, the dcc captures and stores the values at these addresses. This patch contains the driver which has all the methods pertaining to the debugfs interface, auxiliary functions to support all the four fundamental operations of dcc namely read, write, read/modify/write and loop. The probe method here instantiates all the resources necessary for dcc to operate mainly the dedicated dcc sram where it stores the values. The DCC driver can be used for debugging purposes without going for a reboot since it can perform software triggers as well based on user inputs. Also add the documentation for debugfs entries which explains the functionalities of each debugfs file that has been created for dcc. The following is the justification of using debugfs interface over the other alternatives like sysfs/ioctls i) As can be seen from the debugfs attribute descriptions, some of the debugfs attribute files here contains multiple arguments which needs to be accepted from the user. This goes against the design style of sysfs. ii) The user input patterns have been made simple and convenient in this case with the use of debugfs interface as user doesn't need to shuffle between different files to execute one instruction as was the case on using other alternatives. Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com> Reviewed-by: Alex Elder <elder@linaro.org> [bjorn: Fixed up a few indents and line wraps] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/644b4f66a358492a8a6738454035c3b120092fe7.1672148732.git.quic_schowdhu@quicinc.com
2022-12-27soc: qcom: Add Qualcomm Ramp Controller driverAngeloGioacchino Del Regno3-0/+352
The Ramp Controller is used to program the sequence ID for pulse swallowing, enable sequence and linking sequence IDs for the CPU cores on some Qualcomm SoCs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221117132956.169432-3-angelogioacchino.delregno@collabora.com
2022-12-27soc: sifive: ccache: Add StarFive JH7110 supportEmil Renner Berthing2-2/+2
This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-12-26soc: renesas: r8a779g0-sysc: Add missing A3DUL power domainTam Nguyen1-0/+1
Add the power domain structure for the A3DUL domain (PAP-Subsystem), as described in the R-Car V4H Series Hardware User's Manual Rev. 0.51 and later. Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> [geert: Manual reference] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/14bd8a8de16ced703ff824f6a241e89d1ead6b07.1669740926.git.geert+renesas@glider.be
2022-12-20Merge tag 'soc-fixes-6.2-1' of ↵Linus Torvalds2-1/+4
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd Bergmann: "These are a couple of build fixes from randconfig testing, plus a set of Mediatek SoC specific fixes, all trivial" * tag 'soc-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: soc: tegra: fix CPU_BIG_ENDIAN dependencies ARM: disallow pre-ARMv5 builds with ld.lld ARM: pxa: fix building with clang MAINTAINERS: add related dts to IXP4xx ARM: dts: spear: drop 0x from unit address arm64: dts: mt8183: Fix Mali GPU clock arm64: dts: mediatek: mt8195-demo: fix the memory size of node secmon soc: mediatek: pm-domains: Fix the power glitch issue
2022-12-19Merge tag 'v6.1-soc-fixes' of ↵Arnd Bergmann1-1/+1
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/fixes PM domains: enable isolation before resetting power * tag 'v6.1-soc-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: pm-domains: Fix the power glitch issue Link: https://lore.kernel.org/r/29c8b913-53cf-096f-fe44-832ceaeac116@suse.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-19soc: tegra: fix CPU_BIG_ENDIAN dependenciesArnd Bergmann1-0/+3
My previous patch to prevent BPMP from being enabled on big endian kernels caused a build regression: WARNING: unmet direct dependencies detected for TEGRA_BPMP Depends on [n]: ARCH_TEGRA [=y] && TEGRA_HSP_MBOX [=y] && TEGRA_IVC [=y] && !CPU_BIG_ENDIAN [=y] Selected by [y]: - ARCH_TEGRA_186_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] - ARCH_TEGRA_194_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] - ARCH_TEGRA_234_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] Add even more such dependencies for the SoC types that use the BPMP driver. Fixes: 4ddb1bf1a837 ("tegra: mark BPMP driver as little-endian only") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221215165336.1781080-1-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-16soc: mediatek: pm-domains: Fix the power glitch issueChun-Jie Chen1-1/+1
Power reset maybe generate unexpected signal. In order to avoid the glitch issue, we need to enable isolation first to guarantee the stable signal when power reset is triggered. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221014102029.1162-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-12-16Merge tag 'i2c-for-6.2-rc1' of ↵Linus Torvalds1-14/+65
git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux Pull i2c updates from Wolfram Sang: "Core got a new helper 'i2c_client_get_device_id()', designware got some bigger updates, the rest is driver updates all over the place" * tag 'i2c-for-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (41 commits) i2c: ismt: Fix an out-of-bounds bug in ismt_access() i2c: mux: reg: check return value after calling platform_get_resource() i2c: xiic: Make sure to disable clock on .remove() i2c: hisi: Add support to get clock frequency from clock i2c: pxa-pci: fix missing pci_disable_device() on error in ce4100_i2c_probe i2c: slave-eeprom: Convert to i2c's .probe_new() i2c: mux: pca954x: Convert to i2c's .probe_new() drivers/i2c: use simple i2c probe i2c: mux: pca9541: switch to using .probe_new i2c: gpio: Fix potential unused warning for 'i2c_gpio_dt_ids' i2c: qcom-geni: add support for I2C Master Hub variant i2c: qcom-geni: add desc struct to prepare support for I2C Master Hub variant soc: qcom: geni-se: add support for I2C Master Hub wrapper variant soc: qcom: geni-se: add desc struct to specify clocks from device match data dt-bindings: i2c: qcom-geni: document I2C Master Hub serial I2C engine dt-bindings: qcom: geni-se: document I2C Master Hub wrapper variant dt-bindings: i2c: renesas,riic: Document RZ/Five SoC i2c: tegra: Set ACPI node as primary fwnode i2c: smbus: add DDR support for SPD i2c: /pasemi: PASemi I2C controller IRQ enablement ...
2022-12-14Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds2-1/+1
Pull ARM updates from Russell King: - update unwinder to cope with module PLTs - enable UBSAN on ARM - improve kernel fault message - update UEFI runtime page tables dump - avoid clang's __aeabi_uldivmod generated in NWFPE code - disable FIQs on CPU shutdown paths - update XOR register usage - a number of build updates (using .arch, thread pointer, removal of lazy evaluation in Makefile) - conversion of stacktrace code to stackwalk - findbit assembly updates - hwcap feature updates for ARMv8 CPUs - instruction dump updates for big-endian platforms - support for function error injection * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (31 commits) ARM: 9279/1: support function error injection ARM: 9277/1: Make the dumped instructions are consistent with the disassembled ones ARM: 9276/1: Refactor dump_instr() ARM: 9275/1: Drop '-mthumb' from AFLAGS_ISA ARM: 9274/1: Add hwcap for Speculative Store Bypassing Safe ARM: 9273/1: Add hwcap for Speculation Barrier(SB) ARM: 9272/1: vfp: Add hwcap for FEAT_AA32I8MM ARM: 9271/1: vfp: Add hwcap for FEAT_AA32BF16 ARM: 9270/1: vfp: Add hwcap for FEAT_FHM ARM: 9269/1: vfp: Add hwcap for FEAT_DotProd ARM: 9268/1: vfp: Add hwcap FPHP and ASIMDHP for FEAT_FP16 ARM: 9267/1: Define Armv8 registers in AArch32 state ARM: findbit: add unwinder information ARM: findbit: operate by words ARM: findbit: convert to macros ARM: findbit: provide more efficient ARMv7 implementation ARM: findbit: document ARMv5 bit offset calculation ARM: 9259/1: stacktrace: Convert stacktrace to generic ARCH_STACKWALK ARM: 9258/1: stacktrace: Make stack walk callback consistent with generic code ARM: 9265/1: pass -march= only to compiler ...
2022-12-14Merge tag 'pinctrl-v6.2-1' of ↵Linus Torvalds1-1/+3
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "The two large chunks is the header clean-up from Andy and the Qualcomm DT bindings clean-up from Krzysztof. Each which could give rise to conflicts, but I haven't seen any. The YAML conversions happening around the device tree is the biggest item in the series and is the result of Rob Herrings ambition to autovalidate these trees against strict schemas and it is paying off in lots of bugs found and ever prettier device trees. Sooner or later the transition will be complete, Krzysztof is fixing up all of the Qualcomm stuff, which is pretty voluminous. Core changes: - minor but nice and important documentation clean-ups New drivers: - subdriver for the Qualcomm SDM670 SoC - subdriver for the Intel Moorefield SoC - trivial support for the NXP Freescale i.MXRT1170 SoC Other changes and improvements - major clean-up of the Qualcomm pin control device tree bindings by Krzysztof - major header clean-up by Andy - some immutable irqchip clean-up for the Actions Semiconductor and Nuvoton drivers - GPIO helpers for The Cypress cy8c95x0 driver - bias handling in the Mediatek MT7986 driver - remove the unused pins-are-numbered concept that never flew" * tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits) pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions() dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered pinctrl: stm32: Remove check for pins-are-numbered pinctrl: mediatek: common: Remove check for pins-are-numbered pinctrl: qcom: remove duplicate included header files pinctrl: sunxi: d1: Add CAN bus pinmuxes pinctrl: loongson2: Fix some const correctness pinctrl: pinconf-generic: add missing of_node_put() pinctrl: intel: Enumerate PWM device when community has a capability pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() pwm: lpss: Allow other drivers to enable PWM LPSS pwm: lpss: Include headers we are the direct user of pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS pwm: Add a stub for devm_pwmchip_add() pinctrl: k210: call of_node_put() pinctrl: starfive: Use existing variable gpio dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching pinconf-generic: fix style issues in pin_config_param doc pinctrl: pinctrl-loongson2: fix Kconfig dependency ...
2022-12-12Merge tag 'irq-core-2022-12-10' of ↵Linus Torvalds3-10/+5
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "Updates for the interrupt core and driver subsystem: The bulk is the rework of the MSI subsystem to support per device MSI interrupt domains. This solves conceptual problems of the current PCI/MSI design which are in the way of providing support for PCI/MSI[-X] and the upcoming PCI/IMS mechanism on the same device. IMS (Interrupt Message Store] is a new specification which allows device manufactures to provide implementation defined storage for MSI messages (as opposed to PCI/MSI and PCI/MSI-X that has a specified message store which is uniform accross all devices). The PCI/MSI[-X] uniformity allowed us to get away with "global" PCI/MSI domains. IMS not only allows to overcome the size limitations of the MSI-X table, but also gives the device manufacturer the freedom to store the message in arbitrary places, even in host memory which is shared with the device. There have been several attempts to glue this into the current MSI code, but after lengthy discussions it turned out that there is a fundamental design problem in the current PCI/MSI-X implementation. This needs some historical background. When PCI/MSI[-X] support was added around 2003, interrupt management was completely different from what we have today in the actively developed architectures. Interrupt management was completely architecture specific and while there were attempts to create common infrastructure the commonalities were rudimentary and just providing shared data structures and interfaces so that drivers could be written in an architecture agnostic way. The initial PCI/MSI[-X] support obviously plugged into this model which resulted in some basic shared infrastructure in the PCI core code for setting up MSI descriptors, which are a pure software construct for holding data relevant for a particular MSI interrupt, but the actual association to Linux interrupts was completely architecture specific. This model is still supported today to keep museum architectures and notorious stragglers alive. In 2013 Intel tried to add support for hot-pluggable IO/APICs to the kernel, which was creating yet another architecture specific mechanism and resulted in an unholy mess on top of the existing horrors of x86 interrupt handling. The x86 interrupt management code was already an incomprehensible maze of indirections between the CPU vector management, interrupt remapping and the actual IO/APIC and PCI/MSI[-X] implementation. At roughly the same time ARM struggled with the ever growing SoC specific extensions which were glued on top of the architected GIC interrupt controller. This resulted in a fundamental redesign of interrupt management and provided the today prevailing concept of hierarchical interrupt domains. This allowed to disentangle the interactions between x86 vector domain and interrupt remapping and also allowed ARM to handle the zoo of SoC specific interrupt components in a sane way. The concept of hierarchical interrupt domains aims to encapsulate the functionality of particular IP blocks which are involved in interrupt delivery so that they become extensible and pluggable. The X86 encapsulation looks like this: |--- device 1 [Vector]---[Remapping]---[PCI/MSI]--|... |--- device N where the remapping domain is an optional component and in case that it is not available the PCI/MSI[-X] domains have the vector domain as their parent. This reduced the required interaction between the domains pretty much to the initialization phase where it is obviously required to establish the proper parent relation ship in the components of the hierarchy. While in most cases the model is strictly representing the chain of IP blocks and abstracting them so they can be plugged together to form a hierarchy, the design stopped short on PCI/MSI[-X]. Looking at the hardware it's clear that the actual PCI/MSI[-X] interrupt controller is not a global entity, but strict a per PCI device entity. Here we took a short cut on the hierarchical model and went for the easy solution of providing "global" PCI/MSI domains which was possible because the PCI/MSI[-X] handling is uniform across the devices. This also allowed to keep the existing PCI/MSI[-X] infrastructure mostly unchanged which in turn made it simple to keep the existing architecture specific management alive. A similar problem was created in the ARM world with support for IP block specific message storage. Instead of going all the way to stack a IP block specific domain on top of the generic MSI domain this ended in a construct which provides a "global" platform MSI domain which allows overriding the irq_write_msi_msg() callback per allocation. In course of the lengthy discussions we identified other abuse of the MSI infrastructure in wireless drivers, NTB etc. where support for implementation specific message storage was just mindlessly glued into the existing infrastructure. Some of this just works by chance on particular platforms but will fail in hard to diagnose ways when the driver is used on platforms where the underlying MSI interrupt management code does not expect the creative abuse. Another shortcoming of today's PCI/MSI-X support is the inability to allocate or free individual vectors after the initial enablement of MSI-X. This results in an works by chance implementation of VFIO (PCI pass-through) where interrupts on the host side are not set up upfront to avoid resource exhaustion. They are expanded at run-time when the guest actually tries to use them. The way how this is implemented is that the host disables MSI-X and then re-enables it with a larger number of vectors again. That works by chance because most device drivers set up all interrupts before the device actually will utilize them. But that's not universally true because some drivers allocate a large enough number of vectors but do not utilize them until it's actually required, e.g. for acceleration support. But at that point other interrupts of the device might be in active use and the MSI-X disable/enable dance can just result in losing interrupts and therefore hard to diagnose subtle problems. Last but not least the "global" PCI/MSI-X domain approach prevents to utilize PCI/MSI[-X] and PCI/IMS on the same device due to the fact that IMS is not longer providing a uniform storage and configuration model. The solution to this is to implement the missing step and switch from global PCI/MSI domains to per device PCI/MSI domains. The resulting hierarchy then looks like this: |--- [PCI/MSI] device 1 [Vector]---[Remapping]---|... |--- [PCI/MSI] device N which in turn allows to provide support for multiple domains per device: |--- [PCI/MSI] device 1 |--- [PCI/IMS] device 1 [Vector]---[Remapping]---|... |--- [PCI/MSI] device N |--- [PCI/IMS] device N This work converts the MSI and PCI/MSI core and the x86 interrupt domains to the new model, provides new interfaces for post-enable allocation/free of MSI-X interrupts and the base framework for PCI/IMS. PCI/IMS has been verified with the work in progress IDXD driver. There is work in progress to convert ARM over which will replace the platform MSI train-wreck. The cleanup of VFIO, NTB and other creative "solutions" are in the works as well. Drivers: - Updates for the LoongArch interrupt chip drivers - Support for MTK CIRQv2 - The usual small fixes and updates all over the place" * tag 'irq-core-2022-12-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (134 commits) irqchip/ti-sci-inta: Fix kernel doc irqchip/gic-v2m: Mark a few functions __init irqchip/gic-v2m: Include arm-gic-common.h irqchip/irq-mvebu-icu: Fix works by chance pointer assignment iommu/amd: Enable PCI/IMS iommu/vt-d: Enable PCI/IMS x86/apic/msi: Enable PCI/IMS PCI/MSI: Provide pci_ims_alloc/free_irq() PCI/MSI: Provide IMS (Interrupt Message Store) support genirq/msi: Provide constants for PCI/IMS support x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X PCI/MSI: Provide prepare_desc() MSI domain op PCI/MSI: Split MSI-X descriptor setup genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN genirq/msi: Provide msi_domain_alloc_irq_at() genirq/msi: Provide msi_domain_ops:: Prepare_desc() genirq/msi: Provide msi_desc:: Msi_data genirq/msi: Provide struct msi_map x86/apic/msi: Remove arch_create_remap_msi_irq_domain() ...
2022-12-12Merge tag 'soc-drivers-6.2' of ↵Linus Torvalds47-900/+2337
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "There are few major updates in the SoC specific drivers, mainly the usual reworks and support for variants of the existing SoC. While this remains Arm centric for the most part, the branch now also contains updates to risc-v and loongarch specific code in drivers/soc/. Notable changes include: - Support for the newly added Qualcomm Snapdragon variants (MSM8956, MSM8976, SM6115, SM4250, SM8150, SA8155 and SM8550) in the soc ID, rpmh, rpm, spm and powerdomain drivers. - Documentation for the somewhat controversial qcom,board-id properties that are required for booting a number of machines - A new SoC identification driver for the loongson-2 (loongarch) platform - memory controller updates for stm32, tegra, and renesas. - a new DT binding to better describe LPDDR2/3/4/5 chips in the memory controller subsystem - Updates for Tegra specific drivers across multiple subsystems, improving support for newer SoCs and better identification - Minor fixes for Broadcom, Freescale, Apple, Renesas, Sifive, TI, Mediatek and Marvell SoC drivers" * tag 'soc-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (137 commits) soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variants soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155 dt-bindings: soc: qcom: apr: document generic qcom,apr compatible soc: qcom: Select REMAP_MMIO for ICC_BWMON driver soc: qcom: Select REMAP_MMIO for LLCC driver soc: qcom: rpmpd: Add SM4250 support dt-bindings: power: rpmpd: Add SM4250 support dt-bindings: soc: qcom: aoss: Add compatible for SM8550 soc: qcom: llcc: Add configuration data for SM8550 dt-bindings: arm: msm: Add LLCC compatible for SM8550 soc: qcom: llcc: Add v4.1 HW version support soc: qcom: socinfo: Add SM8550 ID soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done response soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets soc: qcom: rpmhpd: Add SM8550 power domains dt-bindings: power: rpmpd: Add SM8550 to rpmpd binding soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976 ...
2022-12-12Merge tag 'soc-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2-6/+6
Pull ARM SoC code updates from Arnd Bergmann: "This time there are only fairly minor cleanups across the i.MX, ixp4xx, ux500 and renesas platforms. The only notable update is a change to the keystone2 platform to switch switch it over to standard PSCI SMP bringup, which apparently was present in the shipped firmware almost from the start" * tag 'soc-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: ixp4xx: Remove unused debug iomap MAINTAINERS: Add DHCOR to the DH electronic i.MX6 board support ARM: ixp4xx: Remove unused static map MAINTAINERS: adjust ARM/INTEL IXP4XX ARM ARCHITECTURE to ixp4xx clean-up ARM: imx3: Remove unneeded #include <linux/pinctrl/machine.h> ARM: mxs: Remove unneeded #include <linux/pinctrl/consumer.h> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option ARM: ux500: Drop unused register file ARM: ux500: do not directly dereference __iomem arm/mach-ux500: fix repeated words in comments arm64: renesas: Drop selecting GPIOLIB and PINCTRL ARM: shmobile: Drop selecting GPIOLIB and PINCTRL ARM: keystone: Replace platform SMP with PSCI soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS
2022-12-08Merge tag 'qcom-drivers-for-6.2-2' of ↵Arnd Bergmann9-101/+331
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers More Qualcomm driver updates for 6.2 Socinfo is extended with knowledge about MSM8956, MSM8976, SM6115, SM4250, SM8150, SA8155 and SM8550. Support for RSC v3, as found in SM8550 is added to the RPMH RSC driver. Support for SM8550 and SM4250 ARC regulators are added to the RPM(h) power-domain drivers. SM8550 support is added to the LLCC driver. The AOSS QMP binding is declared compatible for SM8550. BWMON and LLCC now selects REGMAP_MMIO to ensure dependencies are built properly. * tag 'qcom-drivers-for-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variants soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155 dt-bindings: soc: qcom: apr: document generic qcom,apr compatible soc: qcom: Select REMAP_MMIO for ICC_BWMON driver soc: qcom: Select REMAP_MMIO for LLCC driver soc: qcom: rpmpd: Add SM4250 support dt-bindings: power: rpmpd: Add SM4250 support dt-bindings: soc: qcom: aoss: Add compatible for SM8550 soc: qcom: llcc: Add configuration data for SM8550 dt-bindings: arm: msm: Add LLCC compatible for SM8550 soc: qcom: llcc: Add v4.1 HW version support soc: qcom: socinfo: Add SM8550 ID soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done response soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets soc: qcom: rpmhpd: Add SM8550 power domains dt-bindings: power: rpmpd: Add SM8550 to rpmpd binding soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976 Link: https://lore.kernel.org/r/20221207154134.3233779-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-06soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id tableBhupesh Sharma1-0/+4
Add SoC ID table entries for the SM6115 / SM4250 and variants. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-5-bhupesh.sharma@linaro.org
2022-12-06soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id tableBhupesh Sharma1-0/+2
Add SoC ID table entries for the SM8150 and SA8155 SoCs. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-3-bhupesh.sharma@linaro.org
2022-12-06soc: qcom: Select REMAP_MMIO for ICC_BWMON driverManivannan Sadhasivam1-0/+1
ICC_BWMON driver uses REGMAP_MMIO for accessing the hardware registers. So select the dependency in Kconfig. Without this, there will be errors while building the driver with COMPILE_TEST only: ERROR: modpost: "__devm_regmap_init_mmio_clk" [drivers/soc/qcom/icc-bwmon.ko] undefined! make[1]: *** [scripts/Makefile.modpost:126: Module.symvers] Error 1 make: *** [Makefile:1944: modpost] Error 2 Cc: <stable@vger.kernel.org> # 6.0 Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Fixes: b9c2ae6cac40 ("soc: qcom: icc-bwmon: Add bandwidth monitoring driver") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221129072022.41962-1-manivannan.sadhasivam@linaro.org
2022-12-06soc: qcom: Select REMAP_MMIO for LLCC driverManivannan Sadhasivam1-0/+1
LLCC driver uses REGMAP_MMIO for accessing the hardware registers. So select the dependency in Kconfig. Without this, there will be errors while building the driver with COMPILE_TEST only: ERROR: modpost: "__devm_regmap_init_mmio_clk" [drivers/soc/qcom/llcc-qcom.ko] undefined! make[1]: *** [scripts/Makefile.modpost:126: Module.symvers] Error 1 make: *** [Makefile:1944: modpost] Error 2 Cc: <stable@vger.kernel.org> # 4.19 Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Reported-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221129071201.30024-2-manivannan.sadhasivam@linaro.org
2022-12-06soc: qcom: rpmpd: Add SM4250 supportBhupesh Sharma1-0/+18
SM4250 has the same RPM power domains as SM6115. Add SM4250 support by reusing SM6115 power domains. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221127112204.1486337-3-bhupesh.sharma@linaro.org
2022-12-06soc: qcom: llcc: Add configuration data for SM8550Abel Vesa1-0/+41
Add LLCC configuration data for SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113005.2653284-4-abel.vesa@linaro.org
2022-12-06soc: qcom: llcc: Add v4.1 HW version supportAbel Vesa1-7/+118
The LLCC found in SM8550 supports more slice configuration knobs and HW block version has been bumped up to 4.1. Add support for the new version and make sure the new config values are programed on probe. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113005.2653284-2-abel.vesa@linaro.org
2022-12-06soc: qcom: socinfo: Add SM8550 IDAbel Vesa1-0/+1
Add the ID for the Qualcomm SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112438.2643607-1-abel.vesa@linaro.org
2022-12-06soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done responseAbel Vesa4-37/+10
The RSC interrupt is issued only after the request is complete. For fire-n-forget requests, the irq-done interrupt is sent after issuing the RPMH request and for response-required request, the interrupt is triggered only after all the requests are complete. These unnecessary checks in the interrupt handler issues AHB reads from a critical path. Lets remove them and clean up error handling in rpmh_request data structures. Co-developed-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112246.2640648-2-abel.vesa@linaro.org
2022-12-06soc: qcom: rpmh-rsc: Add support for RSC v3 register offsetsAbel Vesa2-58/+110
The SM8550 RSC has a new set of register offsets due to its version bump. So read the version from HW and use the proper register offsets based on that. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112246.2640648-1-abel.vesa@linaro.org
2022-12-06soc: qcom: rpmhpd: Add SM8550 power domainsAbel Vesa1-0/+24
Add the power domains exposed by RPMH in the Qualcomm SM8550 platform. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116111745.2633074-3-abel.vesa@linaro.org
2022-12-05soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id tableAngeloGioacchino Del Regno1-0/+2
Add SoC ID table entries for MSM8956 and MSM8976 chips. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-8-angelogioacchino.delregno@collabora.com
2022-12-05oc: ti: ti_sci_inta_msi: Switch to domain id aware MSI functionsAhmed S. Darwish1-6/+2
Switch to the new domain id aware interfaces to phase out the previous ones. Remove the domain check as it happens in the core code now. No functional change. Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221124230314.634800247@linutronix.de
2022-12-05genirq/msi: Rename msi_add_msi_desc() to msi_insert_msi_desc()Thomas Gleixner1-2/+2
This reflects the functionality better. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221124230314.103554618@linutronix.de
2022-12-05soc: fsl: qe: request pins non-exclusivelyDmitry Torokhov1-27/+24
Commit 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") changed qe_pin_request() to request and hold GPIO corresponding to a given pin. Unfortunately this does not work, as fhci-hcd requests these GPIOs first, befor calling qe_pin_request() (see drivers/usb/host/fhci-hcd.c::of_fhci_probe()). To fix it change qe_pin_request() to request GPIOs non-exclusively, and free them once the code determines GPIO controller and offset for each GPIO/pin. Also reaching deep into gpiolib implementation is not the best idea. We should either export gpio_chip_hwgpio() or keep converting to the global gpio numbers space until we fix the driver to implement proper pin control. Fixes: 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/Y400YXnWBdz1e/L5@google.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-05soc: qcom: geni-se: add support for I2C Master Hub wrapper variantNeil Armstrong1-0/+10
The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Add the clock list for the I2C Master Hub variant to a new desc struct then pass it through the I2C Master Hub compatible match data. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-12-05soc: qcom: geni-se: add desc struct to specify clocks from device match dataNeil Armstrong1-14/+55
The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Prepare support for the I2C Master Hub variant by moving the required clocks list to a new desc struct then passing it through the compatible match data. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-12-04pxa: Remove dev_err() after platform_get_irq()zhang songyi1-3/+1
There is no need to call the dev_err() function directly to print a custom message when handling an error from either the platform_get_irq() or platform_get_irq_byname() functions as both are going to display an appropriate error message in case of a failure. Signed-off-by: zhang songyi <zhang.songyi@zte.com.cn> Reviewed-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/202212021042043546303@zte.com.cn Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-30Merge tag 'asahi-soc-rtkit-sart-6.2' of https://github.com/AsahiLinux/linux ↵Arnd Bergmann2-4/+10
into soc/drivers Apple SoC RTKit/SART updates for 6.2. Just two minor correctness nits reported by the kernel test robot. * tag 'asahi-soc-rtkit-sart-6.2' of https://github.com/AsahiLinux/linux: soc: apple: rtkit: Stop casting function pointer signatures soc: apple: sart: Stop casting function pointer signatures Link: https://lore.kernel.org/r/57f84134-8645-35f6-2427-ee683800c413@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-18 02:50:32 +0300