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2022-12-20Merge tag 'soc-fixes-6.2-1' of ↵Linus Torvalds1-0/+3
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd Bergmann: "These are a couple of build fixes from randconfig testing, plus a set of Mediatek SoC specific fixes, all trivial" * tag 'soc-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: soc: tegra: fix CPU_BIG_ENDIAN dependencies ARM: disallow pre-ARMv5 builds with ld.lld ARM: pxa: fix building with clang MAINTAINERS: add related dts to IXP4xx ARM: dts: spear: drop 0x from unit address arm64: dts: mt8183: Fix Mali GPU clock arm64: dts: mediatek: mt8195-demo: fix the memory size of node secmon soc: mediatek: pm-domains: Fix the power glitch issue
2022-12-19soc: tegra: fix CPU_BIG_ENDIAN dependenciesArnd Bergmann1-0/+3
My previous patch to prevent BPMP from being enabled on big endian kernels caused a build regression: WARNING: unmet direct dependencies detected for TEGRA_BPMP Depends on [n]: ARCH_TEGRA [=y] && TEGRA_HSP_MBOX [=y] && TEGRA_IVC [=y] && !CPU_BIG_ENDIAN [=y] Selected by [y]: - ARCH_TEGRA_186_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] - ARCH_TEGRA_194_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] - ARCH_TEGRA_234_SOC [=y] && ARCH_TEGRA [=y] && ARM64 [=y] Add even more such dependencies for the SoC types that use the BPMP driver. Fixes: 4ddb1bf1a837 ("tegra: mark BPMP driver as little-endian only") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221215165336.1781080-1-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-18soc/tegra: cbb: Remove redundant dev_err callShang XiaoJing1-3/+1
devm_ioremap_resource() prints error message in itself. Remove the dev_err call to avoid redundant error message. Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_errLiu Shixin1-12/+1
Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No functional change. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Check firewall before enabling error reportingSumit Gupta1-2/+81
To enable error reporting for a fabric to CCPLEX, we need to write its register for enabling error interrupt to CCPLEX during boot and later clear the error status register after error occurs. If a fabric's registers are protected and not accessible from CCPLEX, then accessing the registers will cause CBB firewall error. Add support to check whether write access from CCPLEX to the registers of a fabric is not blocked by it's firewall before enabling error reporting to CCPLEX for that fabric. Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Add checks for potential out of bound errorsSumit Gupta1-2/+40
Added checks to avoid potential out of bounds errors which can happen if the 'slave map' and 'CBB errors' arrays are not correct or latest where some entries are missing. Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Update slave maps for Tegra234Sumit Gupta1-21/+13
Updating the slave map for fabrics and using the same maps for DCE, RCE and SCE as they all are a replica in Tegra234. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194Sumit Gupta2-14/+13
In Tegra194 SoC, master_id bit range is different between cluster NOC and CBB NOC. Currently same bit range is used which results in wrong master_id value. Due to this, illegal accesses from the CCPLEX master do not result in a crash as expected. Fix this by using the correct range for the CBB NOC. Finally, it is only necessary to extract the master_id when the erd_mask_inband_err flag is set because when this is not set, a crash is always triggered. Fixes: b71344221466 ("soc/tegra: cbb: Add CBB 1.0 driver for Tegra194") Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: fuse: Use platform info with SoC revisionKartik2-2/+21
Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms. Instead, populate the revision SoC attribute with a combination of the platform name and the chip revision for silicon platforms, and simply with the platform name on pre-silicon platforms. Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-10soc/tegra: pmc: Process wake events during resumePetlozu Pravareshwar1-0/+41
During system resume, translate tier2 SC7 wake sources back into IRQs and do generic_handle_irq() to invoke the interrupt handlers for edge triggered wake events such as SW-wake. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-10soc/tegra: pmc: Fix dual edge triggered wakesPetlozu Pravareshwar1-5/+176
When a wake event is defined to be triggered on both positive and negative edge of the input wake signal, it is crucial to know the current state of the signal when going into suspend. The intended way to obtain the current state of the wake signals is to read the WAKE_AOWAKE_SW_STATUS register, which should contains the raw state of the wake signals. However, this register is edge triggered, an edge will not be generated for signals that are already asserted prior to the assertion of WAKE_LATCH_SW. To workaround this, change the polarity of the wake level from '0' to '1' while latching the signals, as this will generate an edge for signals that are set to '1'. Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-10soc/tegra: pmc: Add I/O pad table for Tegra234Petlozu Pravareshwar1-253/+403
Add I/O pad table for Tegra234 to allow configuring DPD mode and switching the pins to 1.8V or 3.3V as needed. On Tegra234, DPD registers are reorganized such that there is a DPD_REQ register and a DPD_STATUS register per pad group. Update the PMC driver accordingly. While at it, use the generated tables from tegra-pinmux-scripts to make the formatting of these tables more consistent. Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> [treding@nvidia.com: generate tables from tegra-pinmux-scripts] Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-10-24soc/tegra: fuse: Add nvmem keepout listKartik3-0/+42
On Tegra186 and later, various FUSE offsets are restricted and cannot be accessed from CCPLEX. Currently nvmem binary interface allows reading such offsets from userspace, which results in RAS errors. Add nvmem keepout lists to avoid any reads to restricted offsets. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-10-24soc/tegra: fuse: Use SoC specific nvmem cellsKartik3-111/+241
Tegra FUSE block size, availability and offsets can vary from one SoC generation to another. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-10-24soc/tegra: pmc: Select IRQ_DOMAIN_HIERARCHYPetlozu Pravareshwar1-0/+1
Tegra PMC driver depends on IRQ domain hierarchy support, hence select the IRQ_DOMAIN_HIERARCHY config for SOC_TEGRA_PMC. Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-23Merge tag 'tegra-for-6.1-cbb' of ↵Arnd Bergmann7-2/+3713
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: cbb: Changes for v6.1-rc1 This introduces the CBB driver that is used to provide (a lot of) information about SErrors when things go wrong, instead of the kernel just crashing or hanging. * tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: cbb: Add support for Tegra241 (Grace) soc/tegra: cbb: Add driver for Tegra234 CBB 2.0 soc/tegra: cbb: Add CBB 1.0 driver for Tegra194 soc/tegra: Set ERD bit to mask inband errors Link: https://lore.kernel.org/r/20220916101957.1635854-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15soc/tegra: pmc: Check device node status propertyPetlozu Pravareshwar1-1/+1
In early_initcall, check if PMC device is available for use and avoid accessing PMC resources if the device node status property is set to disabled. Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com> Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: pmc: Use devm_clk_get_optional()Christophe JAILLET1-11/+4
Use devm_clk_get_optional() instead of hand writing it. While at it, use dev_err_probe() to further simplify the code. This is also less verbose if clk_get() returns -EPROBE_DEFER. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: fuse: Drop Kconfig dependency on TEGRA20_APB_DMADmitry Osipenko1-1/+0
The DMA subsystem could be entirely disabled in Kconfig and then the TEGRA20_APB_DMA option isn't available too. Hence kernel configuration fails if DMADEVICES Kconfig option is disabled due to the unsatisfiable dependency. The FUSE driver isn't a critical driver and currently it only provides NVMEM interface to userspace which isn't known to be widely used, and thus, it's fine if FUSE driver fails to load. Let's remove the erroneous Kconfig dependency and let the FUSE driver to fail the probing if DMA is unavailable. Fixes: 19d41e5e9c68 ("soc/tegra: fuse: Add APB DMA dependency for Tegra20") Reported-by: Necip Fazil Yildiran <fazilyildiran@gmail.com> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209301 Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
2022-09-15soc/tegra: cbb: Add support for Tegra241 (Grace)Sumit Gupta1-2/+269
Adding support for Tegra241 (Grace) which uses fabrics based on the CBB 2.0 architecture. Since Tegra241 requires ACPI, implement ACPI-based probe support. Fabrics reporting errors in Tegra241 are "CBB" and "BPMP". The CBB fabric connects various other CBB 2.0 based fabrics and also services the Initiators and Targets which are connected to itself. The BPMP fabric is present in the BPMP cluster. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: cbb: Add driver for Tegra234 CBB 2.0Sumit Gupta3-1/+848
Adding driver to handle errors from CBB version 2.0 which is used in Tegra234 SoC. The driver prints debug information about failed transaction on receiving interrupt from the error notifier. The error notifier collates the interrupts from various error monitor blocks and presents a single interrupt to the SoC interrupt controller. For timeout errors, the driver also does the lookup to find timed out clients and prints their client ID. Drivers for hardware that needs to be reset on timeout will have to call BPMP from the client IP's driver. BPMP firmware will also clear the timeout bit after resetting the IP so that next transactions are send to them after reset. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: cbb: Add CBB 1.0 driver for Tegra194Sumit Gupta5-0/+2572
Adding driver to handle errors from Control Backbone (CBB) which are generated due to illegal accesses. CBB 1.0 is used in Tegra194 SoCs. When an error is reported from a NOC within CBB, the driver prints debug information about failed transaction like Error Code, Error Description, Master, Address, AXI ID, Cache, Protection, Security Group etc. It then causes system crash using BUG_ON() or call WARN() based on whether the error type is fatal or not. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: pmc: Add USB port wake events for Tegra194Thierry Reding1-0/+7
Tegra194 supports waking up from suspend when activity is detected on any of the USB ports. Add these wake events so that the system can be woken on such activity. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: pmc: Add support for simple wake eventsThierry Reding1-0/+19
Simple wake events are neither mapped to GIC interrupts nor have an associated GPIO line. They are close to GPIO-backed wake events in that the IRQ hierarchy processing needs to stop at the PMC level, but since there is no dedicated GPIO line for them, let's turn them into a separate type. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: pmc: Remove leading spaceThierry Reding1-1/+1
Remove a leading space from a line that is otherwise indented by tabs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: fuse: Add missing of_node_put()Liang He1-2/+5
In tegra_init_apbmisc(), of_find_matching_node() will return a node pointer with refcount incremented. We should use of_node_put() in each failure path or when it is not used anymore. Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: fuse: Add missing of_node_put() in tegra_init_fuse()Liang He1-0/+1
In this function, of_find_matching_node() will return a node pointer with refcount incremented. We should use of_node_put() when the "np" pointer is not used anymore. Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15soc/tegra: Set ERD bit to mask inband errorsSumit Gupta1-2/+27
Add a function to set the ERD (Error Response Disable) bit in the MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error handler driver. ERD bit allows masking of SError due to inband errors which are caused by illegal register accesses through CBB. When the bit is set, interrupt is used for reporting errors and magic code '0xdead2003' is returned. This change is only required for Tegra194 SoC as the config is moved to CBB register space for future SoC's. Also, remove unmapping the apbmisc_base as it's required to get the base address for accessing the misc register. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08soc/tegra: Migrate to dev_pm_opp_set_config()Viresh Kumar1-21/+31
The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08soc/tegra: Add comment over devm_pm_opp_set_clkname()Viresh Kumar1-0/+7
Explain why special handling was required here, it isn't obvious at all. Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-07-08OPP: Make dev_pm_opp_set_regulators() accept NULL terminated listViresh Kumar1-2/+2
Make dev_pm_opp_set_regulators() accept a NULL terminated list of names instead of making the callers keep the two parameters in sync, which creates an opportunity for bugs to get in. Suggested-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Steven Price <steven.price@arm.com> # panfrost Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2022-05-30Merge tag 'pm-5.19-rc1-2' of ↵Linus Torvalds1-25/+62
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull more power management updates from Rafael Wysocki: "These update the ARM cpufreq drivers and fix up the CPPC cpufreq driver after recent changes, update the OPP code and PM documentation and add power sequences support to the system reboot and power off code. Specifics: - Add Tegra234 cpufreq support (Sumit Gupta) - Clean up and enhance the Mediatek cpufreq driver (Wan Jiabing, Rex-BC Chen, and Jia-Wei Chang) - Fix up the CPPC cpufreq driver after recent changes (Zheng Bin, Pierre Gondois) - Minor update to dt-binding for Qcom's opp-v2-kryo-cpu (Yassine Oudjana) - Use list iterator only inside the list_for_each_entry loop (Xiaomeng Tong, and Jakob Koschel) - New APIs related to finding OPP based on interconnect bandwidth (Krzysztof Kozlowski) - Fix the missing of_node_put() in _bandwidth_supported() (Dan Carpenter) - Cleanups (Krzysztof Kozlowski, and Viresh Kumar) - Add Out of Band mode description to the intel-speed-select utility documentation (Srinivas Pandruvada) - Add power sequences support to the system reboot and power off code and make related platform-specific changes for multiple platforms (Dmitry Osipenko, Geert Uytterhoeven)" * tag 'pm-5.19-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (60 commits) cpufreq: CPPC: Fix unused-function warning cpufreq: CPPC: Fix build error without CONFIG_ACPI_CPPC_CPUFREQ_FIE Documentation: admin-guide: PM: Add Out of Band mode kernel/reboot: Change registration order of legacy power-off handler m68k: virt: Switch to new sys-off handler API kernel/reboot: Add devm_register_restart_handler() kernel/reboot: Add devm_register_power_off_handler() soc/tegra: pmc: Use sys-off handler API to power off Nexus 7 properly reboot: Remove pm_power_off_prepare() regulator: pfuze100: Use devm_register_sys_off_handler() ACPI: power: Switch to sys-off handler API memory: emif: Use kernel_can_power_off() mips: Use do_kernel_power_off() ia64: Use do_kernel_power_off() x86: Use do_kernel_power_off() sh: Use do_kernel_power_off() m68k: Switch to new sys-off handler API powerpc: Use do_kernel_power_off() xen/x86: Use do_kernel_power_off() parisc: Use do_kernel_power_off() ...
2022-05-19soc/tegra: pmc: Use sys-off handler API to power off Nexus 7 properlyDmitry Osipenko1-25/+62
Nexus 7 Android tablet can be turned off using a special bootloader command which is conveyed to bootloader by putting magic value into the special scratch register and then rebooting normally. This power-off method should be invoked if USB cable is connected. Bootloader then will display battery status and power off the device. This behaviour is borrowed from downstream kernel and matches user expectations, otherwise it looks like device got hung during power-off and it may wake up on USB disconnect. Switch PMC driver to sys-off handler API, which provides drivers with chained power-off callbacks functionality that is required for powering-off devices properly. It also brings resource-managed API for the restart handler registration that makes PMC driver code cleaner. Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-05-06soc/tegra: pmc: Document core domain fieldsThierry Reding1-0/+2
These fields are used to track the state of the core domain. Add basic descriptions so that kerneldoc can be properly generated for them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-05-04soc/tegra: pmc: Select REGMAPThierry Reding1-0/+1
Commit 9d5e7c3e36eb ("soc/tegra: pmc: Provide USB sleepwalk register map") introduced a dependency on the regmap infrastructure, so select the corresponding Kconfig entry. This avoids failures in random builds that may otherwise end up having SOC_TEGRA_PMC enabled but not REGMAP. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-06soc/tegra: pmc: Update Tegra234 reset sourcesSandipan Patra1-8/+25
Update the tegra234_reset_sources array to contain all reset sources for Tegra234 and NULL out the entries that do not actually exist. Signed-off-by: Sandipan Patra <spatra@nvidia.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-06soc/tegra: fuse: Add nvmem cell lookup entries for Tegra194Sagar Kamble2-5/+20
Add nvmem cell lookup entries for below FUSE cells: - gcplex-config-fuse - pdi0 - pdi1 Also include the device name prefix "gpu-" in the names of the GPU FUSE cells in nvmem_cell_info. Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25soc/tegra: pmc: Add Tegra234 wake eventskartik1-3/+9
Enable the Tegra RTC alarm and power key wake-ups for Tegra234 Signed-off-by: kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24soc/tegra: fuse: Explicitly cast to/from __iomemThierry Reding1-2/+2
sparse is picky about casts between different address spaces. A cast to plain void * needs to be accompanied by a __force modifier and casting back to void __iomem * needs to be explicit to avoid warnings. Reported-by: kernel test robot <lkp@intel.com> Fixes: 88724b78a84c ("soc/tegra: fuse: Use resource-managed helpers") Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24soc/tegra: fuse: Update nvmem cell listkartik1-1/+19
Update tegra_fuse_cells with below entries: - gcplex-config-fuse: Configuration bits for GPU, used to enable/disable write protected region used for storing GPU firmware. - pdi0: Unique per chip public identifier. - pdi1: Unique per chip public identifier. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30Dmitry Osipenko1-2/+2
All device drivers got runtime PM and OPP support. Flip the core domain support status for Tegra20 and Tegra30 SoCs. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-01-10Merge tag 'drivers-5.17' of ↵Linus Torvalds7-25/+351
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "There are cleanups and minor bugfixes across several SoC specific drivers, for Qualcomm, Samsung, NXP i.MX, AT91, Tegra, Keystone, Renesas, ZynqMP Noteworthy new features are: - The op-tee firmware driver gains support for asynchronous notifications from secure-world firmware. - Qualcomm platforms gain support for new SoC types in various drivers: power domain, cache controller, RPM sleep, soc-info - Samsung SoC drivers gain support for new SoCs in ChipID and PMU, as well as a new USIv2 driver that handles various types of serial communiction (uart, i2c, spi) - Renesas adds support for R-Car S4-8 (R8A779F0) in multiple drivers, as well as memory controller support for RZ/G2L (R9A07G044). - Apple M1 gains support for the PMGR power management driver" * tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits) soc: qcom: rpmh-rsc: Fix typo in a comment soc: qcom: socinfo: Add SM6350 and SM7225 dt-bindings: arm: msm: Don't mark LLCC interrupt as required dt-bindings: firmware: scm: Add SM6350 compatible dt-bindings: arm: msm: Add LLCC for SM6350 soc: qcom: rpmhpd: Sort power-domain definitions and lists soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280 soc: qcom: rpmhpd: Rename rpmhpd struct names soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao soc: qcom: socinfo: add SM8450 ID soc: qcom: rpmhpd: Add SM8450 power domains dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding soc: qcom: smem: Update max processor count dt-bindings: arm: qcom: Document SM8450 SoC and boards dt-bindings: firmware: scm: Add SM8450 compatible dt-bindings: arm: cpus: Add kryo780 compatible soc: qcom: rpmpd: Add support for sm6125 dt-bindings: qcom-rpmpd: Add sm6125 power domains soc: qcom: aoss: constify static struct thermal_cooling_device_ops PM: AVS: qcom-cpr: Use div64_ul instead of do_div ...
2021-12-16soc/tegra: pmc: Rename core power domainDmitry Osipenko1-1/+1
CORE power domain uses name of device-tree node, which is inconsistent with the names of PMC domains. Set the name to "core" to make it consistent. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: pmc: Rename 3d power domainsDmitry Osipenko1-4/+4
Device-tree schema doesn't allow domain name to start with a number. We don't use 3d domain yet in device-trees, so rename it to the name used by Tegra TRMs: TD, TD2. Reported-by: David Heidelberg <david@ixit.cz> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: regulators: Prepare for suspendDmitry Osipenko2-0/+221
Depending on hardware version, Tegra SoC may require a higher voltages during resume from system suspend, otherwise hardware will crash. Set SoC voltages to a nominal levels during suspend. Link: https://lore.kernel.org/all/a8280b5b-7347-8995-c97b-10b798cdf057@gmail.com/ Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: fuse: Use resource-managed helpersDmitry Osipenko2-17/+48
Use resource-managed helpers to make code cleaner and more correct, properly releasing all resources in case of driver probe error. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: fuse: Reset hardwareDmitry Osipenko2-0/+26
The FUSE controller is enabled at a boot time. Reset it in order to put hardware and clock into clean and disabled state. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: pmc: Add reboot notifierJon Hunter1-3/+28
The Tegra PMC driver implements a restart handler that supports Tegra specific reboot commands such as placing the device into 'recovery' mode in order to reprogram the platform. This is accomplished by setting the appropriate bit in the PMC scratch0 register prior to rebooting the platform. For Tegra platforms that support PSCI or EFI, the default Tegra restart handler is not called and the PSCI or EFI restart handler is called instead. Hence, for Tegra platforms that support PSCI or EFI, the Tegra specific reboot commands do not currently work. Fix this by moving the code that programs the PMC scratch0 register into a separate reboot notifier that will always be called on reboot. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: Don't print error message when OPPs not availableDmitry Osipenko1-3/+1
Previously we assumed that devm_tegra_core_dev_init_opp_table() will be used only by drivers that will always have device with OPP table, but this is not true anymore. For example now Tegra30 will have OPP table for PWM, but Tegra20 not and both use the same driver. Hence let's not print the error message about missing OPP table in the common helper, we can print it elsewhere. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: Enable runtime PM during OPP state-syncingDmitry Osipenko1-0/+25
GENPD core now can set up domain's performance state properly while device is RPM-suspended. Runtime PM of a device must be enabled during setup because GENPD checks whether device is suspended and check doesn't work while RPM is disabled. Instead of replicating the boilerplate RPM-enable code around OPP helper for each driver, let's make OPP helper to take care of enabling it. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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