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path: root/drivers/soc/bcm/brcmstb/biuctrl.c
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2023-04-03soc: bcm: brcmstb: biuctrl: fix of_iomap leakZhaoyang Li1-0/+4
Smatch reports: drivers/soc/bcm/brcmstb/biuctrl.c:291 setup_hifcpubiuctrl_regs() warn: 'cpubiuctrl_base' from of_iomap() not released on lines: 291. This is because in setup_hifcpubiuctrl_regs(), cpubiuctrl_base is not released when handle error, which may cause a leak. To fix this, iounmap is added when handle error. Fixes: 22f7a9116eba ("soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs") Signed-off-by: Zhaoyang Li <lizhaoyang04@hust.edu.cn> Reviewed-by: Dan Carpenter <error27@gmail.com> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Link: https://lore.kernel.org/r/20230327115422.1536615-1-lizhaoyang04@hust.edu.cn Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-09-16soc: bcm: brcmstb: biuctrl: Avoid double of_node_put()Florian Fainelli1-1/+0
Commit 9a073d4fbb18 ("soc: bcm: brcmstb: biuctrl: Add missing of_node_put()") added what was thought to be a missing of_node_put() but now causes a double of_node_put() to be called, once from setup_hifcpubiuctrl_regs() and another time from brcmstb_biuctrl_init(). Ensure that setup_hifcpubiuctrl_regs() is not calling of_node_put() since it is not obvious it does that on one of its parameters. Fixes: 9a073d4fbb18 ("soc: bcm: brcmstb: biuctrl: Add missing of_node_put()") Reported-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Change-Id: I1c405c36c2f06c8b8c0f684143b7a52db7e809f0
2022-06-18soc: bcm: brcmstb: biuctrl: Add missing of_node_put()Liang He1-3/+6
In brcmstb_biuctrl_init(), of_find_compatible_node() will return a node pointer with refcount incremented. We should use of_node_put() in each fail path or when it is not used anymore. Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-17soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72116Florian Fainelli1-0/+1
72116 uses a quad core Brahma-B53 CPU complex which uses the same tuning as done for previous chips, add that chip to the list. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-09-17soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72113Florian Fainelli1-0/+1
72113 uses a dual core Cortex-A72 CPU complex which requires tuning of its bus interface unit the same way that the existing Cortex-A72 based systems are tuned. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-06soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 ↵Florian Fainelli1-2/+6
consecutive lines Change the RACPREFDATA(x) setting to prefetch the next 256-byte line after 4 consecutive lines have been used, instead of after 2 consecutive lines. This does improve the synthetic memcpy benchmark by an additional +0.5% on top of the previous change for Cortex-A72 CPUs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-04soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2Florian Fainelli1-4/+16
Change the RAC prefetch distance from +/- 1 to +/- 2 for Cortex-A72 CPUs since this provides an average of a 3.8% performance increase for synthetic memcpy benchmarks. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-04soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165Florian Fainelli1-0/+1
72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it according to the existing values we have. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-04soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164Florian Fainelli1-0/+1
72164 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it according to the existing values we have. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-08-17soc: bcm: brcmstb: biuctrl: Enable Read-ahead cacheFlorian Fainelli1-10/+77
Brahma-B53 and Cortex-A72 CPUs integrated on Broadcom STB SoCs feature a read-ahead cache that performs cache line size adaptation between the bus interface unit and the memory controller. On 32-bit ARM kernels we have to resort to a full featured read-ahead cache driver under arch/arm/mm/cache-b15-rac.c (CONFIG_CACHE_B15_RAC) because there are still cache maintenance operations by set/ways/index that cannot be transparently handled by the ARM Coherency Extension that the read-ahead cache interfaces to. The 64-bit ARM kernel however has long deprecated all of those, so this is simply a one time configuration. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-06soc: bcm: brcmstb: biuctrl: Update programming for 7211Florian Fainelli1-6/+7
Add a matching entry for 7211 which can be programmed with the same BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the function to include a72 in the name to reflect this applies to both types of 64-bit capable CPUs that we support (Brahma-B53 and Cortex-A72). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-06soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211Florian Fainelli1-0/+8
The BIUCTRL layout is a little different on 7211 which is equipped with a Cortex-A72, account for those register offset differences. We will match 7211 specifically in a subsequent commit. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-06soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216Florian Fainelli1-0/+2
7255 and 7216 are some of the latest chips that were produced and support the full register range configuration for the BIU, add the two entries to get the expected programming. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-06soc: bcm: brcmstb: biuctrl: Tune 7260 BIU interfaceFlorian Fainelli1-2/+5
7260A0 and B0 are both supported, and 7260A0 has a small difference in that it does not support the write-back control register, which is why we have a different array of registers. Update the comment above b53_cpubiuctrl_no_wb_regs to denote that difference. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-16Merge tag 'arm-soc/for-5.2/drivers-fixes' of ↵Olof Johansson1-2/+4
https://github.com/Broadcom/stblinux into fixes This pull request contains Broadcom ARM/ARM64/MIPS SoCs device drivers fixes for 5.2-rc1, please pull the following: - Florian fixes the biuctrl driver not to create an error condition/path upon unsupported CPU and also fixes the biuctrl driver writes to used a data barrier which is necessary given the HW block design * tag 'arm-soc/for-5.2/drivers-fixes' of https://github.com/Broadcom/stblinux: soc: bcm: brcmstb: biuctrl: Register writes require a barrier soc: brcmstb: Fix error path for unsupported CPUs Signed-off-by: Olof Johansson <olof@lixom.net>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-20soc: bcm: brcmstb: biuctrl: Register writes require a barrierFlorian Fainelli1-1/+1
The BIUCTRL register writes require that a data barrier be inserted after comitting the write to the register for the block to latch in the recently written values. Reads have no such requirement and are not changed. Fixes: 34642650e5bc ("soc: Move brcmstb to bcm/brcmstb") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-05-20soc: brcmstb: Fix error path for unsupported CPUsFlorian Fainelli1-1/+3
In case setup_hifcpubiuctrl_regs() returns an error, because of e.g: an unsupported CPU type, just catch that error and return instead of blindly continuing with the initialization. This fixes a NULL pointer de-reference with the code continuing without having a proper array of registers to use. Fixes: 22f7a9116eba ("soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15soc: brcmstb: biuctrl: exit without warning on non brcmstb platformsSudeep Holla1-9/+11
Currently if this driver is included, we get the following warning on any platforms irrespective of whether it's brcmstb platform or not. " brcmstb: biuctrl: missing BIU control node brcmstb: biuctrl: MCP: Unable to disable write pairing! " This patch allows to exit early without any warning messages on non brcmstb platforms as it's meaningless for them. Cc: Brian Norris <computersforpeace@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: bcm-kernel-feedback-list@broadcom.com Fixes: f780429adfbc ("soc: brcmstb: biuctrl: Move to early_initcall") Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> [florian: Add fixes tag, make initcall non fatal] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-12-21soc: brcmstb: biuctrl: Move to early_initcallFlorian Fainelli1-2/+4
Being called during early_initcall() is early enough that it occurs before SMP initialization, which is all we care about for the Bus Interface Unit configuration. This solves lack of BIU initialization on ARM64 platforms where we do not have an anchor where to put the BIU initialization (since there are no machine descriptors). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-12-21soc: brcmstb: biuctrl: Fine tune B53 MCP interface settingsFlorian Fainelli1-0/+76
In order to achieve expected MCP bus throughput on 3 particular chips: 7268, 7271 and 7278, do the appropriate programming of the MCP interface: increase number of MCP write credits, turn on write-back throttling when present. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-12-21soc: brcmstb: biuctrl: Wire-up new registersFlorian Fainelli1-1/+7
Add definitions for B53 systems register: CPU_MCP_FLOW_REG and CPU_WRITEBACK_CTRL_REG. These register will be saved and restored accordingly. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-12-21soc: brcmstb: biuctrl: Prepare for saving/restoring other registersFlorian Fainelli1-17/+58
In preparation for saving/restoring additional registers required on some newer platforms (7268, 7271, 7278), migrate the code to use enums and helper functions to access registers. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-12-21soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUsFlorian Fainelli1-3/+21
On Broadcom Brahma-B53 CPUs, the CPU_CREDIT_REG offset got moved to 0x0b0 instead of 0x184, correct this such that we correcty enable/disable write-pairing for these chips. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-12-21soc: brcmstb: Make CPU credit offset more parameterizedFlorian Fainelli1-5/+6
In preparation for fixing and changing values in the CPU_CREDIT_REG register for B53-based systems, make the offset parameterized. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-06-07soc: brcmstb: fix warning from missing includeBen Dooks1-0/+1
The brcmstb_biuctrl_init() is defined in the soc specific header file, but wasn't included in the driver file. Fix the following warning by including <linux/soc/brcmstb/brcmstb.h> in the driver: drivers/soc/brcmstb/biuctrl.c:101:13: warning: symbol 'brcmstb_biuctrl_init' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31soc: Move brcmstb to bcm/brcmstbFlorian Fainelli1-0/+116
Unify the different Broadcom SoCs directory and have everybody live under drivers/soc/bcm/*. Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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