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2025-12-09Merge tag 'pinctrl-v6.19-1' of ↵Linus Torvalds77-1916/+10154
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "The technical details below. For me the CIX Semi and Axis Communications ARTPEC-9 SoCs were the most interesting new drivers in this merge window. Core changes: - Handle per-direction skew control in the generic pin config - Drop the pointless subsystem boilerplate banner message during boot. Less noise in the console. It's available as debug message if someone really want it New drivers: - Samsung Exynos 8890 SoC support - Samsung Exynos derived Axis Communications ARTPEC-9 SoC support. These guys literally live next door to me, ARTPEC spells out "Axis Real-Time Picture Encoding Chip" and is tailored for camera image streams and is something they have evolved for a quarter of a century - Mediatek MT6878 SoC support - Qualcomm Glymur PMIC support (mostly just compatible strings) - Qualcomm Kaanapali SoC TLMM support - Microchip pic64gx "gpio2" SoC support - Microchip Polarfire "iomux0" SoC support - CIX Semiconductors SKY1 SoC support - Rockchip RK3506 SoC support - Airhoa AN7583 chip support Improvements: - Improvements for ST Microelectronics STM32 handling of skew settings so input and output can have different skew settings - A whole bunch of device tree binding cleanups: Marvell Armada and Berlin, Actions Semiconductor S700 and S900, Broadcom Northstar 2 (NS2), Bitmain BM1880 and Spreadtrum SC9860 are moved over to schema" * tag 'pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits) pinctrl: add CONFIG_OF dependencies for microchip drivers pinctrl: starfive: use dynamic GPIO base allocation pinctrl: single: Fix incorrect type for error return variable MAINTAINERS: Change Linus Walleij mail address pinctrl: cix: Fix obscure dependency dt-bindings: pinctrl: cix,sky1-pinctrl: Drop duplicate newline dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data pinctrl: airoha: fix pinctrl function mismatch issue pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges() pinctrl: intel: Export intel_gpio_add_pin_ranges() pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling pinctrl: airoha: convert comma to semicolon pinctrl: elkhartlake: Switch to INTEL_GPP() macro pinctrl: cherryview: Switch to INTEL_GPP() macro pinctrl: emmitsburg: Switch to INTEL_GPP() macro pinctrl: denverton: Switch to INTEL_GPP() macro pinctrl: cedarfork: Switch to INTEL_GPP() macro pinctrl: airoha: add support for Airoha AN7583 PINs dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller ...
2025-12-06Merge tag 'bitmap-for-6.19' of github.com:/norov/linuxLinus Torvalds1-4/+0
Pull bitmap updates from Yury Norov: - Runtime field_{get,prep}() (Geert) - Rust ID pool updates (Alice) - min_t() simplification (David) - __sw_hweightN kernel-doc fixes (Andy) - cpumask.h headers cleanup (Andy) * tag 'bitmap-for-6.19' of github.com:/norov/linux: (32 commits) rust_binder: use bitmap for allocation of handles rust: id_pool: do not immediately acquire new ids rust: id_pool: do not supply starting capacity rust: id_pool: rename IdPool::new() to with_capacity() rust: bitmap: add BitmapVec::new_inline() rust: bitmap: add MAX_LEN and MAX_INLINE_LEN constants cpumask: Don't use "proxy" headers soc: renesas: Use bitfield helpers clk: renesas: Use bitfield helpers ALSA: usb-audio: Convert to common field_{get,prep}() helpers soc: renesas: rz-sysc: Convert to common field_get() helper pinctrl: ma35: Convert to common field_{get,prep}() helpers iio: mlx90614: Convert to common field_{get,prep}() helpers iio: dac: Convert to common field_prep() helper gpio: aspeed: Convert to common field_{get,prep}() helpers EDAC/ie31200: Convert to common field_get() helper crypto: qat - convert to common field_get() helper clk: at91: Convert to common field_{get,prep}() helpers bitfield: Add non-constant field_{prep,get}() helpers bitfield: Add less-checking __FIELD_{GET,PREP}() ...
2025-12-06Merge tag 'soc-drivers-6.19' of ↵Linus Torvalds1-4/+3
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "This is the first half of the driver changes: - A treewide interface change to the "syscore" operations for power management, as a preparation for future Tegra specific changes - Reset controller updates with added drivers for LAN969x, eic770 and RZ/G3S SoCs - Protection of system controller registers on Renesas and Google SoCs, to prevent trivially triggering a system crash from e.g. debugfs access - soc_device identification updates on Nvidia, Exynos and Mediatek - debugfs support in the ST STM32 firewall driver - Minor updates for SoC drivers on AMD/Xilinx, Renesas, Allwinner, TI - Cleanups for memory controller support on Nvidia and Renesas" * tag 'soc-drivers-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (114 commits) memory: tegra186-emc: Fix missing put_bpmp Documentation: reset: Remove reset_controller_add_lookup() reset: fix BIT macro reference reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe reset: th1520: Support reset controllers in more subsystems reset: th1520: Prepare for supporting multiple controllers dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets reset: remove legacy reset lookup code clk: davinci: psc: drop unused reset lookup reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support reset: eswin: Add eic7700 reset driver dt-bindings: reset: eswin: Documentation for eic7700 SoC reset: sparx5: add LAN969x support dt-bindings: reset: microchip: Add LAN969x support soc: rockchip: grf: Add select correct PWM implementation on RK3368 soc/tegra: pmc: Add USB wake events for Tegra234 amba: tegra-ahb: Fix device leak on SMMU enable ...
2025-12-04pinctrl: add CONFIG_OF dependencies for microchip driversArnd Bergmann1-0/+2
The two newly added drivers fail to link on builds without CONFIG_OF: x86_64-linux-ld: drivers/pinctrl/pinctrl-pic64gx-gpio2.o: in function `pinconf_generic_dt_node_to_map_all': pinctrl-pic64gx-gpio2.c:(.text+0xc9): undefined reference to `pinconf_generic_dt_node_to_map' x86_64-linux-ld: drivers/pinctrl/pinctrl-mpfs-iomux0.o: in function `pinconf_generic_dt_node_to_map_all': pinctrl-mpfs-iomux0.c:(.text+0xc9): undefined reference to `pinconf_generic_dt_node_to_map' Add a Kconfig dependencies. Fixes: 38cf9d641314 ("pinctrl: add pic64gx "gpio2" pinmux driver") Fixes: 46397274da22 ("pinctrl: add polarfire soc iomux0 pinmux driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2025-12-04pinctrl: starfive: use dynamic GPIO base allocationAli Tariq4-6/+1
The JH7110 pinctrl driver currently sets a static GPIO base number from platform data: sfp->gc.base = info->gc_base; Static base assignment is deprecated and results in the following warning: gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation. Set `sfp->gc.base = -1` to let the GPIO core dynamically allocate the base number. This removes the warning and aligns the driver with current GPIO guidelines. Since the GPIO base is now allocated dynamically, remove `gc_base` field in `struct jh7110_pinctrl_soc_info` and the associated `JH7110_SYS_GC_BASE` and `JH7110_AON_GC_BASE` constants as they are no longer used anywhere in the driver. Tested on VisionFive 2 (JH7110 SoC). Signed-off-by: Ali Tariq <alitariq45892@gmail.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2025-12-04pinctrl: single: Fix incorrect type for error return variableHaotian Zhang1-3/+4
pcs_pinconf_get() and pcs_pinconf_set() declare ret as unsigned int, but assign it the return values of pcs_get_function() that may return negative error codes. This causes negative error codes to be converted to large positive values. Change ret from unsigned int to int in both functions. Fixes: 9dddb4df90d1 ("pinctrl: single: support generic pinconf") Signed-off-by: Haotian Zhang <vulab@iscas.ac.cn> Signed-off-by: Linus Walleij <linusw@kernel.org>
2025-11-25Merge tag 'intel-pinctrl-v6.19-1' of ↵Linus Walleij19-451/+319
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.19-1 * Add and use common macro INTEL_GPP() to avoid duplication * Export intel_gpio_add_pin_ranges() and reuse it instead of custom copies * Unify error messages with help of dev_err_probe() Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-25pinctrl: cix: Fix obscure dependencyLinus Walleij1-0/+1
When compile-testing for UM-Linux the build fails because we don't have IOMEM. Add an explicit dependency. Fixes: 920500c5fe66 ("pinctrl: cix: Add pin-controller support for sky1") Reviewed-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-24pinctrl: ma35: Convert to common field_{get,prep}() helpersGeert Uytterhoeven1-6/+0
Drop the driver-specific field_get() and field_prep() macros, in favor of the globally available variants from <linux/bitfield.h>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-11-24pinctrl: ma35: #undef field_{get,prep}() before local definitionGeert Uytterhoeven1-0/+2
Prepare for the advent of globally available common field_get() and field_prep() macros by undefining the symbols before defining local variants. This prevents redefinition warnings from the C preprocessor when introducing the common macros later. Suggested-by: Yury Norov <yury.norov@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
2025-11-19pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_dataNathan Chancellor1-1/+1
Clang warns (or errors with CONFIG_WERROR=y / W=e): pinctrl/mediatek/pinctrl-airoha.c:2064:41: error: variable 'an7583_pinctrl_drive_e2_conf' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration] 2064 | static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ Due to a typo, an7583_pinctrl_drive_e2_conf is only used within ARRAY_SIZE() (hence no instance of -Wunused-variable), which is evaluated at compile time, so it will not be needed in the final object file. Fix the .confs assignment for AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data to clear up the warning. Closes: https://github.com/ClangBuiltLinux/linux/issues/2142 Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Acked-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-19pinctrl: airoha: fix pinctrl function mismatch issueChukun Pan1-1/+1
The blamed commit made the following changes: -#define PINCTRL_FUNC_DESC(id)... - .desc = PINCTRL_PINFUNCTION(#id, ... +#define PINCTRL_FUNC_DESC(id, table)... + .desc = PINCTRL_PINFUNCTION(#id, ... - PINCTRL_FUNC_DESC(pon)... + PINCTRL_FUNC_DESC("pon", pon)... It's clear that the id of funcs doesn't match the definition. Remove redundant #string from the definition to fix this issue: pinctrl-airoha ...: invalid function mdio in map table Fixes: 4043b0c45f85 ("pinctrl: airoha: generalize pins/group/function/confs handling") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Acked-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-19Merge tag 'renesas-pinctrl-for-v6.19-tag2' of ↵Linus Walleij3-91/+68
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.19 (take two) - Remove removed signals on R-Car V4H and V4M, - Refactor OEN register PWPR handling on RZ/G2L. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-19pinctrl: s32cc: initialize gpio_pin_config::list after kmalloc()Jared Kangas1-0/+1
s32_pmx_gpio_request_enable() does not initialize the newly-allocated gpio_pin_config::list before adding it to s32_pinctrl::gpio_configs. This could result in a linked list corruption. Initialize the new list_head with INIT_LIST_HEAD() to fix this. Fixes: fd84aaa8173d ("pinctrl: add NXP S32 SoC family support") Signed-off-by: Jared Kangas <jkangas@redhat.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-19pinctrl: s32cc: fix uninitialized memory in s32_pinctrl_descJared Kangas1-1/+1
s32_pinctrl_desc is allocated with devm_kmalloc(), but not all of its fields are initialized. Notably, num_custom_params is used in pinconf_generic_parse_dt_config(), resulting in intermittent allocation errors, such as the following splat when probing i2c-imx: WARNING: CPU: 0 PID: 176 at mm/page_alloc.c:4795 __alloc_pages_noprof+0x290/0x300 [...] Hardware name: NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3) (DT) [...] Call trace: __alloc_pages_noprof+0x290/0x300 (P) ___kmalloc_large_node+0x84/0x168 __kmalloc_large_node_noprof+0x34/0x120 __kmalloc_noprof+0x2ac/0x378 pinconf_generic_parse_dt_config+0x68/0x1a0 s32_dt_node_to_map+0x104/0x248 dt_to_map_one_config+0x154/0x1d8 pinctrl_dt_to_map+0x12c/0x280 create_pinctrl+0x6c/0x270 pinctrl_get+0xc0/0x170 devm_pinctrl_get+0x50/0xa0 pinctrl_bind_pins+0x60/0x2a0 really_probe+0x60/0x3a0 [...] __platform_driver_register+0x2c/0x40 i2c_adap_imx_init+0x28/0xff8 [i2c_imx] [...] This results in later parse failures that can cause issues in dependent drivers: s32g-siul2-pinctrl 4009c240.pinctrl: /soc@0/pinctrl@4009c240/i2c0-pins/i2c0-grp0: could not parse node property s32g-siul2-pinctrl 4009c240.pinctrl: /soc@0/pinctrl@4009c240/i2c0-pins/i2c0-grp0: could not parse node property [...] pca953x 0-0022: failed writing register: -6 i2c i2c-0: IMX I2C adapter registered s32g-siul2-pinctrl 4009c240.pinctrl: /soc@0/pinctrl@4009c240/i2c2-pins/i2c2-grp0: could not parse node property s32g-siul2-pinctrl 4009c240.pinctrl: /soc@0/pinctrl@4009c240/i2c2-pins/i2c2-grp0: could not parse node property i2c i2c-1: IMX I2C adapter registered s32g-siul2-pinctrl 4009c240.pinctrl: /soc@0/pinctrl@4009c240/i2c4-pins/i2c4-grp0: could not parse node property s32g-siul2-pinctrl 4009c240.pinctrl: /soc@0/pinctrl@4009c240/i2c4-pins/i2c4-grp0: could not parse node property i2c i2c-2: IMX I2C adapter registered Fix this by initializing s32_pinctrl_desc with devm_kzalloc() instead of devm_kmalloc() in s32_pinctrl_probe(), which sets the previously uninitialized fields to zero. Fixes: fd84aaa8173d ("pinctrl: add NXP S32 SoC family support") Signed-off-by: Jared Kangas <jkangas@redhat.com> Tested-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-18pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges()Andy Shevchenko1-19/+1
Driver is ready to use intel_gpio_add_pin_ranges() directly instead of custom approach. Convert it now. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-18pinctrl: intel: Export intel_gpio_add_pin_ranges()Andy Shevchenko2-1/+13
Export intel_gpio_add_pin_ranges() for reuse in other drivers. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-13pinctrl: renesas: rzg2l: Refactor OEN register PWPR handlingJohn Madieu1-20/+33
Extract the OEN register write with PWPR protection logic into a helper function to eliminate code duplication between rzg2l_write_oen() and rzg2l_pinctrl_resume_noirq(). Introduce rzg2l_oen_write_with_pwpr() helper that encapsulates the PWPR unlock, OEN register write, and PWPR lock sequence. This helper must be called with pctrl->lock already held by the caller. Reported-by: Pavel Machek <pavel@denx.de> Closes: https://lore.kernel.org/cip-dev/OS9PR01MB16368C765305362F5F4132759FFC4A@OS9PR01MB16368.jpnprd01.prod.outlook.com/T/#u Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251106080758.36645-1-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-11-12pinctrl: airoha: convert comma to semicolonChen Ni1-6/+6
Replace comma between expressions with semicolons. Using a ',' in place of a ';' can have unintended side effects. Although that is not the case here, it is seems best to use ';' unless ',' is intended. Found by inspection. No functional change intended. Compile tested only. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-12pinctrl: qcom: msm: Fix deadlock in pinmux configurationPraveen Talari1-1/+1
Replace disable_irq() with disable_irq_nosync() in msm_pinmux_set_mux() to prevent deadlock when wakeup IRQ is triggered on the same GPIO being reconfigured. The issue occurs when a wakeup IRQ is triggered on a GPIO and the IRQ handler attempts to reconfigure the same GPIO's pinmux. In this scenario, msm_pinmux_set_mux() calls disable_irq() which waits for the currently running IRQ handler to complete, creating a circular dependency that results in deadlock. Using disable_irq_nosync() avoids waiting for the IRQ handler to complete, preventing the deadlock condition while still properly disabling the interrupt during pinmux reconfiguration. Suggested-by: Prasad Sodagudi <prasad.sodagudi@oss.qualcomm.com> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-12pinctrl: elkhartlake: Switch to INTEL_GPP() macroAndy Shevchenko1-25/+18
Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-12pinctrl: cherryview: Switch to INTEL_GPP() macroAndy Shevchenko1-26/+20
Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-12pinctrl: emmitsburg: Switch to INTEL_GPP() macroAndy Shevchenko1-20/+13
Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-12pinctrl: denverton: Switch to INTEL_GPP() macroAndy Shevchenko1-14/+7
Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-12pinctrl: cedarfork: Switch to INTEL_GPP() macroAndy Shevchenko1-22/+15
Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-11pinctrl: airoha: add support for Airoha AN7583 PINsChristian Marangi1-7/+740
Add all the required entry to add suppot for Airoha AN7583 PINs. Where possible the same function group are used from Airoha EN7581 to reduce code duplication. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-11pinctrl: airoha: convert PWM GPIO to macroChristian Marangi1-397/+68
The PWM GPIO struct definition follow the same pattern for every GPIO pin hence it can be converted to a macro. Create 2 macro one for normal mux and one for ext mux and convert all the entry to these new macro to reduce code size. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-11pinctrl: airoha: convert PHY LED GPIO to macroChristian Marangi1-488/+100
PHY LED GPIO pinctrl struct definition is very similar across the different 4 PHY and 2 LED and it can be generelized to a macro. To reduce code size, convert them to a common macro. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-11pinctrl: airoha: generalize pins/group/function/confs handlingChristian Marangi1-249/+318
In preparation for support of Airoha AN7583, generalize pins/group/function/confs handling and move them in match_data. Inner function will base the values on the pinctrl priv struct instead of relying on hardcoded struct. This permits to use different PIN data while keeping the same logic. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-11pinctrl: stm32: handle semaphore acquisition when handling pinctrl/pinmuxGatien Chevallier1-8/+27
When a GPIO RIF configuration is in semaphore mode, and the semaphore hasn't been taken before configuring the GPIO, the write operations silently fail. To avoid a silent fail when applying a pinctrl, if the pins that are being configured are in semaphore mode, take the semaphore. Note that there is no proper release of the RIF semaphore yet for pinctrl. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-11pinctrl: rockchip: Add rk3506 pinctrl supportYe Zhang2-8/+438
Add support for the 5 rk3506 GPIO banks. Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-10Merge tag 'samsung-pinctrl-6.19' of ↵Linus Walleij3-0/+212
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.19 Add pin controller support for Samsung Exynos8890 and Axis ARTPEC-9 SoCs. The latter is a newer design of Artpec SoCs made/designed by Samsung, thus it shares most of the core blocks with Samsung Exynos, including the pinctrl. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-10pinctrl: renesas: r8a779h0: Remove STPWT_EXTFXRGeert Uytterhoeven1-2/+1
Rev.0.81 of the R-Car V4M Series Hardware User’s Manual removed the "STPWT_EXTFXR" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/f849fa3b9b516e9dd04b45462b69f52225259480.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: renesas: r8a779h0: Remove CC5_OSCOUTHuy Bui1-2/+1
Rev.0.71 of the R-Car V4M Series Hardware User’s Manual removed the "CC5_OSCOUT" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/895bb560467309706931d14aeea0e063ad0e86eb.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: renesas: r8a779g0: Remove STPWT_EXTFXRHuy Bui1-2/+1
Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "STPWT_EXTFXR" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/f6cfdbbc024d85e87583a1d57ea01582632f1216.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: renesas: r8a779g0: Remove CC5_OSCOUTHuy Bui1-2/+1
Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "CC5_OSCOUT" signal from the pin control register tables. As this is further unused in the pin control driver, it can be removed safely. Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/77f9efe5388f2801ace945b7793d4823618eeec8.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: renesas: r8a779g0: Remove AVB[01]_MIIThanh Quan1-64/+32
Rev.1.30 of the R-Car V4H Series Hardware User’s Manual removed the "AVB[01]_MII_*" signals from the pin control register tables. As these are further unused in the pin control driver, they can be removed safely. Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/58662f50136280532bcc8bbe94741d82425bd118.1762274384.git.geert+renesas@glider.be
2025-11-10pinctrl: cirrus: Fix fwnode leak in cs42l43_pin_probe()Haotian Zhang1-4/+19
The driver calls fwnode_get_named_child_node() which takes a reference on the child node, but never releases it, which causes a reference leak. Fix by using devm_add_action_or_reset() to automatically release the reference when the device is removed. Fixes: d5282a539297 ("pinctrl: cs42l43: Add support for the cs42l43") Suggested-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Haotian Zhang <vulab@iscas.ac.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-10Merge tag 'renesas-pinctrl-for-v6.19-tag1' of ↵Linus Walleij18-76/+83
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.19 - Fix interrupt configuration and port mode after resume on RZ/G2L family SoCs, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-11-05pinctrl: sunrisepoint: Switch to INTEL_GPP() macroAndy Shevchenko1-17/+9
Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: tigerlake: Switch to INTEL_GPP() macroAndy Shevchenko1-39/+31
Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: meteorpoint: Switch to INTEL_GPP() macroAndy Shevchenko1-27/+19
Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: meteorlake: Switch to INTEL_GPP() macroAndy Shevchenko1-31/+23
Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: lakefield: Switch to INTEL_GPP() macroAndy Shevchenko1-17/+9
Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: jasperlake: Switch to INTEL_GPP() macroAndy Shevchenko1-21/+13
Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: icelake: Switch to INTEL_GPP() macroAndy Shevchenko1-34/+26
Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: cannonlake: Switch to INTEL_GPP() macroAndy Shevchenko1-38/+30
Replace custom macro with the recently defined INTEL_GPP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: alderlake: Switch to INTEL_GPP() macroAndy Shevchenko1-38/+30
Replace custom macro with the recently defined INTEL_GPP(). Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: intel: Introduce INTEL_GPP() macroAndy Shevchenko1-0/+9
A new macro will be used for the further refactoring of the drivers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-05pinctrl: cix: sky1: Provide pin control dummy statesLinus Walleij2-0/+16
This exports and calls the pinctrl_provide_dummies() function from the CIX SKY1 driver. The reasons are explained in a comment in the commit, in essence the two pin controllers need to go through explicit state transitions default->sleep->default despite they only handle one single state each. Reviewed-by: Hans Zhang <hans.zhang@cixtech.com> Reviewed-by: Fugang Duan <fugang.duan@cixtech.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-04-28 12:46:46 +0300