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2012-10-10pinctrl/nomadik: use simple or linear IRQ domainLinus Walleij1-3/+13
This alters the Nomadik pinctrl driver to: - Call irqdomain_add_linear() for the DT case so we get all independent from IRQ numbers in this case. - Call irqdomain_add_simple() for the legacy case, which allocates the IRQ descriptors for the Nomadik pin controller dynamically. Cc: Lee Jones <lee.jones@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-10pinctrl/nomadik: support other alternate-C functionsJean-Nicolas Graux4-47/+765
Upgrade nomadik pinctrl driver to enable selection of other alternate-C[1-4] functions on some specific ux500 SoC pins. Handling of those functions is done thanks to PRCM GPIOCR registers. This was previously managed in PRCMU driver and it was not really convenient. Idea is to provide a common way to control all alternate functions. Note that this improvement does not support the old-fashioned way used to control nomadik pins, namely the "nmk_config_pin()" function and its derivatives. Signed-off-by: Jean-Nicolas Graux <jean-nicolas.graux@stericsson.com> Reviewed-by: Philippe Langlais <philippe.langlais@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-09Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds6-0/+1804
Pull MIPS update from Ralf Baechle: "This is the MIPS update for 3.7. A fair chunk of them are platform updates to the Cavium Octeon SOC (which involves machine generated header files of considerable size), Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx platforms. Support for the commercial MIPS simulator MIPSsim has been removed as MIPS Technologies is shifting away from this product and Qemu is offering various more powerful platforms. The generic MIPS code can now also probe for no-execute / write-only TLB features implemented without the full SmartMIPS extension as permitted by the latest MIPS processor architecture. Lots of small changes to generic code." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits) MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x MIPS: BCM63XX: Properly handle mac address octet overflow MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user. MIPS: Replace `-' in defconfig filename wth `_' for consistency. MIPS: Wire kcmp syscall. MIPS: MIPSsim: Remove the MIPSsim platform. MIPS: NOTIFY_RESUME is not needed in TIF masks MIPS: Merge the identical "return from syscall" per-ABI code MIPS: Unobfuscate _TIF..._MASK MIPS: Prevent hitting do_notify_resume() with !user_mode(regs). MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. MIPS: Add base architecture support for RI and XI. MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. MIPS: uasm: Add INS and EXT instructions. MIPS: Avoid pipeline stalls on some MIPS32R2 cores. MIPS: Make VPE count to be one-based. MIPS: Add new end of interrupt functionality for GIC. MIPS: Add EIC support for GIC. MIPS: Code clean-ups for the GIC. ...
2012-10-07Merge tag 'soc-late' of ↵Linus Torvalds8-0/+2954
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull late ARM soc platform updates from Olof Johansson: "This branch contains updates to OMAP and Marvell platforms (kirkwood, dove, mvebu) that came in after we had done the big multiplatform merges, so they were kept separate from the rest, and not separated into the traditional topics of cleanup/driver/platform features. For OMAP, the updates are: - Runtime PM conversions for the GPMC and RNG IP blocks - Preparation patches for the OMAP common clock framework conversion - clkdev alias additions required by other drivers - Performance Monitoring Unit (PMU) support for OMAP2, 3, and non-4430 OMAP4 - OMAP hwmod code and data improvements - Preparation patches for the IOMMU runtime PM conversion - Preparation patches for OMAP4 full-chip retention support For Kirkwood/Dove/mvebu: - New driver for "address decoder controller" for mvebu, which is a piece of hardware that configures addressable devices and peripherals. First user is the boot rom aperture on armada XP since it is needed for SMP support. - New device tree bindings for peripherals such as gpio-fan, iconnect nand, mv_cesa and the above address decoder controller. - Some defconfig updates, mostly to enable new DT boards and a few drivers. - New drivers using the pincontrol subsystem for dove, kirkwood and mvebu - New clean gpio driver for mvebu" * tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (98 commits) ARM: mvebu: fix build breaks from multi-platform conversion ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70 ARM: OMAP2+: PMU: Add runtime PM support ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD ARM: OMAP3: hwmod data: Add debugss HWMOD data ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP hwrng: OMAP: remove SoC restrictions from driver registration ARM: OMAP: split OMAP1, OMAP2+ RNG device registration hwrng: OMAP: convert to use runtime PM hwrng: OMAP: store per-device data in per-device variables, not file statics ARM: OMAP2xxx: hwmod/CM: add RNG integration data ARM: OMAP2+: gpmc: minimal driver support ARM: OMAP2+: gpmc: Adapt to HWMOD ARM: OMAP2/3: hwmod data: add gpmc ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp ARM: OMAP3: hwmod data: add mmu data for iva and isp ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks ...
2012-10-03Merge tag 'pinctrl-for-v3.7' of ↵Linus Torvalds16-473/+4602
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pinctrl changes from Linus Walleij: "Some of this stuff is hitting arch/arm/* and have been ACKed by the ARM SoC folks, or it's device tree bindings pertaining to the specific driver. These are the bulk pinctrl changes for kernel v3.7: - Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs, provide platform config for the Nomadik. - Add a driver for the i.MX35. - Add a driver for the BCM2835, an advanced GPIO expander. - Various fixes and clean-ups and minor improvements for the core, Nomadik, pinctr-single, sirf drivers. - Some platform config for the ux500." * tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (27 commits) pinctrl: add bcm2835 driver pinctrl: clarify idle vs sleep states pinctrl/nomadik: use irq_find_mapping() pinctrl: sirf: add lost chained_irq_enter and exit in sirfsoc_gpio_handle_irq pinctrl: sirf: initialize the irq_chip pointer of pinctrl_gpio_range pinctrl: sirf: fix spinlock deadlock in sirfsoc_gpio_set_input pinctrl: sirf: add missing pins to pinctrl list pinctrl: sirf: fix a typo in sirfsoc_gpio_probe pinctrl: pinctrl-single: add debugfs pin h/w state info ARM: ux500: 8500: update I2C sleep states pinctrl pinctrl: Fix potential memory leak in pinctrl_register_one_pin() ARM: ux500: tidy up pin sleep modes ARM: ux500: fix spi2 pin group pinctrl: imx: remove duplicated const pinctrl: document semantics vs GPIO ARM: ux500: 8500: use hsit_a_2 group for HSI pinctrl: use kasprintf() in pinmux_request_gpio() pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux pinctrl/nomadik : add MC1_a_2 pin MC1 function group list pinctrl: pinctrl-single: Make sure we do not change bits outside of mask ...
2012-10-02Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds6-0/+1935
Pull ARM soc driver specific changes from Olof Johansson: - A long-coming conversion of various platforms to a common LED infrastructure - AT91 is moved over to use the newer MCI driver for MMC - Pincontrol conversions for samsung platforms - DT bindings for gscaler on samsung - i2c driver fixes for tegra, acked by i2c maintainer Fix up conflicts as per Olof. * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) drivers: bus: omap_l3: use resources instead of hardcoded irqs pinctrl: exynos: Fix wakeup IRQ domain registration check pinctrl: samsung: Uninline samsung_pinctrl_get_soc_data pinctrl: exynos: Correct the detection of wakeup-eint node pinctrl: exynos: Mark exynos_irq_demux_eint as inline pinctrl: exynos: Handle only unmasked wakeup interrupts pinctrl: exynos: Fix typos in gpio/wkup _irq_mask pinctrl: exynos: Set pin function to EINT in irq_set_type of GPIO EINTa drivers: bus: Move the OMAP interconnect driver to drivers/bus/ i2c: tegra: dynamically control fast clk i2c: tegra: I2_M_NOSTART functionality not supported in Tegra20 ARM: tegra: clock: remove unused clock entry for i2c ARM: tegra: clock: add connection name in i2c clock entry i2c: tegra: pass proper name for getting clock ARM: tegra: clock: add i2c fast clock entry in clock table ARM: EXYNOS: Adds G-Scaler device from Device Tree ARM: EXYNOS: Add clock support for G-Scaler ARM: EXYNOS: Enable pinctrl driver support for EXYNOS4 device tree enabled platform ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC ARM: EXYNOS: skip wakeup interrupt setup if pinctrl driver is used ...
2012-10-02Merge tag 'cleanup2' of ↵Linus Torvalds2-2/+44
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM soc cleanups, part 2 from Olof Johansson: "A shorter cleanup branch submitted separately due to dependencies with some of the previous topics. Major thing here is that the Broadcom bcmring platform is removed. It's an SoC that's used on some stationary VoIP platforms, and is in desperate need of some cleanup. Broadcom came back and suggested that we just deprecate the platform for now, since they aren't going to spend the resources needed on cleaning it up, and there are no users of the platform directly from mainline." Fix some conflicts due to BCM2835 getting added next to the removed BCMRING, and removal of tegra files that had been converted to devicetree. * tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: Orion5x: ts78xx: Add IOMEM for virtual addresses. ARM: ux500: use __iomem pointers for MMIO ARM: Remove mach-bcmring ARM: clps711x: Remove board support for CEIVA ARM: clps711x: Fix register definitions ARM: clps711x: Fix lowlevel debug-macro ARM: clps711x: Added simple clock framework pinctrl: tegra: move pinconf-tegra.h content into drivers/pinctrl ARM: tegra: delete unused headers ARM: tegra: remove useless includes of <mach/*.h> ARM: tegra: remove dead code
2012-10-02Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-1/+57
Pull ARM soc device tree updates from Olof Johansson: "Device tree conversion and enablement branch. Mostly a bunch of new bindings and setup for various platforms, but the Via/Winchip VT8500 platform is also converted over from being 100% legacy to now use device tree for probing. More of that will come for 3.8." Trivial conflicts due to removal of vt8500 files, and one documentation file that was added with slightly different contents both here and in the USb tree. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (212 commits) arm: vt8500: Fixup for missing gpio.h ARM: LPC32xx: LED fix in PHY3250 DTS file ARM: dt: mmp-dma: add binding file arm: vt8500: Update arch-vt8500 to devicetree support. arm: vt8500: gpio: Devicetree support for arch-vt8500 arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices arm: vt8500: clk: Add Common Clock Framework support video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb serial: vt8500: Add devicetree support for vt8500-serial rtc: vt8500: Add devicetree support for vt8500-rtc arm: vt8500: Add device tree files for VIA/Wondermedia SoC's ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support ARM: tegra: Add Avionic Design Medcom-Wide support ARM: tegra: Add Avionic Design Plutux support ARM: tegra: Add Avionic Design Tamonten support ARM: tegra: dts: Add pwm label ARM: ux500: Fix SSP register address format ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT ARM: ux500: Add all encompassing sound node to the HREF Device Tree ...
2012-10-01pinctrl: add bcm2835 driverSimon Arlott3-0/+1081
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt controller, and pinmux/control device. Original driver by Simon Arlott. Rewrite including GPIO chip device by Chris Boot. Upstreaming changes by Stephen Warren: * Wrote DT binding documentation. * Changed brcm,function to an integer to more directly match the datasheet, and to match brcm,pins being an integer. * Implemented pull-up/down pin config. * Removed read-only DT property and related code. The restriction this implemented are driven by the board, not the GPIO HW block, so don't really make sense of a HW block binding, were in general incomplete (since they could only know about the few pins hard-coded into the Raspberry Pi B board design and not the uncommitted GPIOS), and are better represented simply by not writing incorrect data into pin configuration nodes. * Don't set GPIO_IN function select in gpio_request_enable() to avoid glitches; defer this to gpio_set_direction(). Consequently, removed empty bcm2835_pmx_gpio_request_enable(). * Simplified enabled_irq_map[]; make it explicitly 1 entry per bank. * Lifted use of enabled_irq_map[] outside the per-interrupt loop in IRQ handler, thus fixing an issue where the code was indexing into enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID. * Removed locking in IRQ handler, since all other code uses spin_lock_irqsave() and so guarantees it doesn't run concurrently with the handler. * Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of bcm2835_gpio_pins[]. * Remove range-checking from bcm2835_pctl_get_groups_count() since we've decided to trust the pinctrl core. * Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set() directly for simplicity. * Fixed body of dt_free_map() to match latest dt_node_to_map(). * Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl core owns doing this. * Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more descriptive. * Simplified remove(); removed call to non-existent pinctrl_remove_gpio_range(), remove early return on error. * Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's base GPIO number. * Error-handling cleanups in probe(). * Switched to module_platform_driver() rather than open-coding. * Made pin, group, and function names lower-case. * s/broadcom/brcm/ in DT property names. * s/2708/2835/. * Fixed a couple minor checkpatch warnings, and other minor cleanup. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Chris Boot <bootc@bootc.net> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-28pinctrl/nomadik: use irq_find_mapping()Linus Walleij1-3/+1
The code was using a homegrown method of looking up the offset from the irq domain, not to be encouraged. Use the proper irq_find_mapping() call instead. Cc: Lee Jones <lee.jones@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-28pinctrl: sirf: add lost chained_irq_enter and exit in sirfsoc_gpio_handle_irqBarry Song1-0/+6
This patch fixes the chained irq hang issue, tested by DM9000 driver using GPIO0-3(irqnr=131) as the external IRQ on SiRFmarco: $ cat /proc/interrupts CPU0 CPU1 32: 1608 0 GIC sirfsoc_timer0 33: 0 3197 GIC sirfsoc_timer1 50: 10207 0 GIC sirfsoc-uart 56: 2 0 GIC cc0e0000.i2c 70: 44 0 GIC mmc0 131: 333 0 sirf-gpio-irq eth0 ... Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-28pinctrl: sirf: initialize the irq_chip pointer of pinctrl_gpio_rangeBarry Song1-1/+3
This patch initializes the optional irq_chip pointer gc in sirfsoc pinctrl_gpio_range. Signed-off-by: Baohua Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-28pinctrl: sirf: fix spinlock deadlock in sirfsoc_gpio_set_inputBarry Song1-5/+0
sirfsoc_gpio_set_input() is called in those functions which have held the spinlock, so delete the duplicated locking. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-28pinctrl: sirf: add missing pins to pinctrl listBarry Song1-0/+6
We always use pinctrl_request_gpio() to get GPIO, If we don't have these missing pins in the pin list, gpio_request and related operations will fail for them. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-28pinctrl: sirf: fix a typo in sirfsoc_gpio_probeBarry Song1-0/+2
Return 0 while probing success. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-28pinctrl: pinctrl-single: add debugfs pin h/w state infoMatt Porter1-1/+9
Adds support for displaying the individual pin h/w config state. Signed-off-by: Matt Porter <mporter@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-27pinctrl: Fix potential memory leak in pinctrl_register_one_pin()Sachin Kamat1-1/+3
'pindesc' was not freed when returning from an error induced exit path. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-23Merge branch 'kirkwood/drivers' of ↵Olof Johansson8-0/+2954
git://git.infradead.org/users/jcooper/linux into late/kirkwood From Jason Cooper: New drivers: - pinctrl (dove, kirkwood, mvebu) - gpio (mvebu) * 'kirkwood/drivers' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: add gpio support in defconfig arm: mvebu: add DT information for GPIO banks on Armada 370 and XP arm: mvebu: use GPIO support now that a driver is available Documentation: add description of DT binding for the gpio-mvebu driver gpio: introduce gpio-mvebu driver for Marvell SoCs arm: mvebu: select the pinctrl drivers for Armada 370 and Armada XP platforms arm: mvebu: split Kconfig options for Armada 370 and XP ARM: mvebu: adjust Armada XP evaluation board DTS ARM: mvebu: Add pinctrl support to Armada 370 SoC ARM: mvebu: Add pinctrl support to Armada XP SoCs pinctrl: mvebu: add pinctrl driver for Armada XP pinctrl: mvebu: add pinctrl driver for Armada 370 pinctrl: mvebu: kirkwood pinctrl driver pinctrl: mvebu: dove pinctrl driver pinctrl: mvebu: pinctrl driver core Signed-off-by: Olof Johansson <olof@lixom.net>
2012-09-22pinctrl: mvebu: add pinctrl driver for Armada XPThomas Petazzoni3-0/+473
This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22pinctrl: mvebu: add pinctrl driver for Armada 370Thomas Petazzoni3-0/+426
This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22pinctrl: mvebu: kirkwood pinctrl driverSebastian Hesselbarth3-0/+477
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22pinctrl: mvebu: dove pinctrl driverSebastian Hesselbarth3-0/+625
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22pinctrl: mvebu: pinctrl driver coreSebastian Hesselbarth4-0/+953
This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net> Conflicts: arch/arm/Kconfig
2012-09-21Merge branch 'next/dt' into next/multiplatformOlof Johansson1-1/+57
* next/dt: (182 commits) ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support ARM: tegra: Add Avionic Design Medcom-Wide support ARM: tegra: Add Avionic Design Plutux support ARM: tegra: Add Avionic Design Tamonten support ARM: tegra: dts: Add pwm label ARM: dt: tegra: whistler: configure power off ARM: mxs: m28evk: Disable OCOTP OUI loading ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent ARM: dts: imx6q-sabrelite: add usbotg pinctrl support ARM: dts: imx23-olinuxino: Add USB host support ARM: dts: imx6q-sabrelite: add usbmisc device ARM: dts: mx23: Add USB resources ARM: dts: mxs: Add ethernetX to macX aliases ARM: msm: Remove non-DT targets from 8960 ARM: msm: Add DT support for 8960 ARM: msm: Move io mapping prototypes to common.h ARM: msm: Rename board-msm8x60 to signify its DT only status ARM: msm: Make 8660 a DT only target ARM: msm: Move 8660 to DT timer ARM: msm: Add DT support to msm_timer ...
2012-09-21pinctrl: exynos: Fix wakeup IRQ domain registration checkTomasz Figa1-1/+1
Because of a typo, incorrect field of a structure was being checked. This patch fixes the check to use correct field. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-21pinctrl: samsung: Uninline samsung_pinctrl_get_soc_dataTomasz Figa1-1/+1
Although the function is used only a single time, it is not performance critical and it is pretty heavy, so let the compiler decide whether to inline it instead. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-21pinctrl: exynos: Correct the detection of wakeup-eint nodeTomasz Figa1-5/+9
Current way of finding the wakeup-eint node scans the whole device tree not only children of the pinctrl node, so it might detect a wakeup-eint node of another pinctrl device. This patch limits the scope of looking for nodes only to subnodes of the pinctrl node. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-21pinctrl: exynos: Mark exynos_irq_demux_eint as inlineTomasz Figa1-1/+1
The exynos_irq_demux_eint utility function is used in chained IRQ handler for EINT16-31 to handle multiplexed interrupts. Inlining it should improve the performance a bit. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-21pinctrl: exynos: Handle only unmasked wakeup interruptsTomasz Figa1-2/+5
A bit in EINTxx_PEND register is set regardless of interrupt mask, which causes spurious interrupts. To avoid them, the read value of pending register must be masked with current interrupt mask manually. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-21pinctrl: exynos: Fix typos in gpio/wkup _irq_maskTomasz Figa1-2/+2
To mask GPIO/wakeup IRQ, the corresponding bit in mask register has to be set. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-21pinctrl: exynos: Set pin function to EINT in irq_set_type of GPIO EINTaTomasz Figa2-0/+13
Pins used as GPIO interrupts need to be configured as EINTs. This patch adds the required configuration code to exynos_gpio_irq_set_type, to set the pin as EINT when its interrupt trigger is configured. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-18pinctrl: imx: remove duplicated constRichard Zhao1-1/+1
fix smatch warning: drivers/pinctrl/pinctrl-imx.c:435:21: warning: duplicate const Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-14pinctrl: tegra: move pinconf-tegra.h content into drivers/pinctrlStephen Warren2-2/+44
Now that Tegra's pinmux is configured solely from device tree, there's no need for the pinconf types to be defined in arch/arm/mach-tegra/. Move it into the pinctrl directory to clean up mach-tegra, as a pre- requisite for single-zImage. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-14pinctrl: use kasprintf() in pinmux_request_gpio()Thomas Petazzoni1-4/+1
Instead of using a temporary buffer, snprintf() and kstrdup(), just use kasprintf() that does the same thing in just oneline. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Colin Cross <ccross@google.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-13OF: pinctrl: MIPS: lantiq: adds support for FALCON SoCJohn Crispin3-0/+474
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
2012-09-13OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl supportJohn Crispin5-0/+1330
Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
2012-09-13pinctrl: pinctrl-single: Add pinctrl-single,bits type of muxPeter Ujfalusi1-10/+36
With pinctrl-single,bits it is possible to update just part of the register within the pinctrl-single,function-mask area. This is useful when one register configures mmore than one pin's mux. pinctrl-single,bits takes three parameters: <reg offset, value, sub-mask> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> [Removed a misplaced comment] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-10pinctrl/nomadik : add MC1_a_2 pin MC1 function group listPatrice Chotard1-1/+4
Another possible pin configuration for the MC1 pin group. Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-10pinctrl: pinctrl-single: Make sure we do not change bits outside of maskPeter Ujfalusi1-1/+1
Use the pcs->fmask to make sure that the value is not changing (setting) bits in areas where it should not. To avoid situations like this: pmx_dummy: pinmux@4a100040 { compatible = "pinctrl-single"; reg = <0x4a100040 0x0196>; #address-cells = <1>; #size-cells = <0>; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x00ff>; }; &pmx_dummy { pinctrl-names = "default"; pinctrl-0 = <&board_pins>; board_pins: pinmux_board_pins { pinctrl-single,pins = < 0x6c 0xf0f 0x6e 0x10f 0x70 0x23f 0x72 0xa5f >; }; }; Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-07pinctrl: add exynos4210 specific extensions for samsung pinctrl driverThomas Abraham4-0/+782
Add information about the Exynos4210 pin banks and driver data which is used by the Samsung pinctrl driver. In addition to this, the support for external gpio and wakeup interrupt support is included and hooked up with the Samsung pinctrl driver. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07pinctrl: add samsung pinctrl and gpiolib driverThomas Abraham4-0/+1133
Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-05pinctrl: sirf: add DT-binding pinmux mapping supportBarry Song1-1/+57
This makes us possible to define pinmux mapping in board-specific DTS. prima2.dtsi provides all possible (groups,functions) configuration, and device in .dts select configurations from dtsi files. Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-04Merge branch 'cleanup/io-pci' into next/cleanupArnd Bergmann8-24/+14
The io-pci series has gained a merge to resolve a nontrivial conflict. * cleanup/io-pci: ARM: Fix ioremap() of address zero Also includes an update to Linux 3.6-rc3 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-09-03pinctrl/nomadik: MASK_ON_SUSPENDEtienne Carriere1-0/+1
ux500 machines performs pins (GPIO) reconfiguration when entering in the suspended mode. This reconfiguration aims at reaching an ultra low power HW configuration. Due to this HW reconfiguration, some HW devices can change of HW state and have their output signals at level that could generate IRQs. If the non-wakeup IRQs are disabled but not yet masked (delayed interrupt disable feature from the generic irq layer), effective interrupts reach the system only because the system attempt to enter the suspended mode. To prevent such IRQs to trig, all irq chips embedded in ux500 platform should enable their IRQCHIP_MASK_ON_SUSPEND flag. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-03pinctrl: imx5: start numbering pad from 0Shawn Guo2-446/+446
Unlike imx6q pinctrl driver that starts nubmering pad from 0, imx5 pinctrl drivers number pad from 1. It causes problem/confusion when driver accesses imx51_pinctrl_pads array using pin ID as the index. Change imx51_pads and imx53_pads numbering start from 0. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-03pinctrl: pinctrl-imx: add imx35 pinctrl driverUwe Kleine-König3-0/+1604
This is mostly cut'n'paste from the imx51 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx35.h. Changes since (implicit) v1 - remove references to file names in binding documentation - remove sed commands from comments in driver - add explicit numbers for pins and functions Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-03pinctrl/nomadik: add STn8815 ASIC supportLinus Walleij5-0/+377
This adds support for the STN8815 ASIC for the Nomadik pin controller. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-03pinctrl/nomadik: add ASIC DB8450 pinctrl driverPatrice Chotard5-0/+1021
This implements a subdriver for the DB8540 ASIC for the Nomadik pin controller. Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-08-17pinctrl/nomadik: add kp_b_2 keyboard function group listPatrice Chotard1-1/+4
There is yet another way to mux the keyboard, so fix up that group. Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-08-17pinctrl: imx51: fix .conf_reg of MX51_PAD_SD2_CMD__CSPI_MOSIShawn Guo1-1/+1
The .conf_reg of MX51_PAD_SD2_CMD__CSPI_MOSI should be 0x7bc rather than NO_PAD. This error will cause SD2 probe failure. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-23 13:12:41 +0300