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2017-10-08pinctrl: cherryview: fix issues caused by dynamic gpio irqs mappingGrygorii Strashko1-1/+13
New GPIO IRQs are allocated and mapped dynamically by default when GPIO IRQ infrastructure is used by cherryview-pinctrl driver. This causes issues on some Intel platforms [1][2] with broken BIOS which hardcodes Linux IRQ numbers in their ACPI tables. On such platforms cherryview-pinctrl driver should allocate and map all GPIO IRQs at probe time. Side effect - "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n" can be seen at boot log. NOTE. It still may fail if boot sequence will changed and some interrupt controller will be probed before cherryview-pinctrl which will shift Linux IRQ numbering (expected with CONFIG_SPARCE_IRQ enabled). [1] https://bugzilla.kernel.org/show_bug.cgi?id=194945 [2] https://lkml.org/lkml/2017/9/28/153 Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Chris Gorman <chrisjohgorman@gmail.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reported-by: Chris Gorman <chrisjohgorman@gmail.com> Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Chris Gorman <chrisjohgorman@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-27pinctrl/amd: Fix build dependency on pinmux codePetr Mladek1-0/+1
The commit 79d2c8bede2c93f943 ("pinctrl/amd: save pin registers over suspend/resume") caused the following compilation errors: drivers/pinctrl/pinctrl-amd.c: In function ‘amd_gpio_should_save’: drivers/pinctrl/pinctrl-amd.c:741:8: error: ‘const struct pin_desc’ has no member named ‘mux_owner’ if (pd->mux_owner || pd->gpio_owner || ^ drivers/pinctrl/pinctrl-amd.c:741:25: error: ‘const struct pin_desc’ has no member named ‘gpio_owner’ if (pd->mux_owner || pd->gpio_owner || We need to enable CONFIG_PINMUX for this driver as well. Cc: stable@vger.kernel.org Fixes: 79d2c8bede2c93f943 ("pinctrl/amd: save pin registers over suspend/resume") Signed-off-by: Petr Mladek <pmladek@suse.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-21pinctrl: bcm2835: fix build warning in bcm2835_gpio_irq_handle_bankCorentin Labbe1-4/+0
This patch fix the following build warning: drivers/pinctrl/bcm/pinctrl-bcm2835.c:376:15: warning: variable 'type' set but not used [-Wunused-but-set-variable] Furthermore, it is unused for a long time, at least since commit 85ae9e512f43 ("pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP") where a "FIXME no clue why the code looks up the type here" was added. A year after, nobody answeered this question, so its time to remove it. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-12pinctrl/amd: save pin registers over suspend/resumeDaniel Drake2-0/+76
The touchpad in the Asus laptop models X505BA/BP and X542BA/BP is unresponsive after suspend/resume. The following error appears during resume: i2c_hid i2c-ELAN1300:00: failed to reset device. The problem here is that i2c_hid does not notice the interrupt being generated at this point, because the GPIO is no longer configured for interrupts. Fix this by saving pinctrl-amd pin registers during suspend and restoring them at resume time. Based on code from pinctrl-intel. Cc: stable@vger.kernel.org Signed-off-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-12pinctrl: armada-37xx: Fix gpio interrupt setupGregory CLEMENT1-19/+22
Since commit dc749a09ea5e ("gpiolib: allow gpio irqchip to map irqs dynamically"), the irqs for gpio are not statically allocated during in gpiochip_irqchip_add. This driver was based on this assumption for initializing the mask associated to each interrupt this led to a NULL pointer crash in the kernel: Unable to handle kernel NULL pointer dereference at virtual address 00000000 Mem abort info: Exception class = DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 Data abort info: ISV = 0, ISS = 0x00000068 CM = 0, WnR = 1 [0000000000000000] user address but active_mm is swapper Internal error: Oops: 96000044 [#1] PREEMPT SMP Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.13.0-06657-g3b9f8ed25dbe #576 Hardware name: Marvell Armada 3720 Development Board DB-88F3720-DDR3 (DT) task: ffff80001d908000 task.stack: ffff000008068000 PC is at armada_37xx_pinctrl_probe+0x5f8/0x670 LR is at armada_37xx_pinctrl_probe+0x5e8/0x670 pc : [<ffff000008e25cdc>] lr : [<ffff000008e25ccc>] pstate: 60000045 sp : ffff00000806bb80 x29: ffff00000806bb80 x28: 0000000000000024 x27: 000000000000000c x26: 0000000000000001 x25: ffff80001efee760 x24: 0000000000000000 x23: ffff80001db6f570 x22: ffff80001db6f438 x21: 0000000000000000 x20: ffff80001d9f4810 x19: ffff80001db6f418 x18: 0000000000000000 x17: 0000000000000001 x16: 0000000000000019 x15: ffffffffffffffff x14: 0140000000000000 x13: 0000000000000000 x12: 0000000000000030 x11: 0101010101010101 x10: 0000000000000040 x9 : ffff000009923580 x8 : ffff80001d400248 x7 : ffff80001d400270 x6 : 0000000000000000 x5 : ffff80001d400248 x4 : ffff80001d400270 x3 : 0000000000000000 x2 : 0000000000000001 x1 : 0000000000000001 x0 : 0000000000000000 Process swapper/0 (pid: 1, stack limit = 0xffff000008068000) Call trace: Exception stack(0xffff00000806ba40 to 0xffff00000806bb80) ba40: 0000000000000000 0000000000000001 0000000000000001 0000000000000000 ba60: ffff80001d400270 ffff80001d400248 0000000000000000 ffff80001d400270 ba80: ffff80001d400248 ffff000009923580 0000000000000040 0101010101010101 baa0: 0000000000000030 0000000000000000 0140000000000000 ffffffffffffffff bac0: 0000000000000019 0000000000000001 0000000000000000 ffff80001db6f418 bae0: ffff80001d9f4810 0000000000000000 ffff80001db6f438 ffff80001db6f570 bb00: 0000000000000000 ffff80001efee760 0000000000000001 000000000000000c bb20: 0000000000000024 ffff00000806bb80 ffff000008e25ccc ffff00000806bb80 bb40: ffff000008e25cdc 0000000060000045 ffff00000806bb60 ffff0000081189b8 bb60: ffffffffffffffff ffff00000811cf1c ffff00000806bb80 ffff000008e25cdc [<ffff000008e25cdc>] armada_37xx_pinctrl_probe+0x5f8/0x670 [<ffff00000859d8c8>] platform_drv_probe+0x58/0xb8 [<ffff00000859bb44>] driver_probe_device+0x22c/0x2d8 [<ffff00000859bcac>] __driver_attach+0xbc/0xc0 [<ffff000008599c84>] bus_for_each_dev+0x4c/0x98 [<ffff00000859b440>] driver_attach+0x20/0x28 [<ffff00000859af90>] bus_add_driver+0x1b8/0x228 [<ffff00000859c648>] driver_register+0x60/0xf8 [<ffff00000859df64>] __platform_driver_probe+0x74/0x130 [<ffff000008e256dc>] armada_37xx_pinctrl_driver_init+0x20/0x28 [<ffff000008083980>] do_one_initcall+0x38/0x128 [<ffff000008e00cf4>] kernel_init_freeable+0x188/0x22c [<ffff0000089b56e8>] kernel_init+0x10/0x100 [<ffff000008084bb0>] ret_from_fork+0x10/0x18 Code: f9403fa2 12001341 1100075a 9ac12041 (b9000001) ---[ end trace 8b0f4e05e1603208 ]--- This patch moves the initialization of the mask field in the irq_startup function. However some callbacks such as irq_set_type and irq_set_wake could be called before irq_startup. For those functions the mask is computed at each call which is not a issue as these functions are not located in a hot path but are used sporadically for configuration. Fixes: dc749a09ea5e ("gpiolib: allow gpio irqchip to map irqs dynamically") Cc: <stable@vger.kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-12pinctrl: sprd: fix off by one bugsDan Carpenter1-4/+4
info->groups[] has info->ngroups elements so these comparisons should be >= instead of >. Fixes: 41d32cfce1ae ("pinctrl: sprd: Add Spreadtrum pin control driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Baolin Wang <baolin.wang@spreadtrum.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-12pinctrl: sprd: check for allocation failureDan Carpenter1-3/+7
devm_pinctrl_get() could fail with ERR_PTR(-ENOMEM) so I have added a check for that. I also reversed the other IS_ERR() test because it was a little confusing to test one way and then the opposite a couple lines later. Fixes: 41d32cfce1ae ("pinctrl: sprd: Add Spreadtrum pin control driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-12pinctrl: sprd: Restrict PINCTRL_SPRD to ARCH_SPRD or COMPILE_TESTGeert Uytterhoeven1-1/+2
The Spreadtrum pinctrl drivers are only useful when building for a Spreadtrum platform. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-12pinctrl: sprd: fix build errors and dependenciesRandy Dunlap1-0/+2
Fix build errors when CONFIG_OF is not enabled. Also, the pinctrl-sprd-sc9860 driver uses functions from the pinctrl-sprd driver, so the former should depend on the latter driver. ../drivers/pinctrl/sprd/pinctrl-sprd.c: In function 'sprd_dt_node_to_map': ../drivers/pinctrl/sprd/pinctrl-sprd.c:290:2: error: implicit declaration of function 'pinconf_generic_parse_dt_config' [-Werror=implicit-function-declaration] ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, ^ ../drivers/pinctrl/sprd/pinctrl-sprd.c: At top level: ../drivers/pinctrl/sprd/pinctrl-sprd.c:844:44: error: array type has incomplete element type static const struct pinconf_generic_params sprd_dt_params[] = { ^ Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Baolin Wang <baolin.wang@spreadtrum.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-12pinctrl: sprd: make three local functions staticColin Ian King1-7/+7
The functions sprd_pmx_get_function_count, sprd_pmx_get_function_name and sprd_pmx_get_function_groups are local to the source and do not need to be in global scope, so make them static. Cleans up sparse warnings: "symbol 'sprd_pmx_get_function_count' was not declared. Should it be static?" "symbol 'sprd_pmx_get_function_name' was not declared. Should it be static?" "symbol 'sprd_pmx_get_function_groups' was not declared. Should it be static?" Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-12pinctrl: uniphier: include <linux/build_bug.h> instead of <linux/bug.h>Masahiro Yamada1-1/+1
The #includes <linux/bug.h> is here to use BUILD_BUG_ON_ZERO(). Thanks to commit bc6245e5efd7 ("bug: split BUILD_BUG stuff out into <linux/build_bug.h>"), it is now possible to reduce the number of headers pulled in. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-07Merge tag 'mfd-next-4.14' of ↵Linus Torvalds3-0/+503
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "New Drivers - RK805 Power Management IC (PMIC) - ROHM BD9571MWV-M MFD Power Management IC (PMIC) - Texas Instruments TPS68470 Power Management IC (PMIC) & LEDs New Device Support: - Add support for HiSilicon Hi6421v530 to hi6421-pmic-core - Add support for X-Powers AXP806 to axp20x - Add support for X-Powers AXP813 to axp20x - Add support for Intel Sunrise Point LPSS to intel-lpss-pci New Functionality: - Amend API to provide register layout; atmel-smc Fix-ups: - DT re-work; omap, nokia - Header file location change {I2C => MFD}; dm355evm_msp, tps65010 - Fix chip ID formatting issue(s); rk808 - Optionally register touchscreen devices; da9052-core - Documentation improvements; twl-core - Constification; rtsx_pcr, ab8500-core, da9055-i2c, da9052-spi - Drop unnecessary static declaration; max8925-i2c - Kconfig changes (missing deps and remove module support) - Slim down oversized licence statement; hi6421-pmic-core - Use managed resources (devm_*); lp87565 - Supply proper error checking/handling; t7l66xb Bug Fixes: - Fix counter duplication issue; da9052-core - Fix potential NULL deference issue; max8998 - Leave SPI-NOR write-protection bit alone; lpc_ich - Ensure device is put into reset during suspend; intel-lpss - Correct register offset variable size; omap-usb-tll" * tag 'mfd-next-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (61 commits) mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT dt-bindings: mfd: Add bindings for ZII RAVE devices mfd: omap-usb-tll: Fix register offsets mfd: da9052: Constify spi_device_id mfd: intel-lpss: Put I2C and SPI controllers into reset state on suspend mfd: da9055: Constify i2c_device_id mfd: intel-lpss: Add missing PCI ID for Intel Sunrise Point LPSS devices mfd: t7l66xb: Handle return value of clk_prepare_enable mfd: Add ROHM BD9571MWV-M PMIC DT bindings mfd: intel_soc_pmic_chtwc: Turn Kconfig option into a bool mfd: lp87565: Convert to use devm_mfd_add_devices() mfd: Add support for TPS68470 device mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/Broadwell mfd: syscon: atmel-smc: Add helper to retrieve register layout mfd: axp20x: Use correct platform device ID for many PEK dt-bindings: mfd: axp20x: Introduce bindings for AXP813 mfd: axp20x: Add support for AXP813 PMIC dt-bindings: mfd: axp20x: Add AXP806 to supported list of chips mfd: Add ROHM BD9571MWV-M MFD PMIC driver ...
2017-09-05Merge branches 'ib-mfd-arm-i2c-4.14', 'ib-mfd-arm-usb-video-4.14', ↵Lee Jones10-19/+545
'ib-mfd-hwmon-4.14', 'ib-mfd-iio-pwm-4.14', 'ib-mfd-input-rtc-4.14', 'ib-mfd-many-4.14' and 'ib-mfd-pinctrl-regulator-4.14' into ibs-for-mfd-merged
2017-08-31Revert "pinctrl: sunxi: Don't enforce bias disable (for now)"Priit Laes1-1/+2
This reverts commit 2154d94b40ea2a5de05245521371d0461bb0d669. The original patch was intented to avoid some issues with the sunxi gpio rework and was supposed to be reverted after all the required DT bits had been merged around v4.10. Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: uniphier: fix members of rmii group for Pro4Kunihiko Hayashi1-1/+1
The ether_rmii_groups should have "ether_rmii" and "ether_rmiib" as members. This patch replaces to them. Fixes: 1e359ab1285e ("pinctrl: uniphier: add Ethernet pin-mux settings") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: Delete an error messageMarkus Elfring1-4/+1
Omit an extra message for a memory allocation failure in these functions. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: core: Delete an error messageMarkus Elfring1-1/+0
Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: intel: Read back TX buffer stateAndy Shevchenko1-1/+6
In the same way as it's done in pinctrl-cherryview.c we would provide a readback TX buffer state. Fixes: 17fab473693 ("pinctrl: intel: Set pin direction properly") Reported-by: "Bourque, Francis" <francis.bourque@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: "Bourque, Francis" <francis.bourque@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: rockchip: Add rv1108 recalculated iomux supportDavid Wu1-1/+67
The pins from GPIO1A0 to GPIO1B1 are special, need to recalculate iomux. And the register offset is larger than the u8 range, so changed to u32. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: intel: Decrease indentation in intel_gpio_set()Andy Shevchenko1-12/+12
Decrease indentation in intel_gpio_set() to make it looking slightly better and be in align with intel_gpio_get(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: rza1: Remove suffix from gpiochip labelJacopo Mondi1-2/+2
The OF node name already contains the gpio chip identifier, no need to append it when creating the label. The following debug message clearly shows the suffix is not required "pinctrl-rza1 fcfe3000.pin-controller: Parsed gpiochip gpio-0-0 with 6 pins" Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: qcom: spmi-gpio: Correct power_source range checkFenglin Wu1-1/+1
Power source selection in DIG_VIN_CTL is indexed from 0, in the range check it shouldn't be equal to the total number of power sources. Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: freescale: make mxs_regs constBhumika Goyal2-2/+2
Make these const as they are only stored in the const field of a mxs_pinctrl_soc_data structure. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: aspeed: Rework strap register write logic for the AST2500Andrew Jeffery1-10/+16
Yong Li found that writes to the AST2500 strapping register were not properly supported by the Aspeed pinctrl core and provided a patch to rectify the problem. Several revisions of the patch were posted and ultimately v4 should have been applied, however some unfortunate liberal application of tags on my part lead to confusion between v3[1] and v4[2]. Generate the diff between v3 and v4 to apply as a fixup patch. [1] http://patchwork.ozlabs.org/patch/801662/ [2] http://patchwork.ozlabs.org/patch/802946/ Cc: Yong Li <sdliyong@gmail.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: rza1: off by one in rza1_parse_gpiochip()Dan Carpenter1-1/+1
The rza1_pctl->ports[] array has RZA1_NPORTS (12) elements. The > here should be >= to prevent an out of bounds access. Fixes: 5a49b644b307 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: qcom: General Purpose clocks for apq8064Vinay Simha BN1-6/+36
Add support for general purpose (GP) clocks for apq8064 DT binding documentation updated for qcom,apq8064-pinctrl general purpose (GP) clocks. Signed-off-by: Vinay Simha BN <simhavcs@gmail.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: sprd: Add Spreadtrum pin control driverBaolin Wang7-0/+2173
This patch adds the pin control driver for Spreadtrum SC9860 platform. Signed-off-by: Baolin Wang <baolin.wang@spreadtrum.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: Add sleep related state to indicate sleep related configsBaolin Wang1-0/+2
In some scenarios, we should set some pins as input/output/pullup/pulldown when the specified system goes into deep sleep mode, then when the system goes into deep sleep mode, these pins will be set automatically by hardware. That means some pins are not controlled by any specific driver in the OS, but need to be controlled when entering sleep mode. Thus we introduce one sleep state config into pinconf-generic for users to configure. Signed-off-by: Baolin Wang <baolin.wang@spreadtrum.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-31pinctrl: mediatek: update PCIe mux data for MT7623Ryder Lee1-0/+12
MT2701 shares the same driver with MT7623, but there is a slight difference between their pin functions (e.g., PCIe), so we update the different parts in pinmux table. Doing so, SoC could choose the correct mux setting via their own pinfun.h. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Cc: Biao Huang <biao.huang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: intel: Add Intel Lewisburg GPIO supportMika Westerberg3-0/+352
Intel Lewisburg has the same GPIO hardware than Intel Sunrisepoint-H except few differences in register offsets and pin lists. Because of this we add a separate pinctrl driver for Lewisburg. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller supportMika Westerberg1-1/+423
This is desktop version Intel Cannon Lake PCH. The GPIO hardware is the same but pin list differs a bit. Add support for this to the existing Cannon Lake pin controller driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22Merge tag 'sh-pfc-for-v4.14-tag1' of ↵Linus Walleij9-122/+2977
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.14 - Propagate errors on group config, now r8a7740-armadillo800eva.dts is fixed, - Add MSIOF and USB2.0 pin groups on R-Car H3 ES2.0, - Add USB2.0 and USB3.0 pin groups on R-Car M3-W, - Add a missing MMC pin group on R-Car M2-W and RZ/G1M, - Add initial support for R-Car D3, - Small fixes and cleanups.
2017-08-22pinctrl: aspeed: Fix ast2500 strap register write logicYong Li2-2/+18
On AST2500, the hardware strap register(SCU70) only accepts write ‘1’, to clear it to ‘0’, must set bits(write ‘1’) to SCU7C Signed-off-by: Yong Li <sdliyong@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrlIcenowy Zheng1-3/+23
The pin controller of Allwinner H5 has three IRQ banks, however in old versions of drivers and device trees, only two are set, which makes PG bank IRQ not available. If it's directly set to 3, the old device trees will fail to boot. Add a workaround (and a warning) for older device trees, and allow new device trees to use correct 3 IRQ banks. Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: intel: Disable GPIO pin interrupts in suspendRushikesh S Kadam1-0/+1
The fix prevents unintended wakes from second level GPIO pin interrupts. On some Intel Kabylake platforms, it is observed that GPIO pin interrupts can wake the platform from suspend-to-idle, even though the IRQ is not configured as IRQF_NO_SUSPEND or enable_irq_wake(). This can cause undesired wakes on Mobile devices such as Laptops and Chromebook devices. For example a headset jack insertion is not a desired wake source on Chromebook devices. The pinctrl-intel (GPIO controller) driver implements a "Shared IRQ" model. All GPIO pin interrupts are OR'ed and mapped to a first level IRQ14 (or IRQ15). The driver registers an irq_chip struct and maps an irq_domain for the GPIO pin interrupts. The IRQ14 handler demuxes and calls the second level IRQ for the respective pin. In the suspend entry flow, at suspend_noirq stage, the kernel disables IRQs that are not marked for wake. The pinctrl-intel driver does not implement a irq_disable() callback (to take advantage of lazy disabling). The pinctrl-intel GPIO interrupts are not disabled in hardware during suspend entry, and thus are able to wake the SoC out of suspend-to-idle. This patch sets the IRQCHIP_MASK_ON_SUSPEND flag for the GPIO irq_chip, to disable the second level interrupts at suspend_noirq stage via the irq_mask callbacks. The irq_mask callback disables the IRQs in hardware by programming the corresponding GPIO pad registers. Only IRQs that are not marked for wake are disabled. Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-and-tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: vt8500: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-3/+3
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: ti-iodelay: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-2/+2
structures These structures are only stored in fields of a pinctrl_desc structure (confops and pctlops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: tz1090: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-3/+3
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: tz1090-pdc: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-3/+3
structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: tb10x: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-2/+2
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: rza1: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-1/+1
This pinmux_ops structure is only stored in the const pmxops field of a pinctrl_desc structure. Make the pinmux_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: ingenic: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-3/+3
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: adi2: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-2/+2
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: aspeed: g5: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-3/+3
structures These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: aspeed: g4: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-2/+2
structures These structures are only stored in fields of a pinctrl_desc structure (pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: digicolor: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-2/+2
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: sirf: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-2/+2
These structures are only stored in fields of a pinctrl_desc structure (pctlops and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: sirf: atlas7: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-1/+1
structures This pinmux_ops structure is only stored in the const pmxops field of a pinctrl_desc structure. Make the pinmux_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: st: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-3/+3
These structures are only stored in fields of a pinctrl_desc structure (confops, pctlops, and pmxops) that are const. Make the structures const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: armada-37xx: constify pinconf_ops, pinctrl_ops, and pinmux_ops ↵Julia Lawall1-1/+1
structures This pinconf_ops structure is only stored in the const pinconf_ops field of a pinctrl_desc structure. Make the pinconf_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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