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path: root/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
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2020-09-15pinctrl: Rename sh-pfc to renesasGeert Uytterhoeven1-5323/+0
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
2019-10-01Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D"Geert Uytterhoeven1-4/+5
This reverts commit e167d723e1a472d252e5c4baf823b77ce5543b05. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the SEL_SIMCARD_{0,1} definition was to be deleted. However, this errata merely fixed an accidental double definition in the Hardware User's Manual Rev. 1.00. The real definition is still present in later revisions of the manual (Rev. 1.50 and Rev. 2.00). Hence revert the commit to recover the definition. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-4-geert+renesas@glider.be
2019-10-01Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 ↵Geert Uytterhoeven1-9/+11
and SSI_WS2" This reverts commit e87882eb9be10b2b9e28156922c2a47d877f5db4. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the SEL_SSI2_{0,1} definition was to be deleted. However, this errata merely fixed an accidental double definition in the Hardware User's Manual Rev. 1.00. The real definition is still present in later revisions of the manual (Rev. 1.50 and Rev. 2.00). Hence revert the commit to recover the definition. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-3-geert+renesas@glider.be
2019-10-01pinctrl: sh-pfc: r8a77990: Rename AVB_AVTP_{MATCH,CAPTURE} pin functionsTakeshi Kihara1-16/+16
The Hardware Manual Errata for Rev. 1.50 of April 10, 2019 renamed IPSR2 register bit[23:20] value H'3 and register bit[27:24] value H'3 from AVB_AVTP_MATCH_A resp. AVB_AVTP_CAPTURE_A to AVB_AVTP_MATCH resp. AVB_AVTP_CAPTURE. Update the R-Car E3 pin control driver to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Reword, reference errata] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-2-geert+renesas@glider.be
2019-06-04pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pinsGeert Uytterhoeven1-46/+41
Update the R-Car E3 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car E3 SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-05-21pinctrl: sh-pfc: Move PIN_NONE to shared header fileGeert Uytterhoeven1-45/+44
Several drivers have identical definitions for PIN_NONE. Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h, and convert all drivers over to use it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthandGeert Uytterhoeven1-2/+1
It is very common for a pin to support both pull-up and pull-down functionality. Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN. This not only reduces typing, but also avoids the need for several line breaks, and makes many overly long lines shorter, improving readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variantGeert Uytterhoeven1-1/+1
There are two variants of the CPU_ALL_PORT() macro in use: 1. A three-parameter variant, to be provided for SoCs with a linear GPIO pin space ("PORT style"), 2. A two-parameter variant, to be provided for SoCs with 32-port GPIO banks ("GP port style"). Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and to increase naming consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDFTakeshi Kihara1-13/+13
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car E3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitionsTakeshi Kihara1-18/+18
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and IPSR registers are renamed to RTS{0,1,3,4}_#. This patch updates the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car H3 ES1.x, V3M, V3H, and D3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2Takeshi Kihara1-11/+9
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, there is no need to configure MOD_SEL1 bit30 when the SSI_SCK2_{A,B} or SSI_WS2_{A,B} pin functions are selected. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Remove now unused definitions, mark MOD_SEL1 bit30 reserved] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_DTakeshi Kihara1-5/+4
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, there is no need to configure MOD_SEL1 bit31 when the SIM0_D_{A,B} pin function is selected. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Remove now unused definitions, mark MOD_SEL1 bit31 reserved] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_NTakeshi Kihara1-2/+2
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit16 must be set to 0 when the NFALE_A and NFRB_N_A pin functions are selected. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macroGeert Uytterhoeven1-6/+8
Currently the PINMUX_CFG_REG_VAR() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence both the register field widths and the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macroGeert Uytterhoeven1-46/+46
Currently the PINMUX_CFG_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using a new macro GROUPS(). No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Add missing #include <linux/errno.h>Geert Uytterhoeven1-0/+1
Source files using -Exxx error codes should include <linux/errno.h>. On ARM, this header file is included indirectly; on SuperH, it is not, leading to "error: ‘EINVAL’ undeclared" failures when enabling compile-testing later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resumeMarek Vasut1-0/+2
The TDSELCTRL register is responsible for configuring the SDHI/MMC clock return path delay and may be adjusted by the bootloader. Retain the value across suspend/resume to prevent hardware instability after resume. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-03-18pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functionsFabrizio Castro1-8/+8
CANFD is found also on the R8A774C0, therefore move CANFD pin groups and functions to "common". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-03-18pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registersGeert Uytterhoeven1-3/+3
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) renamed the various miscellaneous I/O control registers (IOCTRLx) on R-Car E3, to reflect better their actual purposes, and matching other SoCs. Update the code to match this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-02-05pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functionsTakeshi Kihara1-2/+253
This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-21pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functionsTakeshi Kihara1-2/+51
This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-21Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"Geert Uytterhoeven1-18/+5
This reverts commit f4caa6ee736fa8a46c806ba4382c16f7e5a20248. The same can be expressed better by dropping the SH_PFC_PIN_CFG_PULL_DOWN flag from the GPIO description, as it includes returning an error to the caller when trying to configure the pin for pull-down, causing: sh-pfc e6060000.pin-controller: pin_config_set op failed for pin 201 sh-pfc e6060000.pin-controller: Error applying setting, reverse things back sh-pfc e6060000.pin-controller: failed to select default state Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-21pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capabilityGeert Uytterhoeven1-1/+10
Hence remove the SH_PFC_PIN_CFG_PULL_DOWN flag from the GP6_9 GPIO description. Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-21pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numberingTakeshi Kihara1-14/+18
MOD_SEL register bit numbering was different from R-Car E3 SoC and R-Car H3/M3-[WN] SoCs. MOD_SEL 1-bit H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'0 b'0 Set Value = H'1 b'1 b'1 MOD_SEL 2-bits H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'00 b'00 Set Value = H'1 b'01 b'10 Set Value = H'2 b'10 b'01 Set Value = H'3 b'11 b'11 MOD_SEL 3-bits H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'000 b'000 Set Value = H'1 b'001 b'100 Set Value = H'2 b'010 b'010 Set Value = H'3 b'011 b'110 Set Value = H'4 b'100 b'001 Set Value = H'5 b'101 b'101 Set Value = H'6 b'110 b'011 Set Value = H'7 b'111 b'111 This patch replaces the #define name and value of MOD_SEL. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 6d4036a1e3b3 ("pinctrl: sh-pfc: Initial R8A77990 PFC support") [shimoda: Split a patch per SoC and revise the commit log] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: Use macros to do the actual reordering] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
2019-01-21pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2Takeshi Kihara1-5/+5
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are selected. Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-21pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0Takeshi Kihara1-2/+2
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected, and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is selected. Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 SEL_I2C1 field widthGeert Uytterhoeven1-1/+1
The SEL_I2C1 (MOD_SEL0[21:20]) field in Module Select Register 0 has a width of 2 bits, i.e. it allows programming one out of 4 different configurations. However, the MOD_SEL0_21_20 macro contains 8 values instead of 4, overflowing into the subsequent fields in the register, and thus breaking the configuration of the latter. Fix this by dropping the bogus last 4 values, including the non-existent SEL_I2C1_4 configuration. Fixes: 6d4036a1e3b3ac0f ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a77990: Fix IOCTRL reg state after s2ram on R-Car E3Geert Uytterhoeven1-0/+1
Due to an interaction with commit 9f2b76a2db3c4387 ("pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC support"), the state of the I/O Control Registers is saved/restored during s2ram on RZ/G2E, but not on R-Car E3. Hence on R-Car E3, SDHI voltage state is lost after system resume. Fix this by registering the I/O Control Registers on R-Car E3, too. Fixes: 33847a71373cd6ae ("pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a77990: Add support for pull-up only pinsGeert Uytterhoeven1-5/+18
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) states that the USB30_OVC pin supports pull-up only. It has a bit assigned in the pull-enable register (PUEN5), but not in the pull-up/down control register (PUD5). Add a check for this, to prevent configuring a prohibited setting. Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-19pinctrl: sh-pfc: r8a77990: Add CAN FD pins, groups and functionsTakeshi Kihara1-2/+37
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> [geert: Move canfd from common to automotive] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77990: Add CAN pins, groups and functionsTakeshi Kihara1-2/+49
This patch adds CAN{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functionsTakeshi Kihara1-2/+368
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functionsJacopo Mondi1-2/+298
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHITakeshi Kihara1-2/+33
This patch supports the {get,set}_io_voltage operations of SDHI. This operates the IOCTRL30 register on the R8A77990 SoC and makes 1.8V/3.3V signal voltage switch possible. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functionsTakeshi Kihara1-2/+216
This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: r8a77990: Add Audio SSI pins, groups and functionsTakeshi Kihara1-2/+238
This patch adds Audio SSI{0,1,2,3,4,5,6,7,8,9} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [simon: rebase] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: r8a77990: Add Audio clock pins, groups and functionsTakeshi Kihara1-2/+205
This patch adds AUDIO_CLK{A,B,C}, AUDIO_CLKOUT, AUDIO_CLKOUT{1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [simon: rebase] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-10-02pinctrl: sh-pfc: r8a77990: Add INTC-EX pins, groups and functionGeert Uytterhoeven1-2/+62
Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the R-Car E3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-28pinctrl: sh-pfc: rcar: Rename automotive-only arrays to automotiveGeert Uytterhoeven1-4/+4
Renesas RZ/G SoCs are pin compatible with R-Car SoCs, but lack several automotive-specific peripherals. Currently pin groups and functions for automotive-specific peripherals are grouped in arrays named after the automative SoC part numbers. Rename them to "automotive" for clarity and consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-19pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC supportFabrizio Castro1-151/+188
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car E3 (a.k.a. r8a77990), however it doesn't have several automotive specific peripherals. Add a r8a77990 specific pin groups/functions along with common pin groups/functions for supporting both r8a77990 and r8a774c0 SoCs. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11pinctrl: sh-pfc: r8a77990: Add MSIOF pins, groups and functionsTakeshi Kihara1-0/+405
This patch adds MSIOF{0,1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-30pinctrl: sh-pfc: r8a77990: Add DU pins, groups and functionLaurent Pinchart1-0/+110
This patch adds DU pins, groups and function for the R8A77990 (E3) SoC. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28pinctrl: sh-pfc: r8a77990: Add PWM pins, groups and functionsTakeshi Kihara1-0/+211
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-07-16pinctrl: sh-pfc: r8a77990: Add USB3.0 pins, groups and functionsTakeshi Kihara1-0/+27
This patch adds USB30_{PWEN,OVC} and USB3HS0_ID pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-16pinctrl: sh-pfc: r8a77990: Add USB2.0 pins, groups and functionsTakeshi Kihara1-0/+38
This patch adds USB0_{PWEN,OVC}_{A,B} and USB0_ID pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-16pinctrl: sh-pfc: r8a77990: Revise USB ID pin nameYoshihiro Shimoda1-2/+2
Since the datasheet Rev.1.00 has an error about the USB ID pin name, this patch revises it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-23pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functionsTakeshi Kihara1-0/+90
This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP pins for the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-05-23pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and functionsTakeshi Kihara1-0/+190
This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to the R8A77990 SoC. NOTE: I2C0 and I2C3 are not pin multiplexed. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-05-23pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functionsTakeshi Kihara1-0/+365
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-05-23pinctrl: sh-pfc: r8a77990: Add bias pinconf supportTakeshi Kihara1-9/+331
This patch implements control of pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-16 16:05:53 +0300