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path: root/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
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2017-05-16pinctrl: sh-pfc: r8a7796: Add Audio clock pin supportKuninori Morimoto1-0/+160
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16pinctrl: sh-pfc: r8a7796: Add Audio SSI pin supportKuninori Morimoto1-0/+231
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-16pinctrl: sh-pfc: r8a7796: Rename SSI_{WS,SCK}34 to SSI_{WS,SCK}349Kuninori Morimoto1-10/+10
R-Car Gen3 is using SSI_{WS,SCK}349 instead of SSI_{WS,SCK}34. But, current code is based on old datasheet which had typo. This patch fixes this typo. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15pinctrl: sh-pfc: r8a7796: Rename SSI_{WS,SCK}0129 to SSI_{WS,SCK}01239Kuninori Morimoto1-6/+6
Based on Rev 0.50 or later R-Car Gen3 datasheet. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pinsGeert Uytterhoeven1-3/+27
Group the AVB pins into similar groups as found in other sh-pfc drivers. The pins can not be muxed between functions other than AVB, but their drive strengths can be controlled. The group avb_mdc containing ADV_MDC and ADV_MDIO is called avb_mdio on R-Car Gen2 SoCs. In pfc-r8a7796 the avb_mdc group already existed and is in use in DT. Therefore add the ADV_MDIO pin to the existing group instead of renaming it. Based on commit b25719eb938eb39a ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-05-15pinctrl: sh-pfc: r8a7796: Add PWM pins, groups and functionsTakeshi Kihara1-0/+153
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27pinctrl: sh-pfc: r8a7796: Add HSCIF pins, groups, and functionsUlrich Hecht1-0/+283
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> [geert: Fix hscif2_clk_[bc]_mux[] and hscif4_ctrl_mux[]] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27pinctrl: sh-pfc: r8a7796: Add MSIOF pins, groups and functionsTakeshi Kihara1-0/+913
This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Correct MSIOF3 SS1_E/SS2_E pins] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27pinctrl: sh-pfc: r8a7796: Add CAN FD supportChris Paterson1-0/+37
This patch adds CAN FD[0-1] pinmux support to r8a7796 SoC. Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27pinctrl: sh-pfc: r8a7796: Add CAN supportChris Paterson1-0/+52
This patch adds CAN[0-1] pinmux support to r8a7796 SoC. Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27pinctrl: sh-pfc: r8a7796: Add bias pinconf supportNiklas Söderlund1-39/+315
Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27pinctrl: sh-pfc: r8a7796: Add drive strength supportNiklas Söderlund1-12/+347
Define the drive strength registers for the R8A7796. Add pins which are not part of a GPIO bank nor can be muxed between different functions but which still allow for their drive-strength to be configured. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15pinctrl: sh-pfc: r8a7796: Add DU supportNiklas Söderlund1-0/+101
Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Based on a similar patch from Laurent Pinchart for the r8a7795 PFC driver. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-15pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functionsTakeshi Kihara1-0/+87
This patch adds AVB_LINK, AVB_MAGIC, AVB_PHY_INT, AVB_MDC, AVB_AVTP_PPS, AVB_AVTP_MATCH, AVB_AVTP_CAPTURE pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07pinctrl: sh-pfc: r8a7796: Fix GPSR definitions for SDHI2/3Geert Uytterhoeven1-10/+10
Fix off-by-one (row and/or register) errors in links to Peripheral Function Select Register bitfields from GPIO/Peripheral Function Select Register 4 macros for SDHI2 and SDHI3 pins. Based on rev. 0.52E of the R-Car Gen3 User's Manual. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
2016-10-17pinctrl: sh-pfc: r8a7796: Add DRIF supportRamesh Shanmugasundaram1-0/+291
This patch adds DRIF[0-3] pinmux support for r8a7796 SoC. Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17pinctrl: sh-pfc: r8a7796: Add I2C pin supportUlrich Hecht1-0/+77
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12pinctrl: sh-pfc: r8a7796: Add voltage switch operations for SDHISimon Horman1-2/+26
This patch supports the {get,set}_io_voltage operations of SDHI. This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v voltage switch. Based on work by Takeshi Kihara and Wolfram Sang. Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-19pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functionsTakeshi Kihara1-0/+275
This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-19pinctrl: sh-pfc: r8a7796: Add SCIF pins, groups and functionsTakeshi Kihara1-0/+300
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-19pinctrl: sh-pfc: Initial R8A7796 PFC supportTakeshi Kihara1-0/+2072
This patch adds initial pinctrl driver to support for the R8A7796 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: rebased on top of renesas-drivers] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-07 07:45:01 +0300