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4 dayspinctrl: qcom: lpass-lpi: mark the GPIO controller as sleepingBartosz Golaszewski1-1/+1
commit ebc18e9854e5a2b62a041fb57b216a903af45b85 upstream. The gpio_chip settings in this driver say the controller can't sleep but it actually uses a mutex for synchronization. This triggers the following BUG(): [ 9.233659] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:281 [ 9.233665] in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 554, name: (udev-worker) [ 9.233669] preempt_count: 1, expected: 0 [ 9.233673] RCU nest depth: 0, expected: 0 [ 9.233688] Tainted: [W]=WARN [ 9.233690] Hardware name: Dell Inc. Latitude 7455/0FK7MX, BIOS 2.10.1 05/20/2025 [ 9.233694] Call trace: [ 9.233696] show_stack+0x24/0x38 (C) [ 9.233709] dump_stack_lvl+0x40/0x88 [ 9.233716] dump_stack+0x18/0x24 [ 9.233722] __might_resched+0x148/0x160 [ 9.233731] __might_sleep+0x38/0x98 [ 9.233736] mutex_lock+0x30/0xd8 [ 9.233749] lpi_config_set+0x2e8/0x3c8 [pinctrl_lpass_lpi] [ 9.233757] lpi_gpio_direction_output+0x58/0x90 [pinctrl_lpass_lpi] [ 9.233761] gpiod_direction_output_raw_commit+0x110/0x428 [ 9.233772] gpiod_direction_output_nonotify+0x234/0x358 [ 9.233779] gpiod_direction_output+0x38/0xd0 [ 9.233786] gpio_shared_proxy_direction_output+0xb8/0x2a8 [gpio_shared_proxy] [ 9.233792] gpiod_direction_output_raw_commit+0x110/0x428 [ 9.233799] gpiod_direction_output_nonotify+0x234/0x358 [ 9.233806] gpiod_configure_flags+0x2c0/0x580 [ 9.233812] gpiod_find_and_request+0x358/0x4f8 [ 9.233819] gpiod_get_index+0x7c/0x98 [ 9.233826] devm_gpiod_get+0x34/0xb0 [ 9.233829] reset_gpio_probe+0x58/0x128 [reset_gpio] [ 9.233836] auxiliary_bus_probe+0xb0/0xf0 [ 9.233845] really_probe+0x14c/0x450 [ 9.233853] __driver_probe_device+0xb0/0x188 [ 9.233858] driver_probe_device+0x4c/0x250 [ 9.233863] __driver_attach+0xf8/0x2a0 [ 9.233868] bus_for_each_dev+0xf8/0x158 [ 9.233872] driver_attach+0x30/0x48 [ 9.233876] bus_add_driver+0x158/0x2b8 [ 9.233880] driver_register+0x74/0x118 [ 9.233886] __auxiliary_driver_register+0x94/0xe8 [ 9.233893] init_module+0x34/0xfd0 [reset_gpio] [ 9.233898] do_one_initcall+0xec/0x300 [ 9.233903] do_init_module+0x64/0x260 [ 9.233910] load_module+0x16c4/0x1900 [ 9.233915] __arm64_sys_finit_module+0x24c/0x378 [ 9.233919] invoke_syscall+0x4c/0xe8 [ 9.233925] el0_svc_common+0x8c/0xf0 [ 9.233929] do_el0_svc+0x28/0x40 [ 9.233934] el0_svc+0x38/0x100 [ 9.233938] el0t_64_sync_handler+0x84/0x130 [ 9.233943] el0t_64_sync+0x17c/0x180 Mark the controller as sleeping. Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Cc: stable@vger.kernel.org Reported-by: Val Packett <val@packett.cool> Closes: https://lore.kernel.org/all/98c0f185-b0e0-49ea-896c-f3972dd011ca@packett.cool/ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
10 dayspinctrl: qcom: msm: Fix deadlock in pinmux configurationPraveen Talari1-1/+1
[ Upstream commit 1c2e70397b4125022dba80f6111271a37fb36bae ] Replace disable_irq() with disable_irq_nosync() in msm_pinmux_set_mux() to prevent deadlock when wakeup IRQ is triggered on the same GPIO being reconfigured. The issue occurs when a wakeup IRQ is triggered on a GPIO and the IRQ handler attempts to reconfigure the same GPIO's pinmux. In this scenario, msm_pinmux_set_mux() calls disable_irq() which waits for the currently running IRQ handler to complete, creating a circular dependency that results in deadlock. Using disable_irq_nosync() avoids waiting for the IRQ handler to complete, preventing the deadlock condition while still properly disabling the interrupt during pinmux reconfiguration. Suggested-by: Prasad Sodagudi <prasad.sodagudi@oss.qualcomm.com> Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2025-07-17pinctrl: qcom: msm: mark certain pins as invalid for interruptsBartosz Golaszewski1-0/+20
commit 93712205ce2f1fb047739494c0399a26ea4f0890 upstream. On some platforms, the UFS-reset pin has no interrupt logic in TLMM but is nevertheless registered as a GPIO in the kernel. This enables the user-space to trigger a BUG() in the pinctrl-msm driver by running, for example: `gpiomon -c 0 113` on RB2. The exact culprit is requesting pins whose intr_detection_width setting is not 1 or 2 for interrupts. This hits a BUG() in msm_gpio_irq_set_type(). Potentially crashing the kernel due to an invalid request from user-space is not optimal, so let's go through the pins and mark those that would fail the check as invalid for the irq chip as we should not even register them as available irqs. This function can be extended if we determine that there are more corner-cases like this. Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") Cc: stable@vger.kernel.org Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250612091448.41546-1-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-06-19pinctrl: qcom: pinctrl-qcm2290: Add missing pinsWojciech Slenska1-0/+9
[ Upstream commit 315345610faee8a0568b522dba9e35067d1732ab ] Added the missing pins to the qcm2290_pins table. Signed-off-by: Wojciech Slenska <wojciech.slenska@gmail.com> Fixes: 48e049ef1238 ("pinctrl: qcom: Add QCM2290 pinctrl driver") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/20250523101437.59092-1-wojciech.slenska@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2025-06-04pinctrl: qcom: switch to devm_register_sys_off_handler()Dmitry Baryshkov1-11/+12
[ Upstream commit 41e452e6933d14146381ea25cff5e4d1ac2abea1 ] Error-handling paths in msm_pinctrl_probe() don't call a function required to unroll restart handler registration, unregister_restart_handler(). Instead of adding calls to this function, switch the msm pinctrl code into using devm_register_sys_off_handler(). Fixes: cf1fc1876289 ("pinctrl: qcom: use restart_notifier mechanism for ps_hold") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/20250513-pinctrl-msm-fix-v2-2-249999af0fc1@oss.qualcomm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2025-06-04pinctrl: qcom/msm: Convert to platform remove callback returning voidUwe Kleine-König49-51/+49
[ Upstream commit 22ee670a8ad3ec7cd9d872d4512fe8797130e191 ] The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). To convert all those qcom pinctrl drivers, make msm_pinctrl_remove() return void (instead of zero) and use .remove_new in all drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231009162510.335208-3-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Stable-dep-of: 41e452e6933d ("pinctrl: qcom: switch to devm_register_sys_off_handler()") Signed-off-by: Sasha Levin <sashal@kernel.org>
2025-04-25pinctrl: qcom: Clear latched interrupt status when changing IRQ typeStephan Gerhold1-6/+6
commit e225128c3f8be879e7d4eb71a25949e188b420ae upstream. When submitting the TLMM test driver, Bjorn reported that some of the test cases are failing for GPIOs that not are backed by PDC (i.e. "non-wakeup" GPIOs that are handled directly in pinctrl-msm). Basically, lingering latched interrupt state is still being delivered at IRQ request time, e.g.: ok 1 tlmm_test_silent_rising tlmm_test_silent_falling: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:178 Expected atomic_read(&priv->intr_count) == 0, but atomic_read(&priv->intr_count) == 1 (0x1) not ok 2 tlmm_test_silent_falling tlmm_test_silent_low: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:178 Expected atomic_read(&priv->intr_count) == 0, but atomic_read(&priv->intr_count) == 1 (0x1) not ok 3 tlmm_test_silent_low ok 4 tlmm_test_silent_high Whether to report interrupts that came in while the IRQ was unclaimed doesn't seem to be well-defined in the Linux IRQ API. However, looking closer at these specific cases, we're actually reporting events that do not match the interrupt type requested by the driver: 1. After "ok 1 tlmm_test_silent_rising", the GPIO is in low state and configured for IRQF_TRIGGER_RISING. 2. (a) In preparation for "tlmm_test_silent_falling", the GPIO is switched to high state. The rising interrupt gets latched. (b) The GPIO is re-configured for IRQF_TRIGGER_FALLING, but the latched interrupt isn't cleared. (c) The IRQ handler is called for the latched interrupt, but there wasn't any falling edge. 3. (a) For "tlmm_test_silent_low", the GPIO remains in high state. (b) The GPIO is re-configured for IRQF_TRIGGER_LOW. This seems to result in a phantom interrupt that gets latched. (c) The IRQ handler is called for the latched interrupt, but the GPIO isn't in low state. 4. (a) For "tlmm_test_silent_high", the GPIO is switched to low state. (b) This doesn't result in a latched interrupt, because RAW_STATUS_EN was cleared when masking the level-triggered interrupt. Fix this by clearing the interrupt state whenever making any changes to the interrupt configuration. This includes previously disabled interrupts, but also any changes to interrupt polarity or detection type. With this change, all 16 test cases are now passing for the non-wakeup GPIOs in the TLMM. Cc: stable@vger.kernel.org Fixes: cf9d052aa600 ("pinctrl: qcom: Don't clear pending interrupts when enabling") Reported-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Closes: https://lore.kernel.org/r/20250227-tlmm-test-v1-1-d18877b4a5db@oss.qualcomm.com/ Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Tested-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/20250312-pinctrl-msm-type-latch-v1-1-ce87c561d3d7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-14pinctrl: qcom: spmi-mpp: Add PM8937 compatibleBarnabás Czémán1-0/+1
[ Upstream commit f755261190e88f5d19fe0a3b762f0bbaff6bd438 ] The PM8937 provides 4 MPPs. Add a compatible to support them. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/20241031-msm8917-v2-4-8a075faa89b1@mainlining.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-12-14pinctrl: qcom-pmic-gpio: add support for PM8937Barnabás Czémán1-0/+2
[ Upstream commit 89265a58ff24e3885c2c9ca722bc3aaa47018be9 ] PM8937 has 8 GPIO-s with holes on GPIO3, GPIO4 and GPIO6. Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/20241031-msm8917-v2-2-8a075faa89b1@mainlining.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-12-09pinctrl: qcom: spmi: fix debugfs drive strengthJohan Hovold1-1/+1
commit 6bc0ebfb1d920f13c522545f114cdabb49e9408a upstream. Commit 723e8462a4fe ("pinctrl: qcom: spmi-gpio: Fix the GPIO strength mapping") fixed a long-standing issue in the Qualcomm SPMI PMIC gpio driver which had the 'low' and 'high' drive strength settings switched but failed to update the debugfs interface which still gets this wrong. Fix the debugfs code so that the exported values match the hardware settings. Note that this probably means that most devicetrees that try to describe the firmware settings got this wrong if the settings were derived from debugfs. Before the above mentioned commit the settings would have actually matched the firmware settings even if they were described incorrectly, but now they are inverted. Fixes: 723e8462a4fe ("pinctrl: qcom: spmi-gpio: Fix the GPIO strength mapping") Fixes: eadff3024472 ("pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver") Cc: Anjelique Melendez <quic_amelende@quicinc.com> Cc: stable@vger.kernel.org # 3.19 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/20241025121622.1496-1-johan+linaro@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-07-05pinctrl: qcom: spmi-gpio: drop broken pm8008 supportJohan Hovold1-1/+0
commit 8da86499d4cd125a9561f9cd1de7fba99b0aecbf upstream. The SPMI GPIO driver assumes that the parent device is an SPMI device and accesses random data when backcasting the parent struct device pointer for non-SPMI devices. Fortunately this does not seem to cause any issues currently when the parent device is an I2C client like the PM8008, but this could change if the structures are reorganised (e.g. using structure randomisation). Notably the interrupt implementation is also broken for non-SPMI devices. Also note that the two GPIO pins on PM8008 are used for interrupts and reset so their practical use should be limited. Drop the broken GPIO support for PM8008 for now. Fixes: ea119e5a482a ("pinctrl: qcom-pmic-gpio: Add support for pm8008") Cc: stable@vger.kernel.org # 5.13 Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240529162958.18081-9-johan+linaro@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-06-12pinctrl: qcom: pinctrl-sm7150: Fix sdc1 and ufs special pins regsDanila Tikhonov1-10/+10
[ Upstream commit 5ed79863fae5c06eb33f5cd6b6bdf22dd7089392 ] SDC1 and UFS_RESET special pins are located in the west memory bank. SDC1 have address 0x359a000: 0x3500000 (TLMM BASE) + 0x0 (WEST) + 0x9a000 (SDC1_OFFSET) = 0x359a000 UFS_RESET have address 0x359f000: 0x3500000 (TLMM BASE) + 0x0 (WEST) + 0x9f000 (UFS_OFFSET) = 0x359a000 Fixes: b915395c9e04 ("pinctrl: qcom: Add SM7150 pinctrl driver") Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Message-ID: <20240423203245.188480-1-danila@jiaxyga.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-10-16pinctrl: qcom: lpass-lpi: fix concurrent register updatesKrzysztof Kozlowski1-6/+11
The Qualcomm LPASS LPI pin controller driver uses one lock for guarding Read-Modify-Write code for slew rate registers. However the pin configuration and muxing registers have exactly the same RMW code but are not protected. Pin controller framework does not provide locking here, thus it is possible to trigger simultaneous change of pin configuration registers resulting in non-atomic changes. Protect from concurrent access by re-using the same lock used to cover the slew rate register. Using the same lock instead of adding second one will make more sense, once we add support for newer Qualcomm SoC, where slew rate is configured in the same register as pin configuration/muxing. Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Cc: stable@vger.kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231013145705.219954-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-31Merge tag 'pinctrl-v6.6-1' of ↵Linus Torvalds10-19/+370
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "We have some patches to DTS[I] files in arm and arm64 as well, that were merged here as DT headers were being changed. The most interesting stuff is the Intel Tangier chip support and AMLogic C3 in my opinion. No core changes this time. Drivers: - Intel Tangier SoC pin control support - AMLogic C3 SoC pin control support - Texas Instruments AM654 SoC pin control support - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System) pin control support - Qualcomm PMX75 and PM7550BA (Power Management) pin control support - Qualcomm PMC8180 and PMC8180C (Power Management) pin control support - DROP the Oxnas driver as there is not enough of community interest to keep carrying this ARM(11) port Enhancements: - Bias control in the MT7986 pin control driver - Misc device tree binding enhancements such as the Broadcom 11351 being converted to YAML - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use - Clean up some SPDX headers - Handle non-unique devicetree subnode names in two Renesas drivers" * tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits) pinctrl: mlxbf3: Remove gpio_disable_free() pinctrl: use capital "OR" for multiple licenses in SPDX dt-bindings: pinctrl: renesas,rza2: Use 'additionalProperties' for child nodes pinctrl: cherryview: fix address_space_handler() argument pinctrl: intel: consolidate ACPI dependency pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper pm: Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper pinctrl: mediatek: assign functions to configure pin bias on MT7986 pinctrl: mediatek: fix pull_type data for MT7981 dt-bindings: pinctrl: aspeed: Allow only defined pin mux node properties dt-bindings: pinctrl: Drop 'phandle' properties pinctrl: lynxpoint: Make use of pm_ptr() pinctrl: baytrail: Make use of pm_ptr() pinctrl: intel: Switch to use exported namespace pinctrl: lynxpoint: reuse common functions from pinctrl-intel pinctrl: cherryview: reuse common functions from pinctrl-intel ...
2023-08-15Merge tag 'qcom-pinctrl-6.6' of ↵Linus Walleij3-0/+178
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel Qualcomm pinctrl changes for v6.6 1. Add support for the SM6115 and SM8350 LPASS (Low Power Audio SubSystem) TLMM pin controllers. 2. Add bindings for the Qualcomm PMC8180 and PMC8180C PMICs GPIO pin controllers. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10pinctrl: qcom: Add intr_target_width field to support increased number of ↵Ninad Naik3-3/+9
interrupt targets SA8775 and newer target have added support for an increased number of interrupt targets. To implement this change, the intr_target field, which is used to configure the interrupt target in the interrupt configuration register is increased from 3 bits to 4 bits. In accordance to these updates, a new intr_target_width member is introduced in msm_pingroup structure. This member stores the value of width of intr_target field in the interrupt configuration register. This value is used to dynamically calculate and generate mask for setting the intr_target field. By default, this mask is set to 3 bit wide, to ensure backward compatibility with the older targets. Fixes: 4b6b18559927 ("pinctrl: qcom: add the tlmm driver sa8775p platforms") Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride Signed-off-by: Ninad Naik <quic_ninanaik@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230809100634.3961-1-quic_ninanaik@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07pinctrl: qcom: Remove the unused _groups variable build warningSricharan Ramabadhran1-10/+0
When building with clang toolchain and arm64-randconfig-r015-20230712 kernel test robot reports the below warning. drivers/pinctrl/qcom/pinctrl-ipq5018.c:244:27: warning: unused variable '_groups' [-Wunused-const-variable] static const char * const _groups[] = { ^ 1 warning generated. static const char * const _groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", }; Fixing it by removing the variable. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307120814.vWPY6URk-lkp@intel.com/ Fixes: 725d1c891658 ("pinctrl: qcom: Add IPQ5018 pinctrl driver") Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1689934361-32642-1-git-send-email-quic_srichara@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07pinctrl: qcom: Introduce SM6115 LPI pinctrl driverKonrad Dybcio3-0/+185
Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-26pinctrl: qcom: Introduce SM6115 LPI pinctrl driverKonrad Dybcio3-0/+185
Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-07-24pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMMKrzysztof Kozlowski3-0/+178
Add driver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8250 LPASS pin controller, with difference in one new pin (gpio14) belonging to swr_tx_data. Link: https://lore.kernel.org/r/20230719192058.433517-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-07-20pinctrl: Explicitly include correct DT includesRob Herring4-4/+4
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-20pinctrl: qcom: lpass-lpi: Make the clocks optional, alwaysKonrad Dybcio1-5/+1
Some platforms provide a single clock source to all LPASS peripherals, others provide two, and there are probably others that provide it through magic invisible-to-Linux wires. Rely on bindings to mandate the adequate number of clocks necessary. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230714-topic-lpass_lpi_cleanup-v1-1-dc18b5bd14f7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-17pinctrl: qcom-pmic-gpio: Add support for pmx75Rohit Agarwal1-0/+1
pmx75 pmic support gpio controller so add compatible in the driver. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1688707209-30151-5-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-17pinctrl: qcom-pmic-gpio: Add support for pm7550baRohit Agarwal1-0/+1
pm7550ba pmic support gpio controller so add compatible in the driver. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1688707209-30151-4-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: organize audio drivers in menuconfigKrzysztof Kozlowski1-12/+12
The audio pin controller drivers depend on PINCTRL_LPASS_LPI, but since PINCTRL_LPASS_LPI is not the first entry, they are not displayed in menuconfig as dependent of PINCTRL_LPASS_LPI. Re-order the entries to fix this. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230601152026.1182648-8-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: organize main SoC drivers in new Kconfig.msmKrzysztof Kozlowski2-412/+370
In menuconfig, some entries depending on PINCTRL_MSM are indented and expressed as dependening but some not, because of other Kconfig entries in between, Move all main Qualcomm SoC pin controller driver entries into new Kconfig.msm file so they will be nicely ordered in Kconfig file (by CONFIG_ name) and properly indented as PINCTRL_MSM dependency in menuconfig. Functionally this is the same, but since entire file is guarded with "if PINCTRL_MSM" drop this dependency from individual entries. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230601152026.1182648-7-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: mark true OF dependency - common MSM pinctrl codeKrzysztof Kozlowski1-41/+2
The common MSM pinctrl driver code (PINCTRL_MSM) uses pinconf_generic_dt_node_to_map_group() from GENERIC_PINCONF, which is not available for compile testing for !OF cases. Drivers actually do not depend on OF. Move the OF dependency to the entry actually depending on it and drop any "|| COMPILE_TEST", because OF is required also for compile testing (lack of OF was never visible in compile testing because none of the drivers could be compile tested due to Makefile). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230601152026.1182648-5-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: drop unneeded GPIOLIB dependencyKrzysztof Kozlowski1-14/+8
PINCTRL_MSM depends on GPIOLIB, thus individual driver entries depending on the first do not have to depend on the latter. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230601152026.1182648-4-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: correct language typo (Technologies)Krzysztof Kozlowski1-1/+1
Correct typo: Tehcnologies->Technologies. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230601152026.1182648-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: fix indentation in KconfigKrzysztof Kozlowski1-2/+2
Use tab for correct Kconfig indentation. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230601152026.1182648-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: qdf2xxx: drop ACPI_PTRKrzysztof Kozlowski1-1/+1
Driver can bind only via ACPI matching and acpi_device_id is there unconditionally, so drop useless ACPI_PTR() macro. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230601152026.1182648-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-06-09pinctrl: qcom: Add IPQ5018 pinctrl driverSricharan Ramabadhran3-0/+795
Add pinctrl definitions for the TLMM of IPQ5018. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Co-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/20230608122152.3930377-5-quic_srichara@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-29pinctrl: qcom: Add SDX75 pincontrol driverRohit Agarwal3-11/+1166
Add initial Qualcomm SDX75 pinctrl driver to support pin configuration with pinctrl framework for SDX75 SoC. While at it, reordering the SDX65 entry. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684425432-10072-4-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-22pinctrl: qcom: sa8775p: add the wakeirq mapBartosz Golaszewski1-0/+19
The SA8775P TLMM driver is missing the GPIO-to-wakeup-pin mapping. This adds it. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230515092515.180920-1-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-16pinctrl: qcom: sc8180x: gracefully handle missing IO memory resourceKrzysztof Kozlowski1-1/+5
If device was probed with incorrect DT or ACPI tables, the IO memory resource would be missing and driver would derefernce NULL pointer in sc8180x_pinctrl_add_tile_resources(). Add simplep check if IO memory resource was provided to silence Smatch warning: drivers/pinctrl/qcom/pinctrl-sc8180x.c:1664 sc8180x_pinctrl_add_tile_resources() error: potentially dereferencing uninitialized 'mres'. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230513113510.177666-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-16pinctrl: qcom: Refactor generic qcom pinctrl driverRohit Agarwal47-329/+325
Reuse the generic pingroup struct from pinctrl.h in msm_pingroup along with the macro defined. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684133170-18540-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-16pinctrl: qcom: Remove the msm_function structRohit Agarwal46-6192/+5850
Remove the msm_function struct to reuse the generic pinfunction struct. Also, define a generic PINFUNCTION macro that can be used across qcom target specific pinctrl files to avoid code repetition. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684133170-18540-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-08pinctrl: qcom: spmi-gpio: Add PM8953 supportLuca Weiss1-0/+2
Add support for the 8 GPIOs found on PM8953. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20230421-pm8953-gpio-v1-2-3d33e2de47e3@z3ntu.xyz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-04-21pinctrl: qcom: spmi-gpio: Add PMI632 supportLuca Weiss1-0/+1
Add support for the 8 GPIOs found on PMI632. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230414-pmi632-v2-2-98bafa909c36@z3ntu.xyz Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-04-20pinctrl: qcom ssbi-gpio: Convert to immutable irq_chipLinus Walleij1-3/+21
Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-6-6b59a5186b00@linaro.org
2023-04-20pinctrl: qcom ssbi-mpp: Convert to immutable irq_chipLinus Walleij1-8/+27
Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-5-6b59a5186b00@linaro.org
2023-04-20pinctrl: qcom spmi-mpp: Convert to immutable irq_chipLinus Walleij1-10/+28
Convert the driver to immutable irq-chip with a bit of intuition. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230414-immutable-irqchips-2-v1-4-6b59a5186b00@linaro.org
2023-04-11pinctrl: qcom: Add "and" to PIN_CONFIG_INPUT_ENABLE commentDouglas Anderson1-1/+1
The comment recently added talking about PIN_CONFIG_INPUT_ENABLE is clearly missing the word "and". Comments live forever, so let's fix it. Fixes: e49eabe3e13f ("pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE") Reported-by: Stephen Boyd <swboyd@chromium.org> Link: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/4409769/comment/9a1d5def_e1e71db7/ Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20230407142859.1.Ia5d70e320b60d6707c6182879097708e49b8b519@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-04-11pinctrl: qcom: spmi-gpio: add support for pmm8654au-gpioBartosz Golaszewski1-0/+1
Add support for the GPIO controller present on the pmm8654au PMIC. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230327125316.210812-14-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-29Merge branch 'ib-qcom-quad-spi' into develLinus Walleij1-5/+31
2023-03-29pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLEDouglas Anderson1-5/+31
The Qualcomm pinctrl driver has been violating the documented meaning of PIN_CONFIG_INPUT_ENABLE. That documentation says: Note that this does not affect the pin's ability to drive output. ...yet the Qualcomm driver's sole action when asked to "enable input" on a pin is to disable its output. The Qualcomm driver's implementation stems from the fact that "output-disable" is a "new" property from 2017. It was introduced in commit 425562429d4f ("pinctrl: generic: Add output-enable property"). The "input-enable" handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property"). Let's change the Qualcomm driver to move us in the right direction. As part of this: 1. We'll now support PIN_CONFIG_OUTPUT_ENABLE 2. We'll still support using PIN_CONFIG_INPUT_ENABLE to disable a pin's output (in violation of the docs) with a big comment in the code. This is needed because old device trees have "input-enable" in them and, in some cases, people might need the old behavior. While we could programmatically change all old device trees, it doesn't really hurt to keep supporting the old behavior and we're _supposed_ to try to be compatible with old device trees anyway. It can also be noted that the PIN_CONFIG_INPUT_ENABLE handling code seems to have purposefully ignored its argument. That means that old boards that had _either_ "input-disable" or "input-enable" in them would have had the effect of disabling a pin's output. While we could change this behavior, since we're only leaving the PIN_CONFIG_INPUT_ENABLE there for backward compatibility we might as well be fully backward compatible. NOTE: despite the fact that we'll still support PIN_CONFIG_INPUT_ENABLE for _setting_ config, we take it away from msm_config_group_get(). This appears to be only used for populating debugfs and fixing debugfs to "output enabled" where relevant instead of "input enabled" makes more sense and has more truthiness. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230323102605.8.Id740ae6a993f9313b58add6b10f6a92795d510d4@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-20pinctrl: qcom: Add IPQ9574 pinctrl driverDevi Priya3-0/+838
Add pinctrl definitions for the TLMM of IPQ9574 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20230316072940.29137-5-quic_devipriy@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-19pinctrl: qcom: Add SM7150 pinctrl driverDanila Tikhonov3-0/+1291
Add pinctrl driver for TLMM block found in SM7150 SoC. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20230311212114.108870-3-danila@jiaxyga.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-13pinctrl: qcom: sm8550-lpass-lpi: allow GPIO functionKrzysztof Kozlowski1-0/+8
All LPASS pins have basic GPIO function and most of the code is ready for that. Add missing glue pieces to allow LPASS pins to work as GPIO, which is going to be used on MTP8550 and QRD8550 boards. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230309154949.658380-4-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-03-13pinctrl: qcom: lpass-lpi: allow glitch-free output GPIOKrzysztof Kozlowski1-0/+28
When choosing GPIO function for pins, use the same glitch-free method as main TLMM pinctrl-msm.c driver in msm_pinmux_set_mux(). This replicates the commit d21f4b7ffc22 ("pinctrl: qcom: Avoid glitching lines when we first mux to output") to LPASS pin controller with same justification. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230309154949.658380-3-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2026-01-22 03:58:19 +0300