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2025-04-10pinctrl: intel: Fix wrong bypass assignment in intel_pinctrl_probe_pwm()Andy Shevchenko1-1/+0
[ Upstream commit 0eee258cdf172763502f142d85e967f27a573be0 ] When instantiating PWM, the bypass should be set to false. The field is used for the selected Intel SoCs that do not have PWM feature enabled in their pin control IPs. Fixes: eb78d3604d6b ("pinctrl: intel: Enumerate PWM device when community has a capability") Reported-by: Alexis GUILLEMET <alexis.guillemet@dunasys.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Alexis GUILLEMET <alexis.guillemet@dunasys.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-09-18pinctrl: meteorlake: Add Arrow Lake-H/U ACPI IDMika Westerberg1-0/+1
commit a366e46da10d7bfa1a52c3bd31f342a3d0e8e7fe upstream. Intel Arrow Lake-H/U has the same GPIO hardware than Meteor Lake-P but the ACPI ID is different. Add this new ACPI ID to the list of supported devices. Cc: stable@vger.kernel.org Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-05-17pinctrl: baytrail: Fix selecting gpio pinctrl stateHans de Goede2-36/+42
[ Upstream commit fed6d9a8e6a60ecf6506d0ea004040fbaa109927 ] For all the "score" pin-groups all the intel_pingroup-s to select the non GPIO function are re-used for byt_score_gpio_groups[]. But this is incorrect since a pin-group includes the mode setting, which for the non GPIO functions generally is 1, where as to select the GPIO function mode must be set to 0. So the GPIO function needs separate intel_pingroup-s with their own mode value of 0. Add a new PIN_GROUP_GPIO macro which adds a foo_gpio entry to each pin-group defined this way and update byt_score_gpio_groups[] to point to the new foo_gpio entries. The "sus" usb_oc_grp usb_ulpi_grp and pcu_spi_grp pin-groups are special because these have a non 0 mode value to select the GPIO functions and these already have matching foo_gpio pin-groups, leave these are unchanged. The pmu_clk "sus" groups added in commit 2f46d7f7e959 ("pinctrl: baytrail: Add pinconf group + function for the pmu_clk") do need to use the new PIN_GROUP_GPIO macro. Fixes: 2f46d7f7e959 ("pinctrl: baytrail: Add pinconf group + function for the pmu_clk") Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-02-05pinctrl: baytrail: Fix types of config value in byt_pin_config_set()Andy Shevchenko1-1/+2
[ Upstream commit 1a856a22e6036c5f0d6da7568b4550270f989038 ] When unpacked, the config value is split to two of different types. Fix the types accordingly. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-11-20pinctrl: baytrail: fix debounce disable caseRaag Jadav1-2/+9
[ Upstream commit 2d325e54d9e2e4ae247c9fd03f810208ce958c51 ] We don't need to update debounce pulse value in case debounce is to be disabled. Break such a case where arg value is zero. Fixes: 4cfff5b7af8b ("pinctrl: baytrail: consolidate common mask operation") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/linux-gpio/d164d471-5432-4c3c-afdb-33dc8f53d043@moroto.mountain/ Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-08-22pinctrl: cherryview: fix address_space_handler() argumentRaag Jadav1-3/+2
First argument of acpi_*_address_space_handler() APIs is acpi_handle of the device, which is incorrectly passed in driver ->remove() path here. Fix it by passing the appropriate argument and while at it, make both API calls consistent using ACPI_HANDLE(). Fixes: a0b028597d59 ("pinctrl: cherryview: Add support for GMMR GPIO opregion") Cc: stable@vger.kernel.org Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-22pinctrl: intel: consolidate ACPI dependencyRaag Jadav1-19/+1
Since all the Intel specific platform drivers depend on ACPI, we can consolidate their config dependency. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helperAndy Shevchenko1-7/+3
Since pm.h provides a helper for system no-IRQ PM callbacks, switch the driver to use it instead of open coded variant. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20230717172821.62827-4-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-18pinctrl: lynxpoint: Make use of pm_ptr()Andy Shevchenko1-4/+3
Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that make it simpler and allows the compiler to remove those functions if built without CONFIG_PM and CONFIG_PM_SLEEP support. The lp_gpio_resume() is also assigned to .thaw and .restore members. This is not a problem as the function it enables input pins that had been disabled by firmware and repetion of that doesn't change the pin configuration, i.e. it is idempotent. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20230717172821.62827-6-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-18pinctrl: baytrail: Make use of pm_ptr()Andy Shevchenko1-8/+3
Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that make it simpler and allows the compiler to remove those functions if built without CONFIG_PM and CONFIG_PM_SLEEP support. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20230717172821.62827-3-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: intel: Switch to use exported namespaceAndy Shevchenko16-9/+18
We already have a few symbols exported in the namespace. Let's do the same for others (except PM for now). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15Merge patch series "Reuse common functions from pinctrl-intel"Andy Shevchenko6-236/+57
Raag Jadav <raag.jadav@intel.com> says: This series exports common pinctrl functions that are used across Intel specific platform drivers to PINCTRL_INTEL namespace and reuses them into Baytrail, Cherryview and Lynxpoint drivers. This helps reduce their code and memory footprint. X86 kernels are fairly unikernels such that pinctrl-intel driver is enabled by most Linux distributions and most Intel specific platform drivers (inside drivers/pinctrl/intel) depend on it. The only exception to this is Lynxpoint. But taking into account its fairly old age, it wouldn't suffer much from pinctrl-intel dependency. bloat-o-meter: ============== Intel: add/remove: 17/10 grow/shrink: 0/0 up/down: 375/-319 (56) Total: Before=9598, After=9654, chg +0.58% Baytrail: add/remove: 1/6 grow/shrink: 0/2 up/down: 41/-441 (-400) Total: Before=16538, After=16138, chg -2.42% Cherryview: add/remove: 1/6 grow/shrink: 2/0 up/down: 90/-272 (-182) Total: Before=18133, After=17951, chg -1.00% Lynxpoint: add/remove: 1/6 grow/shrink: 0/1 up/down: 24/-354 (-330) Total: Before=7836, After=7506, chg -4.21% Link: https://lore.kernel.org/r/20230814060311.15945-1-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: lynxpoint: reuse common functions from pinctrl-intelRaag Jadav2-83/+9
Reuse common functions from pinctrl-intel driver. While at it, select pinctrl-intel for Intel Lynxpoint driver. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230814060311.15945-5-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: cherryview: reuse common functions from pinctrl-intelRaag Jadav1-60/+9
Reuse common functions from pinctrl-intel driver. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230814060311.15945-4-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: baytrail: reuse common functions from pinctrl-intelRaag Jadav1-79/+11
Reuse common functions from pinctrl-intel driver. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230814060311.15945-3-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: intel: export common pinctrl functionsRaag Jadav2-14/+28
Export common pinctrl functions that are used across Intel specific platform drivers, so that they can be reused. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230814060311.15945-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15Merge patch series "Introduce Intel Tangier pinctrl driver"Andy Shevchenko7-1277/+778
Raag Jadav <raag.jadav@intel.com> says: Merrifield and Moorefield pinctrl driver implementations are similar in terms of how they access the hardware. We can consolidate their pinctrl functionalities into a common library driver. This patch set introduces: 1. Intel Tangier driver that supports the common pinctrl functionalities for Merrifield and Moorefield platforms. 2. Intel Tangier adaptation for Merrifield pinctrl driver. 3. Intel Tangier adaptation for Moorefield pinctrl driver. Tested on Intel Edison platform. No deviation observed in the contents of below entries before and after this patchset. - /proc/interrupts - /sys/kernel/debug/gpio - /sys/kernel/debug/pinctrl/*/pins Link: https://lore.kernel.org/r/20230814054033.12004-1-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: moorefield: Adapt to Intel Tangier driverRaag Jadav3-622/+37
Make use of Intel Tangier as a library driver for Moorefield. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Link: https://lore.kernel.org/r/20230814054033.12004-4-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: merrifield: Adapt to Intel Tangier driverRaag Jadav3-655/+41
Make use of Intel Tangier as a library driver for Merrifield. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Link: https://lore.kernel.org/r/20230814054033.12004-3-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: tangier: Introduce Intel Tangier driverRaag Jadav5-0/+700
Intel Tangier implements the common pinctrl functionalities for Merrifield and Moorefield platforms. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Link: https://lore.kernel.org/r/20230814054033.12004-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15pinctrl: baytrail: consolidate common mask operationRaag Jadav1-19/+15
Consolidate common mask operation outside of switch cases and limit IO operations to positive cases. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-19pinctrl: cherryview: Drop goto labelAndy Shevchenko1-4/+5
We do not use goto labels in the Intel pin control drivers, so drop the only one in the entire folder. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-19pinctrl: baytrail: invert if conditionRaag Jadav1-3/+1
Invert if condition and get rid of redundant else. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230616203356.27343-4-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-19pinctrl: baytrail: add warning for BYT_VAL_REG retrieval failureRaag Jadav1-0/+8
Add warning for BYT_VAL_REG retrieval failure and continue such case to avoid unintended reads/writes in pm_ops. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230616203356.27343-3-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-19pinctrl: baytrail: reduce scope of spinlock in ->dbg_show() hookRaag Jadav1-10/+10
Reduce scope of spinlock to IO operations in ->dbg_show() hook and save a few bytes. add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-12 (-12) Function old new delta byt_gpio_dbg_show 890 878 -12 Total: Before=17029, After=17017, chg -0.07% Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230616203356.27343-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-15pinctrl: intel: refine ->irq_set_type() hookRaag Jadav1-21/+24
Refine ->irq_set_type() hook and improve its readability by: - Reducing scope of spinlock by moving unneeded operations out of it. - Dropping redundant PADCFG0_RXEVCFG_SHIFT and including it directly into PADCFG0_RXEVCFG_* definitions. - Utilizing temporary variables for common operations. - Simplifying if-else-if chain. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-14pinctrl: intel: refine ->set_mux() hookRaag Jadav1-4/+5
Utilize a temporary variable for common shift operation in ->set_mux() hook and improve readability while saving a few bytes. add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-3 (-3) Function old new delta intel_pinmux_set_mux 245 242 -3 Total: Before=10472, After=10469, chg -0.03% Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230613085054.10976-2-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-12pinctrl: baytrail: Use str_hi_lo() helperAndy Shevchenko1-1/+2
Use str_hi_lo() helper instead of open coding the same. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-07pinctrl: intel: Add Intel Meteor Lake-S pin controller supportAndy Shevchenko1-6/+206
This driver adds pinctrl/GPIO support for Intel Meteor Lake-S. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel pinctrl and GPIO core driver. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-06pinctrl: moorefield: Use BUFCFG_PINMODE_GPIO in ->pin_dbg_show()Andy Shevchenko1-1/+1
Use explicit comparison to BUFCFG_PINMODE_GPIO instead of implying it. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-06pinctrl: moorefield: Fix open-drain pin mode configurationAndy Shevchenko1-2/+12
Currently the pin may not be configured as open-drain in some cases because the argument may be 0 for the boolean types of the pin configurations. Fix this by ignoring the argument. With that, allow to actually restore pin to the push-pull mode. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-06pinctrl: merrifield: Use BUFCFG_PINMODE_GPIO in ->pin_dbg_show()Andy Shevchenko1-1/+1
Use explicit comparison to BUFCFG_PINMODE_GPIO instead of implying it. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-06pinctrl: merrifield: Fix open-drain pin mode configurationAndy Shevchenko1-2/+12
Currently the pin may not be configured as open-drain in some cases because the argument may be 0 for the boolean types of the pin configurations. Fix this by ignoring the argument. With that, allow to actually restore pin to the push-pull mode. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-06pinctrl: cherryview: Return correct value if pin in push-pull modeAndy Shevchenko1-5/+10
Currently the getter returns ENOTSUPP on pin configured in the push-pull mode. Fix this by adding the missed switch case. Fixes: ccdf81d08dbe ("pinctrl: cherryview: add option to set open-drain pin config") Fixes: 6e08d6bbebeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support") Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-02pinctrl: cherryview: Don't use IRQ core constanst for invalid IRQAndy Shevchenko1-1/+1
The semantics of INVALID_HWIRQ is rather localized to IPI usage. Let's keep it that way. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-02pinctrl: baytrail: Use BIT() in BYT_PULL_ASSIGN_* definitionsAndy Shevchenko1-3/+2
The bias setting (pull-up or pull-down) are bit fields and we never enable them both, hence use BIT() macro to define them. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-06-02pinctrl: baytrail: Unify style of error and debug messagesAndy Shevchenko1-41/+23
Use same formatting strings where it makes sense, so linker will utilize only a single copy of it, otherwise make the style similar to the rest of the messages of the close enough semantics. add/remove: 1/0 grow/shrink: 2/2 up/down: 91/-110 (-19) Total: Before=17562, After=17543, chg -0.11% Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-02-22Merge tag 'pinctrl-v6.3-1' of ↵Linus Torvalds22-315/+177
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Nothing special, notably a lot of new Qualcomm hardware is supported, a RISC-V reference SoC and then some cleanups both in code and device tree bindings. Core changes: - Add PINCTRL_PINFUNCTION() macro and use it in several drivers New drivers: - New driver for the StarFive JH7110 SoC "sys" and "aon" (always-on) pin controllers. (RISC-V.) - New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin controller - New subdrivers for the Qualcomm SM8550 SoC and LPASS pin controllers - New subdriver for the Qualcomm SA8775P SoC pin controller - New subdriver for the Qualcomm IPQ5332 SoC pin controller - New (trivial) support for Qualcomm PM8550 and PMR735D PMIC pin control - New subdriver for the Mediatek MT7981 SoC pin controller Improvements: - Several cleanups and refactorings to the Intel drivers - Add 4KOhm bias support to the Intel driver - Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver - Support general purpose clocks in the Qualcomm MSM8226 SoC - Several conversions to use the new I2C .probe_new() call - Massive clean-up of the Qualcomm Device Tree YAML schemas - Add VIN[45] pins, groups and functions to the Renesas r8a77950 SoC driver" * tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (118 commits) pinctrl: qcom: Add support for i2c specific pull feature pinctrl: starfive: Add StarFive JH7110 aon controller driver pinctrl: starfive: Add StarFive JH7110 sys controller driver dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl pinctrl: add mt7981 pinctrl driver dt-bindings: pinctrl: add bindings for MT7981 SoC dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated pinctrl: qcom: Introduce IPQ5332 TLMM driver dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS pinctrl: at91: use devm_kasprintf() to avoid potential leaks dt-bindings: pinctrl: qcom: correct gpio-ranges in examples dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example ...
2023-02-07pinctrl: intel: Restore the pins that used to be in Direct IRQ modeAndy Shevchenko1-3/+13
If the firmware mangled the register contents too much, check the saved value for the Direct IRQ mode. If it matches, we will restore the pin state. Reported-by: Jim Minter <jimminter@microsoft.com> Fixes: 6989ea4881c8 ("pinctrl: intel: Save and restore pins in "direct IRQ" mode") Tested-by: Jim Minter <jimminter@microsoft.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230206141558.20916-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-12-30pinctrl: intel: Get rid of unused members in struct intel_functionAndy Shevchenko1-9/+0
The driver has been converted to a generic data type and macro for the pin function definition, hence get rid of not used members in the struct intel_function. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-30pinctrl: moorefield: Convert to use new memeber in struct intel_functionAndy Shevchenko1-3/+3
Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-30pinctrl: merrifield: Convert to use new memeber in struct intel_functionAndy Shevchenko1-3/+3
Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-30pinctrl: lynxpoint: Convert to use new memeber in struct intel_functionAndy Shevchenko1-4/+4
Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-30pinctrl: cherryview: Convert to use new memeber in struct intel_functionAndy Shevchenko1-3/+3
Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-30pinctrl: baytrail: Convert to use new memeber in struct intel_functionAndy Shevchenko1-5/+5
Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-30pinctrl: intel: Make use of struct pinfunction and PINCTRL_PINFUNCTION()Andy Shevchenko2-8/+11
Since pin control provides a generic data type and a macro for the pin function definition, use them in the Intel driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Define maximum pad number in the groupAndy Shevchenko2-4/+6
Instead of using hard coded magic number here and there, define maximum pad number in the group in newly added INTEL_PINCTRL_MAX_GPP_SIZE. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Use same order of bit fields for PADCFG2Andy Shevchenko1-1/+1
PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same for PADCFG2 bit fields. No functional changes intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Add ~4k bias supportAndy Shevchenko1-0/+12
All versions that have 20k and 5k resistance, i.e. all that the driver supports, may support ~4k when the above mentioned are connected in parallel. Add such a support. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-12-28pinctrl: intel: Add definitions to all possible biasesAndy Shevchenko1-0/+3
Add definitions to all possible biases, i.e. add ~800 Ohms, ~952 Ohms, ~4 kOhms. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-01-21 14:15:06 +0300