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path: root/drivers/pinctrl/intel/pinctrl-intel.c
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2023-02-07pinctrl: intel: Restore the pins that used to be in Direct IRQ modeAndy Shevchenko1-3/+13
If the firmware mangled the register contents too much, check the saved value for the Direct IRQ mode. If it matches, we will restore the pin state. Reported-by: Jim Minter <jimminter@microsoft.com> Fixes: 6989ea4881c8 ("pinctrl: intel: Save and restore pins in "direct IRQ" mode") Tested-by: Jim Minter <jimminter@microsoft.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230206141558.20916-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-12-14Merge tag 'pinctrl-v6.2-1' of ↵Linus Torvalds1-14/+47
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "The two large chunks is the header clean-up from Andy and the Qualcomm DT bindings clean-up from Krzysztof. Each which could give rise to conflicts, but I haven't seen any. The YAML conversions happening around the device tree is the biggest item in the series and is the result of Rob Herrings ambition to autovalidate these trees against strict schemas and it is paying off in lots of bugs found and ever prettier device trees. Sooner or later the transition will be complete, Krzysztof is fixing up all of the Qualcomm stuff, which is pretty voluminous. Core changes: - minor but nice and important documentation clean-ups New drivers: - subdriver for the Qualcomm SDM670 SoC - subdriver for the Intel Moorefield SoC - trivial support for the NXP Freescale i.MXRT1170 SoC Other changes and improvements - major clean-up of the Qualcomm pin control device tree bindings by Krzysztof - major header clean-up by Andy - some immutable irqchip clean-up for the Actions Semiconductor and Nuvoton drivers - GPIO helpers for The Cypress cy8c95x0 driver - bias handling in the Mediatek MT7986 driver - remove the unused pins-are-numbered concept that never flew" * tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits) pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions() dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered pinctrl: stm32: Remove check for pins-are-numbered pinctrl: mediatek: common: Remove check for pins-are-numbered pinctrl: qcom: remove duplicate included header files pinctrl: sunxi: d1: Add CAN bus pinmuxes pinctrl: loongson2: Fix some const correctness pinctrl: pinconf-generic: add missing of_node_put() pinctrl: intel: Enumerate PWM device when community has a capability pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() pwm: lpss: Allow other drivers to enable PWM LPSS pwm: lpss: Include headers we are the direct user of pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS pwm: Add a stub for devm_pwmchip_add() pinctrl: k210: call of_node_put() pinctrl: starfive: Use existing variable gpio dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching pinconf-generic: fix style issues in pin_config_param doc pinctrl: pinctrl-loongson2: fix Kconfig dependency ...
2022-11-28pinctrl: intel: Save and restore pins in "direct IRQ" modeAndy Shevchenko1-1/+26
The firmware on some systems may configure GPIO pins to be an interrupt source in so called "direct IRQ" mode. In such cases the GPIO controller driver has no idea if those pins are being used or not. At the same time, there is a known bug in the firmwares that don't restore the pin settings correctly after suspend, i.e. by an unknown reason the Rx value becomes inverted. Hence, let's save and restore the pins that are configured as GPIOs in the input mode with GPIROUTIOXAPIC bit set. Cc: stable@vger.kernel.org Reported-and-tested-by: Dale Smith <dalepsmith@gmail.com> Reported-and-tested-by: John Harris <jmharris@gmail.com> BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=214749 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20221124222926.72326-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-28Merge tag 'intel-pinctrl-v6.2-2' of ↵Linus Walleij1-0/+29
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.2-2 * Enable PWM feature on Intel pin control IPs The following is an automated git shortlog grouped by driver: intel: - Enumerate PWM device when community has a capability pwm: - lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() - lpss: Allow other drivers to enable PWM LPSS - lpss: Include headers we are the direct user of - lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS - Add a stub for devm_pwmchip_add()
2022-11-22pinctrl: intel: Enumerate PWM device when community has a capabilityAndy Shevchenko1-0/+29
Some of the Communities may have PWM capability. In such cases, enumerate the PWM device via respective driver. A user is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2022-11-03pinctrl: intel: Use temporary variable for struct deviceAndy Shevchenko1-11/+12
Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-10-26pinctrl: intel: Use str_enable_disable() helperAndy Shevchenko1-1/+2
Use str_enable_disable() helper instead of open coding the same. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2022-10-24pinctrl: intel: Add missing header(s)Andy Shevchenko1-2/+4
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-08-10Merge tag 'pinctrl-v6.0-1' of ↵Linus Torvalds1-7/+7
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Outside the pinctrl driver and DT bindings we hit some Arm DT files, patched by the maintainers. Other than that it is business as usual. Core changes: - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver). New drivers: - Intel Meteor Lake support. - Reneasas RZ/V2M and r8a779g0 (R-Car V4H). - AXP209 variants AXP221, AXP223 and AXP809. - Qualcomm MSM8909, PM8226, PMP8074 and SM6375. - Allwinner D1. Improvements: - Proper pin multiplexing in the AMD driver. - Mediatek MT8192 can use generic drive strength and pin bias, then fixes on top plus some I2C pin group fixes. - Have the Allwinner Sunplus SP7021 use the generic DT schema and make interrupts optional. - Handle Qualcomm SC7280 ADSP. - Handle Qualcomm MSM8916 CAMSS GP clock muxing. - High impedance bias on ZynqMP. - Serialize StarFive access to MMIO. - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO" * tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits) dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM pinctrl: qcom: sm8250: Fix PDC map pinctrl: amd: Fix an unused variable dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp dt-bindings: pinctrl: mt8186: Add gpio-line-names property ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header pinctrl: amd: Use unicode for debugfs output pinctrl: amd: Fix newline declaration in debugfs output pinctrl: at91: Fix typo 'the the' in comment dt-bindings: pinctrl: st,stm32: Correct 'resets' property name pinctrl: mvebu: Missing a blank line after declarations. pinctrl: qcom: Add SM6375 TLMM driver dt-bindings: pinctrl: Add DT schema for SM6375 TLMM dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable" pinctrl: imx93: Add MODULE_DEVICE_TABLE() pinctrl: sunxi: Add driver for Allwinner D1 pinctrl: sunxi: Make some layout parameters dynamic pinctrl: sunxi: Refactor register/offset calculation ...
2022-07-14pinctrl: intel: Check against matching data instead of ACPI companionAndy Shevchenko1-8/+6
In some cases we may get a platform device that has ACPI companion which is different to the pin control described in the ACPI tables. This is primarily happens when device is instantiated by board file. In order to allow this device being enumerated, refactor intel_pinctrl_get_soc_data() to check the matching data instead of ACPI companion. Reported-by: Henning Schild <henning.schild@siemens.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Henning Schild <henning.schild@siemens.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org>
2022-06-20pinctrl: intel: Switch to to embedded struct pingroupAndy Shevchenko1-7/+7
Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-20pinctrl: intel: Fix kernel doc format, i.e. add return sectionsAndy Shevchenko1-0/+5
Kernel doc validator is not happy: pinctrl-intel.c:865: warning: No description found for return value of 'intel_gpio_to_pin' pinctrl-intel.c:904: warning: No description found for return value of 'intel_pin_to_gpio' 2 warnings Add return sections to the kernel documentation of the above mentioned functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-18pinctrl: intel: make irq_chip immutableAndy Shevchenko1-15/+25
Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-01-24pinctrl: intel: Fix a glitch when updating IRQ flags on a preconfigured lineAndy Shevchenko1-8/+2
The commit af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO") hadn't taken into account an update of the IRQ flags scenario. When updating the IRQ flags on the preconfigured line the ->irq_set_type() is called again. In such case the sequential Rx buffer configuration changes may trigger a falling or rising edge interrupt that may lead, on some platforms, to an undesired event. This may happen because each of intel_gpio_set_gpio_mode() and __intel_gpio_set_direction() updates the pad configuration with a different value of the GPIORXDIS bit. Notable, that the intel_gpio_set_gpio_mode() is called only for the pads that are configured as an input. Due to this fact, integrate the logic of __intel_gpio_set_direction() call into the intel_gpio_set_gpio_mode() so that the Rx buffer won't be disabled and immediately re-enabled. Fixes: af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO") Reported-by: Kane Chen <kane.chen@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Grace Kao <grace.kao@intel.com>
2022-01-24pinctrl: intel: fix unexpected interruptŁukasz Bartosik1-20/+34
ASUS Chromebook C223 with Celeron N3350 crashes sometimes during cold booot. Inspection of the kernel log showed that it gets into an inifite loop logging the following message: ->handle_irq(): 000000009cdb51e8, handle_bad_irq+0x0/0x251 ->irq_data.chip(): 000000005ec212a7, 0xffffa043009d8e7 ->action(): 00000 IRQ_NOPROBE set unexpected IRQ trap at vector 7c The issue happens during cold boot but only if cold boot happens at most several dozen seconds after Chromebook is powered off. For longer intervals between power off and power on (cold boot) the issue does not reproduce. The unexpected interrupt is sourced from INT3452 GPIO pin which is used for SD card detect. Investigation relevealed that when the interval between power off and power on (cold boot) is less than several dozen seconds then values of INT3452 GPIO interrupt enable and interrupt pending registers survive power off and power on sequence and interrupt for SD card detect pin is enabled and pending during probe of SD controller which causes the unexpected IRQ message. "Intel Pentium and Celeron Processor N- and J- Series" volume 3 doc mentions that GPIO interrupt enable and status registers default value is 0x0. The fix clears INT3452 GPIO interrupt enabled and interrupt pending registers in its probe function. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Signed-off-by: Łukasz Bartosik <lb@semihalf.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-04-30Merge tag 'pinctrl-v5.13-1' of ↵Linus Torvalds1-3/+2
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "There is a lot going on! Core changes: - A semantic change to handle pinmux and pinconf in explicit order while up until now we depended on the semantic order in the device tree. The device tree is a functional programming language and does not imply any order, so the right thing is for the pin control core to provide these semantics. - Add a new pinmux-select debugfs file which makes it possible to go in and select functions for a pin manually (iteratively, at the prompt) for debugging purposes. - Fixes to gpio regmap handling for a new pin control driver making use of regmap-gpio. - Use octal permissions on debugfs files. New drivers: - A massive rewrite of the former custom pin control driver for MIPS Broadcom devices to instead use the pin control subsystem. New pin control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368, BCM63268 and BCM6318 SoC variants are implemented. - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are supported. - Support for the Rockchip RK3568/RK3566 pin controller. - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000. - Support for Mediatek MTK8195. - Add a new Xilinx ZynqMP pin control driver. Driver improvements and non-urgent fixes: - Modularization and improvements of the Rockchip drivers. - Some new pins added to the description of new Renesas SoCs. - Clarifications of the GPIO base calculation in the Intel driver. - Fix the function names for the MPP54 and MPP55 pins in the Armada CP110 pin controller. - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350. - Support for ACPI probing of the Qualcomm SC8180x. - Fix interrupt clear status on rockchip - Fix some missing pins on the Ingenic JZ4770, some semantic fixes for the behaviour of the Ingenic pin controller. Add DMIC pins for JZ4780, X1000, X1500 and X1830. - A slew of janitorial like of_node_put() calls" * tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: Add Xilinx ZynqMP pinctrl driver support firmware: xilinx: Add pinctrl support pinctrl: rockchip: do coding style for mux route struct pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param pinctrl: Introduce MODE group in enum pin_config_param pinctrl: Keep enum pin_config_param ordered by name dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver pinctrl: core: Fix kernel doc string for pin_get_name() pinctrl: mediatek: use spin lock in mtk_rmw pinctrl: add drive for I2C related pins on MT8195 pinctrl: add pinctrl driver on mt8195 dt-bindings: pinctrl: mt8195: add pinctrl file and binding document pinctrl: Ingenic: Add pinctrl driver for X2000. pinctrl: Ingenic: Add pinctrl driver for JZ4775. pinctrl: Ingenic: Add pinctrl driver for JZ4755. pinctrl: Ingenic: Add pinctrl driver for JZ4750. pinctrl: Ingenic: Add pinctrl driver for JZ4730. dt-bindings: pinctrl: Add bindings for new Ingenic SoCs. pinctrl: Ingenic: Reformat the code. pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs. ...
2021-03-25pinctrl: intel: check REVID register value for device presenceRoger Pau Monne1-1/+6
Use the value read from the REVID register in order to check for the presence of the device. A read of all ones is treated as if the device is not present, and hence probing is ended. This fixes an issue when running as a Xen PVH dom0, where the ACPI DSDT table is provided unmodified to dom0 and hence contains the pinctrl devices, but the MMIO region(s) containing the device registers might not be mapped in the guest physical memory map if such region(s) are not exposed on a PCI device BAR or marked as reserved in the host memory map. Fixes: 91d898e51e60 ("pinctrl: intel: Convert capability list to features") Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-03-25pinctrl: intel: No need to disable IRQs in the handlerAndy Shevchenko1-3/+2
In IRQ handler interrupts are already disabled, hence no need to repeat it. Even in the threaded case, which is disabled here, it is not a problem because IRQ framework serializes descriptor handling. Remove disabling IRQ part in the handler. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-03-08pinctrl: intel: Show the GPIO base calculation explicitlyAndy Shevchenko1-0/+2
During the split of intel_pinctrl_add_padgroups(), the _by_size() variant missed the GPIO base calculations and hence made unable to retrieve proper GPIO number. Assign the gpio_base explicitly in _by_size() variant. While at it, differentiate NOMAP case with the rest in _by_gpps() variant. Fixes: 036e126c72eb ("pinctrl: intel: Split intel_pinctrl_add_padgroups() for better maintenance") Reported-and-tested-by: Maximilian Luz <luzmaximilian@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08pinctrl: intel: Convert capability list to featuresAndy Shevchenko1-3/+38
Communities can have features provided in the capability list. Traverse the list and convert to respective features. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08pinctrl: intel: Drop unnecessary check for predefined featuresAndy Shevchenko1-12/+6
None of the drivers is overriding features. Remove unnecessary check. While here, rename rev to value to make easier further development. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08pinctrl: intel: Split intel_pinctrl_add_padgroups() for better maintenanceAndy Shevchenko1-20/+40
Currently the intel_pinctrl_add_padgroups() is twisted a bit due to a different nature of the pin control hardware implementations. Thus, its maintenance is a bit hard. Besides that some pieces of code are run on all hardware and make this code slightly inefficient, and moreover, validation for one case is done in a wrong time in a flow which makes it even slower. Split intel_pinctrl_add_padgroups() to two functions, one per hardware implementation, for better maintenance and readability. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-12-09pinctrl: intel: Actually disable Tx and Rx buffers on GPIO requestAndy Shevchenko1-2/+2
Mistakenly the buffers (input and output) become enabled together for a short period of time during GPIO request. This is problematic, because instead of initial motive to disable them in the commit af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO"), the driven value on the pin, which might be used as an IRQ line, brings firmwares of some touch pads to an awkward state that needs a full power off to recover. Fix this, as stated in the culprit commit, by disabling the buffers. Fixes: af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO") BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=210497 Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Link: https://lore.kernel.org/r/20201208182403.40435-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-10-26pinctrl: intel: Set default bias in case no particular value givenAndy Shevchenko1-0/+8
When GPIO library asks pin control to set the bias, it doesn't pass any value of it and argument is considered boolean (and this is true for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual drivers must behave well, when they got the resistance value of 1 Ohm, i.e. transforming it to sane default. In case of Intel pin control hardware the 5 kOhm sounds plausible because on one hand it's a minimum of resistors present in all hardware generations and at the same time it's high enough to minimize leakage current (will be only 200 uA with the above choice). Fixes: e57725eabf87 ("pinctrl: intel: Add support for hardware debouncer") Reported-by: Jamie McClymont <jamie@kwiius.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-10-26pinctrl: intel: Fix 2 kOhm bias which is 833 OhmAndy Shevchenko1-10/+22
2 kOhm bias was never an option in Intel GPIO hardware, the available matrix is: 000 none 001 1 kOhm (if available) 010 5 kOhm 100 20 kOhm As easy to get the 3 resistors are gated separately and according to parallel circuits calculations we may get combinations of the above where the result is always strictly less than minimal resistance. Hence, additional values can be: 011 ~833.3 Ohm 101 ~952.4 Ohm 110 ~4 kOhm 111 ~800 Ohm That said, convert TERM definitions to be the bit masks to reflect the above. While at it, enable the same setting for pull down case. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Cc: Jamie McClymont <jamie@kwiius.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-08-18pinctrl: intel: Extract intel_pinctrl_get_soc_data() helper for wider useAndy Shevchenko1-6/+18
intel_pinctrl_get_soc_data() helper can be used in few driver instead of open-coded variants. Thus, extract it as a standalone API. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-22pinctrl: intel: Make use of for_each_requested_gpio_in_range()Andy Shevchenko1-15/+6
Make use of for_each_requested_gpio_in_range() instead of home grown analogue. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-22pinctrl: intel: Protect IO in few call backs by lockAndy Shevchenko1-1/+15
Protect IO in intel_gpio_get_direction(), intel_gpio_community_irq_handler(), intel_config_get_debounce() and intel_config_get_pull() by lock. Even for simple readl() we better serialize IO to avoid potential problems. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-22pinctrl: intel: Split intel_config_get() to three functionsAndy Shevchenko1-28/+61
Split intel_config_get() to three functions, i.e. intel_config_get() and two helpers intel_config_get_pull() and intel_config_get_debounce() to be symmetrical with intel_config_set*(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-22pinctrl: intel: Drop the only label in the code for consistencyAndy Shevchenko1-5/+3
Drop the only label in the code, i.e. in intel_config_set_debounce(), for consistency with the rest. In entire driver we use multipoint return. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-22pinctrl: intel: Get rid of redundant 'else' in intel_config_set_debounce()Andy Shevchenko1-5/+5
In a code like if (...) { ... goto label; } else { ... } the 'else' keyword is redundant. Get rid of it for better readability. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-22pinctrl: intel: Make use of IRQ_RETVAL()Andy Shevchenko1-10/+10
Instead of using bitwise operations against returned values, which is a bit fragile, convert IRQ handler to count amount of GPIO groups, where at least one interrupt happened, and convert it to returned value by IRQ_RETVAL() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-22pinctrl: intel: Reduce scope of the lockAndy Shevchenko1-7/+7
In some cases lock covers unneeded calls and operations. Reduce scope of the lock in such cases. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-22pinctrl: intel: Disable input and output buffer when switching to GPIOAndy Shevchenko1-1/+13
It's possible scenario that pin has been in different mode, while the respective GPIO register has a leftover output buffer enabled. In such case when we request GPIO it will switch to GPIO mode, and thus to output with unknown value, followed by switching to input mode. This can produce a glitch on the pin. Disable input and output buffer when switching to GPIO to avoid potential glitches. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-14pinctrl: intel: Introduce new flag to force GPIO base to be 0Andy Shevchenko1-0/+3
In some cases not the first group would like to have GPIO base to be 0. It's not possible right now due to 0 has special meaning already. Thus, introduce a new flag to allow drivers to force GPIO base to be 0 on a certain group. It's assumed that it can be only one group per device with such flag enabled. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-14pinctrl: intel: Introduce common flags for GPIO mapping schemeAndy Shevchenko1-6/+13
Few drivers are using the same flag to tell Intel pin control core how to interpret GPIO base. Provide a generic flags so all drivers can use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-01-09pinctrl: intel: Pass irqchip when adding gpiochipLinus Walleij1-13/+13
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-01-09pinctrl: intel: Add GPIO <-> pin mapping ranges via callbackLinus Walleij1-13/+22
When IRQ chip is instantiated via GPIO library flow, the few functions, in particular the ACPI event registration mechanism, on some of ACPI based platforms expect that the pin ranges are initialized to that point. Add GPIO <-> pin mapping ranges via callback in the GPIO library flow. Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-13pinctrl: intel: Share struct intel_pinctrl for wider useAndy Shevchenko1-34/+1
There are few drivers for Intel SoC GPIO which may utilize the same data structure to describe this IP. Share struct intel_pinctrl for wider user. Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-12-13pinctrl: intel: Use GPIO direction definitionsMatti Vaittinen1-1/+4
Use new GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT when returning GPIO direction to GPIO framework. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-11-07pinctrl: intel: Missed type change to unsigned intAndy Shevchenko1-2/+2
We converted 'unsigned' type to be 'unsigned int' in the driver, but there are couple of leftovers. So, finish the task now. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-10-30pinctrl: intel: Use helper to restore register values on ->resume()Andy Shevchenko1-13/+13
We can restore only values that had been changed and do not spam kernel log with unnecessary messages. Convert intel_gpio_update_pad_mode() to a helper function that will be used across few callers. Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Drop level from warning to debug in intel_restore_hostown()Andy Shevchenko1-1/+1
Since we didn't get any new reports from users about wrong settings of pad ownership, there is no point to spam kernel log with it. Thus, drop level from warning to debug. Also, modify format to be in align with the rest restore helpers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Introduce intel_restore_intmask() helperAndy Shevchenko1-5/+11
Refactor restoring GPI_IE registers by using an introduced helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Introduce intel_restore_hostown() helperAndy Shevchenko1-17/+21
Refactor restoring HOSTSW_OWN registers by using an introduced helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Introduce intel_restore_padcfg() helperAndy Shevchenko1-27/+24
Deduplicate restoring PADCFGx registers by using a common helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Avoid potential glitches if pin is in GPIO modeAndy Shevchenko1-1/+20
When consumer requests a pin, in order to be on the safest side, we switch it first to GPIO mode followed by immediate transition to the input state. Due to posted writes it's luckily to be a single I/O transaction. However, if firmware or boot loader already configures the pin to the GPIO mode, user expects no glitches for the requested pin. We may check if the pin is pre-configured and leave it as is till the actual consumer toggles its state to avoid glitches. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Depends-on: f5a26acf0162 ("pinctrl: intel: Initialize GPIO properly when used through irqchip") Cc: stable@vger.kernel.org Cc: fei.yang@intel.com Reported-by: Oliver Barta <oliver.barta@aptiv.com> Reported-by: Malin Jonsson <malin.jonsson@ericsson.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-01pinctrl: intel: Allocate IRQ chip dynamicAndy Shevchenko1-13/+14
Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. Fixes: ee1a6ca43dba ("pinctrl: intel: Add Intel Broxton pin controller support") Depends-on: 5ff56b015e85 ("pinctrl: intel: Disable GPIO pin interrupts in suspend") Reported-by: Federico Ricchiuto <fed.ricchiuto@gmail.com> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-09-09pinctrl: intel: mark intel_pin_to_gpio __maybe_unusedArnd Bergmann1-1/+1
The intel_pin_to_gpio() function is only called by the PM support functions and causes a warning when those are disabled: drivers/pinctrl/intel/pinctrl-intel.c:841:12: error: unused function 'intel_pin_to_gpio' [-Werror,-Wunused-function] Mark it __maybe_unused to suppress the warning. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Chris Chiu <chiu@endlessm.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-19pinctrl: intel: remap the pin number to gpio offset for irq enabled pinChris Chiu1-1/+24
On Asus X571GT, GPIO 297 is configured as an interrupt and serves for the touchpad. The touchpad will report input events much less than expected after S3 suspend/resume, which results in extremely slow cursor movement. However, the number of interrupts observed from /proc/interrupts increases much more than expected even no touching touchpad. This is due to the value of PADCFG0 of PIN 225 for the interrupt has been changed from 0x80800102 to 0x80100102. The GPIROUTIOXAPIC is toggled on which results in the spurious interrupts. The PADCFG0 of PIN 225 is expected to be saved during suspend, but the 297 is saved instead because the gpiochip_line_is_irq() expect the GPIO offset but what's really passed to it is PIN number. In this case, the /sys/kernel/debug/pinctrl/INT3450:00/gpio-ranges shows 288: INT3450:00 GPIOS [436 - 459] PINS [216 - 239] So gpiochip_line_is_irq() returns true for GPIO offset 297, the suspend routine spuriously saves the content for PIN 297 which we expect to save for PIN 225. This commit maps the PIN number to GPIO offset first in the intel_pinctrl_should_save() to make sure the values for the specific PINs can be correctly saved and then restored. Fixes: c538b9436751 ("pinctrl: intel: Only restore pins that are used by the driver") Signed-off-by: Chris Chiu <chiu@endlessm.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-03 20:47:09 +0300