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2024-08-05phy: xilinx: phy-zynqmp: Fix SGMII linkup failure on resumePiyush Mehta1-0/+56
On a few Kria KR260 Robotics Starter Kit the PS-GEM SGMII linkup is not happening after the resume. This is because serdes registers are reset when FPD is off (in suspend state) and needs to be reprogrammed in the resume path with the same default initialization as done in the first stage bootloader psu_init routine. To address the failure introduce a set of serdes registers to be saved in the suspend path and then restore it on resume. Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver") Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1722837547-2578381-1-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Add debugfs supportSean Anderson1-0/+40
Add support for printing some basic status information to debugfs. This is helpful when debugging phy consumers to make sure they are configuring the phy appropriately. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-6-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Take the phy mutex in xlateSean Anderson1-0/+1
Take the phy mutex in xlate to protect against concurrent modification/access to gtr_phy. This does not typically cause any issues, since in most systems the phys are only xlated once and thereafter accessed with the phy API (which takes the locks). However, we are about to allow userspace to access phys for debugging, so it's important to avoid any data races. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-5-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Only wait for PLL lock "primary" instancesSean Anderson1-9/+21
For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Store instance instead of typeSean Anderson1-84/+31
The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-3-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Enable reference clock correctlySean Anderson1-6/+8
Lanes can use other lanes' reference clocks, as determined by refclk. Use refclk to determine the clock to enable/disable instead of always using the lane's own reference clock. This ensures the clock selected in xpsgtr_configure_pll is the one enabled. For the other half of the equation, always program REF_CLK_SEL even when we are selecting the lane's own clock. This ensures that Linux's idea of the reference clock matches the hardware. We use the "local" clock mux for this instead of going through the ref clock network. Fixes: 25d700833513 ("phy: xilinx: phy-zynqmp: dynamic clock support for power-save") Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-05phy: xilinx: Convert to platform remove callback returning voidUwe Kleine-König1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/57a3338a1cec683ac84d48e00dbf197e15ee5481.1709886922.git.u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-02-23phy: constify of_phandle_args in xlateKrzysztof Kozlowski1-1/+1
The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> #Broadcom Link: https://lore.kernel.org/r/20240217093937.58234-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: zynqmp: Allow variation in refclk rateSean Anderson1-1/+4
Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: xilinx: phy-zynqmp: dynamic clock support for power-savePiyush Mehta1-46/+15
Enabling clock for all the lanes consumes power even PHY is active or inactive. To resolve this, enable/disable clocks in phy_init/phy_exit. By default clock is disabled for all the lanes. Whenever phy_init called from USB, SATA, or display driver, etc. It enabled the required clock for requested lane. On phy_exit cycle, it disabled clock for the active PHYs. During the suspend/resume cycle, each USB/ SATA/ display driver called phy_exit/phy_init individually. It disabled clock on exit, and enabled on initialization for the active PHYs. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Link: https://lore.kernel.org/r/20230613140250.3018947-3-piyush.mehta@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: xilinx: add runtime PM supportPiyush Mehta1-7/+28
Added Runtime power management support to the xilinx phy driver and using DEFINE_RUNTIME_DEV_PM_OPS new macros allows the compiler to remove the unused dev_pm_ops structure and related functions if !CONFIG_PM without the need to mark the functions __maybe_unused. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Link: https://lore.kernel.org/r/20230613140250.3018947-2-piyush.mehta@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-31phy: xilinx: phy-zynqmp: mention SGMII as supported protocolRadhey Shyam Pandey1-3/+2
SGMII is validated on kria KR260 robotics starter kit. So modify the comment description to include it in supported controllers list. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1679940407-13131-1-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: xilinx: zynqmp: Fix bus width setting for SGMIIRobert Hancock1-5/+6
TX_PROT_BUS_WIDTH and RX_PROT_BUS_WIDTH are single registers with separate bit fields for each lane. The code in xpsgtr_phy_init_sgmii was not preserving the existing register value for other lanes, so enabling the PHY in SGMII mode on one lane zeroed out the settings for all other lanes, causing other PS-GTR peripherals such as USB3 to malfunction. Use xpsgtr_clr_set to only manipulate the desired bits in the register. Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20220126001600.1592218-1-robert.hancock@calian.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-08-18phy: xilinx: zynqmp: skip PHY initialization and PLL lock for USBPiyush Mehta1-0/+3
PHY initialization for USB is required on linux boot or when gt lane is changed from the current one and it is applicable on PLL lock too. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Link: https://lore.kernel.org/r/20210818084311.2643986-1-piyush.mehta@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: zynqmp: Handle the clock enable/disable properlyManish Narani1-7/+51
The current driver is not handling the clock enable/disable operations properly. The clocks need to be handled correctly by enabling or disabling at appropriate places. This patch adds code to handle the same. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/1616588325-95602-1-git-send-email-manish.narani@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: zynqmp: Simplify code by using dev_err_probe()Michal Simek1-7/+4
Use already prepared dev_err_probe() introduced by commit a787e5400a1c ("driver core: add device probe log helper"). It simplifies EPROBE_DEFER handling. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/0df30548f721b10475a6cc5659beda102fec3c87.1612444300.git.michal.simek@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-01phy: zynqmp: Fix unused-function compiler warningTobias Klauser1-4/+2
Mark xpsgtr_suspend and xpsgtr_resume as __maybe_unused to fix the following compiler warning when building with !CONFIG_PM_SLEEP: drivers/phy/xilinx/phy-zynqmp.c:830:12: warning: ‘xpsgtr_resume’ defined but not used [-Wunused-function] 830 | static int xpsgtr_resume(struct device *dev) | ^~~~~~~~~~~~~ drivers/phy/xilinx/phy-zynqmp.c:819:12: warning: ‘xpsgtr_suspend’ defined but not used [-Wunused-function] 819 | static int xpsgtr_suspend(struct device *dev) | ^~~~~~~~~~~~~~ Also drop the existing #ifdef CONFIG_PM so the functions are always compile-checked regardless of CONFIG_PM and/or CONFIG_PM_SLEEP being set. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Link: https://lore.kernel.org/r/20200701141017.26931-1-tklauser@distanz.ch Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit TransceiverAnurag Kumar Vulisha3-0/+1011
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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