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2020-03-10PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe stringsBjorn Helgaas1-2/+2
Previously some PCI speed strings came from pci_speed_string(), some came from the PCIe-specific PCIE_SPEED2STR(), and some came from a PCIe-specific switch statement. These methods were inconsistent: pci_speed_string() PCIE_SPEED2STR() switch ------------------ ---------------- ------ 33 MHz PCI ... 2.5 GT/s PCIe 2.5 GT/s 2.5 GT/s 5.0 GT/s PCIe 5 GT/s 5 GT/s 8.0 GT/s PCIe 8 GT/s 8 GT/s 16.0 GT/s PCIe 16 GT/s 16 GT/s 32.0 GT/s PCIe 32 GT/s 32 GT/s Standardize on pci_speed_string() as the single source of these strings. Note that this adds ".0" and "PCIe" to some messages, including sysfs "max_link_speed" files, a brcmstb "link up" message, and the link status dmesg logging, e.g., nvme 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:01.1 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link) I think it's better to standardize on a single version of the speed text. Previously we had strings like this: /sys/bus/pci/slots/0/cur_bus_speed: 8.0 GT/s PCIe /sys/bus/pci/slots/0/max_bus_speed: 8.0 GT/s PCIe /sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8 GT/s /sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8 GT/s This changes the latter two to match the slots files: /sys/devices/pci0000:00/0000:00:1c.0/current_link_speed: 8.0 GT/s PCIe /sys/devices/pci0000:00/0000:00:1c.0/max_link_speed: 8.0 GT/s PCIe Based-on-patch by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-02-04treewide: remove redundant IS_ERR() before error code checkMasahiro Yamada1-1/+1
'PTR_ERR(p) == -E*' is a stronger condition than IS_ERR(p). Hence, IS_ERR(p) is unneeded. The semantic patch that generates this commit is as follows: // <smpl> @@ expression ptr; constant error_code; @@ -IS_ERR(ptr) && (PTR_ERR(ptr) == - error_code) +PTR_ERR(ptr) == - error_code // </smpl> Link: http://lkml.kernel.org/r/20200106045833.1725-1-masahiroy@kernel.org Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Cc: Julia Lawall <julia.lawall@lip6.fr> Acked-by: Stephen Boyd <sboyd@kernel.org> [drivers/clk/clk.c] Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [GPIO] Acked-by: Wolfram Sang <wsa@the-dreams.de> [drivers/i2c] Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [acpi/scan.c] Acked-by: Rob Herring <robh@kernel.org> Cc: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-02-01Merge tag 'pci-v5.6-changes' of ↵Linus Torvalds16-195/+1837
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Resource management: - Improve resource assignment for hot-added nested bridges, e.g., Thunderbolt (Nicholas Johnson) Power management: - Optionally print config space of devices before suspend (Chen Yu) - Increase D3 delay for AMD Ryzen5/7 XHCI controllers (Daniel Drake) Virtualization: - Generalize DMA alias quirks (James Sewart) - Add DMA alias quirk for PLX PEX NTB (James Sewart) - Fix IOV memory leak (Navid Emamdoost) AER: - Log which device prevents error recovery (Yicong Yang) Peer-to-peer DMA: - Whitelist Intel SkyLake-E (Armen Baloyan) Broadcom iProc host bridge driver: - Apply PAXC quirk whether driver is built-in or module (Wei Liu) Broadcom STB host bridge driver: - Add Broadcom STB PCIe host controller driver (Jim Quinlan) Intel Gateway SoC host bridge driver: - Add driver for Intel Gateway SoC (Dilip Kota) Intel VMD host bridge driver: - Add support for DMA aliases on other buses (Jon Derrick) - Remove dma_map_ops overrides (Jon Derrick) - Remove now-unused X86_DEV_DMA_OPS (Christoph Hellwig) NVIDIA Tegra host bridge driver: - Fix Tegra30 afi_pex2_ctrl register offset (Marcel Ziswiler) Panasonic UniPhier host bridge driver: - Remove module code since driver can't be built as a module (Masahiro Yamada) Qualcomm host bridge driver: - Add support for SDM845 PCIe controller (Bjorn Andersson) TI Keystone host bridge driver: - Fix "num-viewport" DT property error handling (Kishon Vijay Abraham I) - Fix link training retries initiation (Yurii Monakov) - Fix outbound region mapping (Yurii Monakov) Misc: - Add Switchtec Gen4 support (Kelvin Cao) - Add Switchtec Intercomm Notify and Upstream Error Containment support (Logan Gunthorpe) - Use dma_set_mask_and_coherent() since Switchtec supports 64-bit addressing (Wesley Sheng)" * tag 'pci-v5.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (60 commits) PCI: Allow adjust_bridge_window() to shrink resource if necessary PCI: Set resource size directly in adjust_bridge_window() PCI: Rename extend_bridge_window() to adjust_bridge_window() PCI: Rename extend_bridge_window() parameter PCI: Consider alignment of hot-added bridges when assigning resources PCI: Remove local variable usage in pci_bus_distribute_available_resources() PCI: Pass size + alignment to pci_bus_distribute_available_resources() PCI: Rename variables PCI: vmd: Add two VMD Device IDs PCI: Remove unnecessary braces PCI: brcmstb: Add MSI support PCI: brcmstb: Add Broadcom STB PCIe host controller driver x86/PCI: Remove X86_DEV_DMA_OPS PCI: vmd: Remove dma_map_ops overrides iommu/vt-d: Remove VMD child device sanity check iommu/vt-d: Use pci_real_dma_dev() for mapping PCI: Introduce pci_real_dma_dev() x86/PCI: Expose VMD's pci_dev in struct pci_sysdata x86/PCI: Add to_pci_sysdata() helper PCI/AER: Initialize aer_fifo ...
2020-01-30Merge branch 'remotes/lorenzo/pci/uniphier'Bjorn Helgaas1-30/+1
- Remove unused modular code from uniphier, which cannot be built as a module (Masahiro Yamada) * remotes/lorenzo/pci/uniphier: PCI: uniphier: remove module code from built-in driver
2020-01-30Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-2/+2
- Fix checking of pm_runtime_get_sync() return value (David Engraf) - Fix AFI_PEX2_CTRL reg offset for Tegra30 (Marcel Ziswiler) * remotes/lorenzo/pci/tegra: PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30 PCI: tegra: Fix return value check of pm_runtime_get_sync()
2020-01-30Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas1-0/+150
- Add DT clock/reset info for SDM845 PCIe controller (Bjorn Andersson) - Add support for SDM845 PCIe controller to the qcom driver (Bjorn Andersson) * remotes/lorenzo/pci/qcom: PCI: qcom: Add support for SDM845 PCIe controller dt-bindings: PCI: qcom: Add support for SDM845 PCIe
2020-01-30Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas1-1/+1
- Fix "EXYNOS" typographical styling (Krzysztof Kozlowski) - Update MAINTAINERS with Andrew Murray's email address (Andrew Murray) * remotes/lorenzo/pci/misc: MAINTAINERS: Update my email address PCI: exynos: Rename Exynos to lowercase
2020-01-30Merge branch 'remotes/lorenzo/pci/keystone'Bjorn Helgaas1-3/+3
- Fix link training so we can do it more than once (Yurii Monakov) - Fix keystone outbound window mapping (Yurii Monakov) - Fix error handling when DT lacks "num-viewport" (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: PCI: keystone: Fix error handling when "num-viewport" DT property is not populated PCI: keystone: Fix outbound region mapping PCI: keystone: Fix link training retries initiation
2020-01-30Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas6-7/+626
- Add intel-gw driver for PCIe host controller on Intel Gateway SoC (Dilip Kota) - Use shared DesignWare helpers to configure Fast Training Sequence (FTS) in artpec6 (Dilip Kota) * remotes/lorenzo/pci/dwc: PCI: artpec6: Configure FTS with dwc helper function PCI: dwc: intel: PCIe RC controller driver dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
2020-01-30Merge branch 'remotes/lorenzo/pci/brcmstb'Bjorn Helgaas3-0/+1025
- Add brcmstb PCIe bindings for Raspberry Pi 4 (Jim Quinlan) - Add Broadcom STB PCIe host controller driver (Jim Quinlan) - Add MSI support for Broadcom STB PCIe host controller driver (Jim Quinlan) * remotes/lorenzo/pci/brcmstb: PCI: brcmstb: Add MSI support PCI: brcmstb: Add Broadcom STB PCIe host controller driver dt-bindings: PCI: Add bindings for brcmstb's PCIe device
2020-01-30Merge branch 'pci/host-vmd'Bjorn Helgaas2-152/+5
- Save VMD's pci_dev in x86 struct pci_sysdata (Jon Derrick) - Add pci_real_dma_dev() for DMA aliases not on the same bus as requester (Jon Derrick) - Add IOMMU mappings for pci_real_dma_dev() (Jon Derrick) - Remove IOMMU sanity checks for VMD devices (Jon Derrick) - Remove VMD dma_map_ops overrides (Jon Derrick) - Remove unused X86_DEV_DMA_OPS (Christoph Hellwig) - Add VMD device IDs that need bus restriction mode (Sushma Kalakota) * pci/host-vmd: PCI: vmd: Add two VMD Device IDs x86/PCI: Remove X86_DEV_DMA_OPS PCI: vmd: Remove dma_map_ops overrides iommu/vt-d: Remove VMD child device sanity check iommu/vt-d: Use pci_real_dma_dev() for mapping PCI: Introduce pci_real_dma_dev() x86/PCI: Expose VMD's pci_dev in struct pci_sysdata x86/PCI: Add to_pci_sysdata() helper
2020-01-30PCI: vmd: Add two VMD Device IDsSushma Kalakota1-0/+4
Add new VMD device IDs that require the bus restriction mode. Signed-off-by: Sushma Kalakota <sushmax.kalakota@intel.com> Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-01-28PCI: brcmstb: Add MSI supportJim Quinlan2-1/+262
This adds MSI support to the Broadcom STB PCIe host controller. The MSI controller is physically located within the PCIe block, however, there is no reason why the MSI controller could not be moved elsewhere in the future. MSIX is not supported by the HW. Since the internal Brcmstb MSI controller is intertwined with the PCIe controller, it is not its own platform device but rather part of the PCIe platform device. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-01-28PCI: brcmstb: Add Broadcom STB PCIe host controller driverJim Quinlan3-0/+764
This adds a basic driver for Broadcom's STB PCIe controller, for now aimed at Raspberry Pi 4's SoC, bcm2711. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> [lorenzo.pieralisi@arm.com: updated brcm_pcie_get_rc_bar2_size_and_offset()according to https://lore.kernel.org/linux-pci/be8ddb33a7360af1815cf686f77f3f0913d02be3.camel@suse.de] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
2020-01-24PCI: vmd: Remove dma_map_ops overridesJon Derrick2-151/+0
Devices on the VMD domain use the VMD endpoint's requester ID and have been relying on the VMD endpoint's DMA operations. The problem with this was that VMD domain devices would use the VMD endpoint's attributes when doing DMA and IOMMU mapping. We can be smarter about this by only using the VMD endpoint when mapping and providing the correct child device's attributes during DMA operations. Remove the dma_map_ops redirect. Link: https://lore.kernel.org/r/1579613871-301529-7-git-send-email-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-01-24x86/PCI: Expose VMD's pci_dev in struct pci_sysdataJon Derrick1-1/+1
Expose VMD's pci_dev pointer in struct pci_sysdata. This will be used indirectly by intel-iommu.c to find the correct domain. Link: https://lore.kernel.org/r/1579613871-301529-3-git-send-email-jonathan.derrick@intel.com [bhelgaas: commit log] Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Christoph Hellwig <hch@lst.de>
2020-01-21PCI: keystone: Fix error handling when "num-viewport" DT property is not ↵Kishon Vijay Abraham I1-1/+1
populated Fix error handling when "num-viewport" DT property is not populated. Fixes: 23284ad677a9 ("PCI: keystone: Add support for PCIe EP in AM654x Platforms") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org # v5.2+
2020-01-13PCI: uniphier: remove module code from built-in driverMasahiro Yamada1-30/+1
builtin_platform_driver() and MODULE_* are always odd combination. This file is not compiled as a module by anyone because CONFIG_PCIE_UNIPHIER is a bool option. Let's remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-01-13PCI: exynos: Rename Exynos to lowercaseKrzysztof Kozlowski1-1/+1
Fix up inconsistent usage of upper and lowercase letters in "Exynos" name. "EXYNOS" is not an abbreviation but a regular trademarked name. Therefore it should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-01-10PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30Marcel Ziswiler1-1/+1
Fix AFI_PEX2_CTRL reg offset for Tegra30 by moving it from the Tegra20 SoC struct where it erroneously got added. This fixes the AFI_PEX2_CTRL reg offset being uninitialised subsequently failing to bring up the third PCIe port. Fixes: adb2653b3d2e ("PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct") Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
2020-01-10PCI: tegra: Fix return value check of pm_runtime_get_sync()David Engraf1-1/+1
pm_runtime_get_sync() returns the device's usage counter. This might be >0 if the device is already powered up or CONFIG_PM is disabled. Abort probe function on real error only. Fixes: da76ba50963b ("PCI: tegra: Add power management support") Link: https://lore.kernel.org/r/20191216111825.28136-1-david.engraf@sysgo.com Signed-off-by: David Engraf <david.engraf@sysgo.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Andrew Murray <andrew.murray@arm.com> Cc: stable@vger.kernel.org # v4.17+
2020-01-10PCI: keystone: Fix outbound region mappingYurii Monakov1-1/+1
The Keystone outbound Address Translation Unit (ATU) maps PCI MMIO space in 8 MB windows. When programming the ATU windows, we previously incremented the starting address by 8, not 8 MB, so all the windows were mapped to the first 8 MB. Therefore, only 8 MB of MMIO space was accessible. Update the loop so it increments the starting address by 8 MB, not 8, so more MMIO space is accessible. Fixes: e75043ad9792 ("PCI: keystone: Cleanup outbound window configuration") Link: https://lore.kernel.org/r/20191004154811.GA31397@monakov-y.office.kontur-niirs.ru Signed-off-by: Yurii Monakov <monakov.y@gmail.com> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Cc: stable@vger.kernel.org # v4.20+
2020-01-10PCI: keystone: Fix link training retries initiationYurii Monakov1-1/+1
ks_pcie_stop_link() function does not clear LTSSM_EN_VAL bit so link training was not triggered more than once after startup. In configurations where link can be unstable during early boot, for example, under low temperature, it will never be established. Fixes: 0c4ffcfe1fbc ("PCI: keystone: Add TI Keystone PCIe driver") Signed-off-by: Yurii Monakov <monakov.y@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Andrew Murray <andrew.murray@arm.com> Cc: stable@vger.kernel.org
2020-01-10PCI: qcom: Add support for SDM845 PCIe controllerBjorn Andersson1-0/+150
The SDM845 has one Gen2 and one Gen3 controller, add support for these. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2020-01-09PCI: artpec6: Configure FTS with dwc helper functionDilip Kota1-7/+1
Use DesignWare helper functions to configure Fast Training Sequence. Drop the respective code in the driver. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-01-09PCI: dwc: intel: PCIe RC controller driverDilip Kota5-0/+625
Add support to PCIe RC controller on Intel Gateway SoCs. PCIe controller is based of Synopsys DesignWare PCIe core. Intel PCIe driver requires Upconfigure support, Fast Training Sequence and link speed configurations. So adding the respective helper functions in the PCIe DesignWare framework. It also programs hardware autonomous speed during speed configuration so defining it in pci_regs.h. Also, mark Intel PCIe driver depends on MSI IRQ Domain as Synopsys DesignWare framework depends on the PCI_MSI_IRQ_DOMAIN. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2020-01-06remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig2-2/+2
ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
2019-12-13PCI: iproc: Apply quirk_paxc_bridge() for module as well as built-inWei Liu1-0/+24
Previously quirk_paxc_bridge() was applied when the iproc driver was built-in, but not when it was compiled as a module. This happened because it was under #ifdef CONFIG_PCIE_IPROC_PLATFORM: PCIE_IPROC_PLATFORM=y causes CONFIG_PCIE_IPROC_PLATFORM to be defined, but PCIE_IPROC_PLATFORM=m causes CONFIG_PCIE_IPROC_PLATFORM_MODULE to be defined. Move quirk_paxc_bridge() to pcie-iproc.c and drop the #ifdef so the quirk is always applied, whether iproc is built-in or a module. [bhelgaas: commit log, move to pcie-iproc.c, not pcie-iproc-platform.c] Link: https://lore.kernel.org/r/20191211174511.89713-1-wei.liu@kernel.org Signed-off-by: Wei Liu <wei.liu@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-12-13PCI: rockchip: Fix IO outbound ATU register numberEnric Balletbo i Serra1-1/+3
Since 62240a88004b ("PCI: rockchip: Drop storing driver private outbound resource data), the offset calculation is wrong to access the register number to program the IO outbound ATU. Fix this by computing the ATU IO register number based on the number of MEM registers, not the size of the IO region. This causes 'synchronous external aborts' like the following: mwifiex_pcie 0000:01:00.0: enabling device (0000 -> 0002) mwifiex_pcie: PCI memory map Virt0: 00000000a573ad00 PCI memory map Virt2: 00000000783126c4 Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP Modules linked in: mwifiex_pcie(+) mwifiex uvcvideo cfg80211 atmel_mxt_ts videobuf2_vmalloc ... CPU: 2 PID: 269 Comm: systemd-udevd Not tainted 5.4.0+ #327 Hardware name: Google Kevin (DT) pstate: 60000005 (nZCv daif -PAN -UAO) pc : mwifiex_register_dev+0x264/0x3f8 [mwifiex_pcie] lr : mwifiex_register_dev+0x150/0x3f8 [mwifiex_pcie] sp : ffff800012073860 x29: ffff800012073860 x28: ffff8000100a2e28 x27: ffff8000118b6210 x26: ffff800008f57458 x25: ffff0000ecfda000 x24: 0000000000000001 x23: ffff0000e9905080 x22: ffff800008f5d000 x21: ffff0000eecea078 x20: ffff0000e9905080 x19: ffff0000eecea000 x18: 0000000000000001 x17: 0000000000000000 x16: 0000000000000000 x15: ffffffffffffffff x14: ffff8000118998c8 x13: ffff000000000000 x12: 0000000000000008 x11: 0101010101010101 x10: ffff7f7fffff7fff x9 : 0000000000000000 x8 : ffff0000e3c24240 x7 : 0000000000000000 x6 : ffff0000e3c24148 x5 : ffff0000e3c24148 x4 : ffff0000e7975ec8 x3 : 0000000000000001 x2 : 0000000000002b42 x1 : ffff800012c00008 x0 : ffff0000e9905080 Call trace: mwifiex_register_dev+0x264/0x3f8 [mwifiex_pcie] mwifiex_add_card+0x2f8/0x430 [mwifiex] mwifiex_pcie_probe+0x98/0x148 [mwifiex_pcie] pci_device_probe+0x110/0x1a8 ... Code: a8c67bfd d65f03c0 f942ac01 91002021 (b9400021) Suggested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Fixes: 62240a88004b ("PCI: rockchip: Drop storing driver private outbound resource data) Link: https://lore.kernel.org/r/20191211093450.7481-1-enric.balletbo@collabora.com Reported-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reported-by: Vicente Bergas <vicencb@gmail.com> Tested-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Andrew Murray <andrew.murray@arm.com>
2019-11-28Merge branch 'pci/trivial'Bjorn Helgaas2-4/+4
- Fix typos and comments (Bjorn Helgaas) - Fix Kconfig whitespace errors (Krzysztof Kozlowski) * pci/trivial: PCI: Fix indentation PCI: Fix typos PCI: Remove useless comments and tidy others PCI: Remove unnecessary includes # Conflicts: # drivers/pci/probe.c
2019-11-28Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas2-4/+5
- Fix iproc-msi and mvebu __iomem annotations (Ben Dooks) - Make mvebu_pci_bridge_emul_ops static (Ben Dooks) - Add Marek Vasut and Yoshihiro Shimoda as R-Car maintainers (Simon Horman) - Fix pcitest.c fd leak (Hewenliang) * remotes/lorenzo/pci/misc: tools: PCI: Fix fd leakage MAINTAINERS: Add Marek and Shimoda-san as R-Car PCIE co-maintainers PCI: mvebu: mvebu_pcie_map_registers __iomem fix PCI: mvebu: Make mvebu_pci_bridge_emul_ops static PCI: iproc-msi: Fix __iomem annotation in decode_msi_hwirq()
2019-11-28Merge branch 'remotes/lorenzo/pci/mmio-dma-ranges'Bjorn Helgaas19-577/+198
- Consolidate DT "dma-ranges" parsing and convert all host drivers to use shared parsing (Rob Herring) * remotes/lorenzo/pci/mmio-dma-ranges: PCI: Make devm_of_pci_get_host_bridge_resources() static PCI: rcar: Use inbound resources for setup PCI: iproc: Use inbound resources for setup PCI: xgene: Use inbound resources for setup PCI: v3-semi: Use inbound resources for setup PCI: ftpci100: Use inbound resources for setup PCI: of: Add inbound resource parsing to helpers PCI: versatile: Enable COMPILE_TEST PCI: versatile: Remove usage of PHYS_OFFSET PCI: versatile: Use pci_parse_request_of_pci_ranges() PCI: xilinx-nwl: Use pci_parse_request_of_pci_ranges() PCI: xilinx: Use pci_parse_request_of_pci_ranges() PCI: xgene: Use pci_parse_request_of_pci_ranges() PCI: v3-semi: Use pci_parse_request_of_pci_ranges() PCI: rockchip: Drop storing driver private outbound resource data PCI: rockchip: Use pci_parse_request_of_pci_ranges() PCI: mobiveil: Use pci_parse_request_of_pci_ranges() PCI: mediatek: Use pci_parse_request_of_pci_ranges() PCI: iproc: Use pci_parse_request_of_pci_ranges() PCI: faraday: Use pci_parse_request_of_pci_ranges() PCI: dwc: Use pci_parse_request_of_pci_ranges() PCI: altera: Use pci_parse_request_of_pci_ranges() PCI: aardvark: Use pci_parse_request_of_pci_ranges() PCI: Export pci_parse_request_of_pci_ranges() resource: Add a resource_list_first_type helper # Conflicts: # drivers/pci/controller/pcie-rcar.c
2019-11-28Merge branch 'remotes/lorenzo/pci/vmd'Bjorn Helgaas1-8/+24
- Add VMD bus 224-255 restriction decode (Jon Derrick) - Add VMD 8086:9A0B device ID (Jon Derrick) - Remove Keith from VMD maintainer list (Keith Busch) * remotes/lorenzo/pci/vmd: MAINTAINERS: Remove Keith from VMD maintainer PCI: vmd: Add device id for VMD device 8086:9A0B PCI: vmd: Add bus 224-255 restriction decode
2019-11-28Merge branch 'remotes/lorenzo/pci/uniphier'Bjorn Helgaas1-0/+10
- Set uniphier to host (RC) mode always (Kunihiko Hayashi) * remotes/lorenzo/pci/uniphier: PCI: uniphier: Set mode register to host mode
2019-11-28Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-4/+2
- Fix Tegra CLKREQ dependency programming (Vidya Sagar) * remotes/lorenzo/pci/tegra: PCI: tegra: Fix CLKREQ dependency programming
2019-11-28Merge branch 'remotes/lorenzo/pci/rockchip'Bjorn Helgaas1-44/+25
- Make rockchip 0V9 and 1V8 power regulators non-optional (Robin Murphy) * remotes/lorenzo/pci/rockchip: PCI: rockchip: Make some regulators non-optional
2019-11-28Merge branch 'remotes/lorenzo/pci/rcar'Bjorn Helgaas1-23/+27
- Clear bit 0 of MACCTLR before PCIETCTLR.CFINIT per manual (Yoshihiro Shimoda) - Remove unnecessary header include from rcar (Andrew Murray) - Tighten register index checking for rcar inbound range programming (Marek Vasut) - Fix rcar inbound range alignment calculation to improve packing of multiple entries (Marek Vasut) - Update rcar MACCTLR setting to match documentation (Yoshihiro Shimoda) * remotes/lorenzo/pci/rcar: PCI: rcar: Fix missing MACCTLR register setting in initialization sequence PCI: rcar: Recalculate inbound range alignment for each controller entry PCI: rcar: Move the inbound index check PCI: rcar: Remove unnecessary header include (../pci.h)
2019-11-28Merge branch 'remotes/lorenzo/pci/mobiveil'Bjorn Helgaas1-57/+62
- Change mobiveil csr_read()/write() function names that conflict with riscv arch functions (Kefeng Wang) * remotes/lorenzo/pci/mobiveil: PCI: mobiveil: Fix csr_read()/write() build issue
2019-11-28Merge branch 'remotes/lorenzo/pci/meson'Bjorn Helgaas1-27/+109
- Fix meson PERST# GPIO polarity problem (Remi Pommarel) - Add DT bindings for Amlogic Meson G12A (Neil Armstrong) - Fix meson clock names to match DT bindings (Neil Armstrong) - Add meson support for Amlogic G12A SoC with separate shared PHY (Neil Armstrong) - Add meson extended PCIe PHY functions for Amlogic G12A USB3+PCIe combo PHY (Neil Armstrong) - Add arm64 DT for Amlogic G12A PCIe controller node (Neil Armstrong) - Add commented-out description of VIM3 USB3/PCIe mux in arm64 DT (Neil Armstrong) * remotes/lorenzo/pci/meson: arm64: dts: khadas-vim3: add commented support for PCIe arm64: dts: meson-g12a: Add PCIe node phy: meson-g12a-usb3-pcie: Add support for PCIe mode PCI: amlogic: meson: Add support for G12A PCI: amlogic: Fix probed clock names dt-bindings: pci: amlogic, meson-pcie: Add G12A bindings PCI: amlogic: Fix reset assertion via gpio descriptor
2019-11-28Merge branch 'remotes/lorenzo/pci/layerscape'Bjorn Helgaas1-0/+1
- Add layerscape LS1028a support (Xiaowei Bao) * remotes/lorenzo/pci/layerscape: PCI: layerscape: Add LS1028a support dt-bindings: pci: layerscape-pci: add compatible strings "fsl, ls1028a-pcie"
2019-11-28Merge branch 'remotes/lorenzo/pci/iproc'Bjorn Helgaas1-0/+28
- Invalidate iProc PAXB address mapping before programming it (Abhishek Shah) * remotes/lorenzo/pci/iproc: PCI: iproc: Invalidate PAXB address mapping before programming it
2019-11-28Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas1-29/+179
- Add hibernation support for Hyper-V virtual PCI devices (Dexuan Cui) - Track Hyper-V pci_protocol_version per-hbus, not globally (Dexuan Cui) - Avoid kmemleak false positive on hv hbus buffer (Dexuan Cui) * remotes/lorenzo/pci/hv: PCI: hv: Avoid a kmemleak false positive caused by the hbus buffer PCI: hv: Change pci_protocol_version to per-hbus PCI: hv: Add hibernation support PCI: hv: Reorganize the code in preparation of hibernation
2019-11-28Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas1-5/+6
- Fix dwc find_next_bit() usage (Niklas Cassel) * remotes/lorenzo/pci/dwc: PCI: dwc: Fix find_next_bit() usage
2019-11-28Merge branch 'remotes/lorenzo/pci/cadence'Bjorn Helgaas9-210/+315
- Refactor Cadence PCIe host controller to use as a library for both host and endpoint (Tom Joseph) * remotes/lorenzo/pci/cadence: PCI: cadence: Move all files to per-device cadence directory PCI: cadence: Refactor driver to use as a core library
2019-11-28Merge branch 'remotes/lorenzo/pci/aardvark'Bjorn Helgaas1-15/+57
- Use LTSSM state to build link training flag since Aardvark doesn't implement the Link Training bit (Remi Pommarel) - Delay before training Aardvark link in case PERST# was asserted before the driver probe (Remi Pommarel) - Fix Aardvark issues with Root Control reads and writes (Remi Pommarel) - Don't rely on jiffies in Aardvark config access path since interrupts may be disabled (Remi Pommarel) - Fix Aardvark big-endian support (Grzegorz Jaszczyk) - Fix bridge emulation big-endian support (Grzegorz Jaszczyk) * remotes/lorenzo/pci/aardvark: PCI: pci-bridge-emul: Fix big-endian support PCI: aardvark: Fix big endian support PCI: aardvark: Don't rely on jiffies while holding spinlock PCI: aardvark: Fix PCI_EXP_RTCTL register configuration PCI: aardvark: Wait for endpoint to be ready before training link PCI: aardvark: Use LTSSM state to build link training flag
2019-11-28Merge branch 'pci/resource'Bjorn Helgaas6-10/+10
- Protect pci_reassign_bridge_resources() against concurrent addition/removal (Benjamin Herrenschmidt) - Fix bridge dma_ranges resource list cleanup (Rob Herring) - Add PCI_STD_NUM_BARS for the number of standard BARs (Denis Efremov) - Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters to control the MMIO and prefetchable MMIO window sizes of hotplug bridges independently (Nicholas Johnson) - Fix MMIO/MMIO_PREF window assignment that assigned more space than desired (Nicholas Johnson) - Only enforce bus numbers from bridge EA if the bridge has EA devices downstream (Subbaraya Sundeep) * pci/resource: PCI: Do not use bus number zero from EA capability PCI: Avoid double hpmemsize MMIO window assignment PCI: Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters PCI: Add PCI_STD_NUM_BARS for the number of standard BARs PCI: Fix missing bridge dma_ranges resource list cleanup PCI: Protect pci_reassign_bridge_resources() against concurrent addition/removal
2019-11-26PCI: hv: Avoid a kmemleak false positive caused by the hbus bufferDexuan Cui1-3/+21
With the recent 59bb47985c1d ("mm, sl[aou]b: guarantee natural alignment for kmalloc(power-of-two)"), kzalloc() is able to allocate a 4KB buffer that is guaranteed to be 4KB-aligned. Here the size and alignment of hbus is important because hbus's field retarget_msi_interrupt_params must not cross a 4KB page boundary. Here we prefer kzalloc to get_zeroed_page(), because a buffer allocated by the latter is not tracked and scanned by kmemleak, and hence kmemleak reports the pointer contained in the hbus buffer (i.e. the hpdev struct, which is created in new_pcichild_device() and is tracked by hbus->children) as memory leak (false positive). If the kernel doesn't have 59bb47985c1d, get_zeroed_page() *must* be used to allocate the hbus buffer and we can avoid the kmemleak false positive by using kmemleak_alloc() and kmemleak_free() to ask kmemleak to track and scan the hbus buffer. Reported-by: Lili Deng <v-lide@microsoft.com> Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
2019-11-26PCI: hv: Change pci_protocol_version to per-hbusDexuan Cui1-12/+10
A VM can have multiple Hyper-V hbus. It's incorrect to set the global variable 'pci_protocol_version' when *every* hbus is initialized in hv_pci_protocol_negotiation(). This is not an issue in practice since every hbus should have the same value of hbus->protocol_version, but we should make the variable per-hbus, so in case we have busses with different protocol versions, the driver can still work correctly. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
2019-11-26PCI: hv: Add hibernation supportDexuan Cui1-2/+123
Add suspend() and resume() functions so that Hyper-V virtual PCI devices are handled properly when the VM hibernates and resumes from hibernation. Note that the suspend() function must make sure there are no pending work items before calling vmbus_close(), since it runs in a process context as a callback in dpm_suspend(). When it starts to run, the channel callback hv_pci_onchannelcallback(), which runs in a tasklet context, can be still running concurrently and scheduling new work items onto hbus->wq in hv_pci_devices_present() and hv_pci_eject_device(), and the work item handlers can access the vmbus channel, which can be being closed by hv_pci_suspend(), e.g. the work item handler pci_devices_present_work() -> new_pcichild_device() writes to the vmbus channel. To eliminate the race, hv_pci_suspend() disables the channel callback tasklet, sets hbus->state to hv_pcibus_removing, and re-enables the tasklet. This way, when hv_pci_suspend() proceeds, it knows that no new work item can be scheduled, and then it flushes hbus->wq and safely closes the vmbus channel. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
2019-11-26PCI: hv: Reorganize the code in preparation of hibernationDexuan Cui1-15/+28
There is no functional change. This is just preparatory for a later patch which adds the hibernation support for the pci-hyperv driver. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-08 12:24:56 +0300