summaryrefslogtreecommitdiff
path: root/drivers/pci/controller/dwc/pcie-tegra194.c
AgeCommit message (Collapse)AuthorFilesLines
2021-09-22PCI: tegra194: Fix MSI-X programmingOm Prakash Singh1-1/+1
[ Upstream commit 43537cf7e351264a1f05ed42ad402942bfc9140e ] Lower order MSI-X address is programmed in MSIX_ADDR_MATCH_HIGH_OFF DBI register instead of higher order address. This patch fixes this programming mistake. Link: https://lore.kernel.org/r/20210623100525.19944-3-omp@nvidia.com Signed-off-by: Om Prakash Singh <omp@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-09-22PCI: tegra194: Fix handling BME_CHGED eventOm Prakash Singh1-15/+15
[ Upstream commit ceb1412c1c8ca5b28c4252bdb15f2f1f17b4a1b0 ] In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches "if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct. Link: https://lore.kernel.org/r/20210623100525.19944-2-omp@nvidia.com Signed-off-by: Om Prakash Singh <omp@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-20PCI: tegra194: Fix tegra_pcie_ep_raise_msi_irq() ill-defined shiftJon Hunter1-1/+1
[ Upstream commit f67092eff2bd40650aad54a1a1910160f41d864a ] tegra_pcie_ep_raise_msi_irq() shifted a signed 32-bit value left by 31 bits. The behavior of this is implementation-defined. Replace the shift by BIT(), which is well-defined. Found by cppcheck: $ cppcheck --enable=all drivers/pci/controller/dwc/pcie-tegra194.c Checking drivers/pci/controller/dwc/pcie-tegra194.c ... drivers/pci/controller/dwc/pcie-tegra194.c:1829:23: portability: Shifting signed 32-bit value by 31 bits is implementation-defined behaviour. See condition at line 1826. [shiftTooManyBitsSigned] appl_writel(pcie, (1 << irq), APPL_MSI_CTRL_1); ^ [bhelgaas: commit log] Link: https://lore.kernel.org/r/20210618160219.303092-1-jonathanh@nvidia.com Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-05-22PCI: tegra: Fix runtime PM imbalance in pex_ep_event_pex_rst_deassert()Dinghao Liu1-1/+1
[ Upstream commit 5859c926d1f052ee61b5815b14658875c14f6243 ] pm_runtime_get_sync() will increase the runtime PM counter even it returns an error. Thus a pairing decrement is needed to prevent refcount leak. Fix this by replacing this API with pm_runtime_resume_and_get(), which will not change the runtime PM counter on error. Link: https://lore.kernel.org/r/20210408072700.15791-1-dinghao.liu@zju.edu.cn Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-21Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-15/+5
- Drop return value checking for debugfs_create() calls (Greg Kroah-Hartman) - Convert debugfs "ports" file to use DEFINE_SEQ_ATTRIBUTE() (Liu Shixin) * remotes/lorenzo/pci/tegra: PCI: tegra: Convert to use DEFINE_SEQ_ATTRIBUTE macro PCI: tegra: No need to check return value of debugfs_create() functions
2020-09-10PCI: dwc: Use DBI accessorsRob Herring1-6/+4
Convert the remaining cases of register accesses using dbi_base rather than dw_pcie_(read|write)[bwl]_dbi accessors. Link: https://lore.kernel.org/r/20200821035420.380495-41-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org
2020-09-10PCI: dwc: Move N_FTS setup to common setupRob Herring1-22/+3
The Designware controller has common registers to set number of fast training sequence ordered sets. The Artpec6, Intel, and Tegra driver initialize these register fields. Let's move the initialization to the common setup code and drivers just have to provide the value. There's a slight change in that the common clock mode N_FTS field is now initialized. Previously only the Intel driver set this. It's not clear from the code if common clock mode is used in the Artpec6 or Tegra driver. It depends on the DWC configuration. Given the field is not initialized while the others are, it seems unlikely common clock mode is used. Link: https://lore.kernel.org/r/20200821035420.380495-40-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org
2020-09-10PCI: dwc: Centralize link gen settingRob Herring1-23/+0
keystone would force gen2 if no DT property. Now it relies on the PCI_EXP_LNKCAP value. Link: https://lore.kernel.org/r/20200821035420.380495-35-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-tegra@vger.kernel.org
2020-09-08PCI: dwc/tegra: Use common Designware port logic register definitionsRob Herring1-34/+22
The Tegra driver has its own defines for common Designware Port Logic registers. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/20200821035420.380495-32-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org
2020-09-08PCI: dwc: Remove root_bus pointerRob Herring1-2/+2
The pci_host_bridge struct already has a pointer to its pci_bus, so let's convert the one user to use the bridge struct and remove the private 'root_bus' pointer. Link: https://lore.kernel.org/r/20200821035420.380495-18-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org
2020-09-08PCI: dwc: tegra: Use pci_ops for root config space accessorsRob Herring1-14/+16
Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Tegra driver to use the standard pci_ops for root bus config accesses. Link: https://lore.kernel.org/r/20200821035420.380495-8-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org
2020-09-07PCI: tegra: No need to check return value of debugfs_create() functionsGreg Kroah-Hartman1-15/+5
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Link: https://lore.kernel.org/r/20200818133739.463193-1-gregkh@linuxfoundation.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Rob Herring <robh@kernel.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Vidya Sagar <vidyas@nvidia.com> Cc: Andrew Murray <amurray@thegoodpenguin.co.uk> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-pci@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-kernel@vger.kernel.org
2020-08-03PCI: Remove dev_err() when handing an error from platform_get_irq()Krzysztof Wilczyński1-3/+1
There is no need to call the dev_err() function directly to print a custom message when handling an error from either the platform_get_irq() or platform_get_irq_byname() functions as both are going to display an appropriate error message in case of a failure. This change is as per suggestions from Coccinelle, e.g., drivers/pci/controller/dwc/pcie-armada8k.c:252:2-9: line 252 is redundant because platform_get_irq() already prints an error [bhelgaas: squashed into one commit] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20200802142601.1635926-2-kw@linux.com Link: https://lore.kernel.org/r/20200802142601.1635926-3-kw@linux.com Link: https://lore.kernel.org/r/20200802142601.1635926-4-kw@linux.com Link: https://lore.kernel.org/r/20200802142601.1635926-5-kw@linux.com Link: https://lore.kernel.org/r/20200802142601.1635926-6-kw@linux.com Link: https://lore.kernel.org/r/20200802142601.1635926-7-kw@linux.com Link: https://lore.kernel.org/r/20200802142601.1635926-8-kw@linux.com Link: https://lore.kernel.org/r/20200802142601.1635926-9-kw@linux.com Link: https://lore.kernel.org/r/20200802142601.1635926-10-kw@linux.com Link: https://lore.kernel.org/r/20200803071040.1663662-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> # altera Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # dwc
2020-06-04Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-3/+2
- Fix error message for failure to get reset GPIO from DT (Pali Rohár) - Fix runtime PM imbalance on error path (both tegra and tegra194) (Dinghao Liu) * remotes/lorenzo/pci/tegra: PCI: tegra: Fix runtime PM imbalance on error PCI: tegra194: Fix runtime PM imbalance on error PCI: tegra: Fix reporting GPIO error value
2020-05-29PCI: tegra194: Fix runtime PM imbalance on errorDinghao Liu1-3/+2
pm_runtime_get_sync() increments the runtime PM usage counter even when it returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Link: https://lore.kernel.org/r/20200521031355.7022-1-dinghao.liu@zju.edu.cn Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Vidya Sagar <vidyas@nvidia.com>
2020-05-12PCI: Check for platform_get_irq() failure consistentlyAman Sharma1-2/+2
The platform_get_irq*() interfaces return either a negative error number or a valid IRQ. 0 is not a valid return value, so check for "< 0" to detect failure as recommended by the function documentation. On failure, return the error number from platform_get_irq*() instead of making up a new one. Link: https://lore.kernel.org/r/cover.1583952275.git.amanharitsh123@gmail.com [bhelgaas: commit log, squash into one patch] Signed-off-by: Aman Sharma <amanharitsh123@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Ryder Lee <ryder.lee@mediatek.com> Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
2020-04-02PCI: tegra: Print -EPROBE_DEFER error message at debug levelThierry Reding1-7/+35
Probe deferral is an expected error condition that will usually be recovered from. Print such error messages at debug level to make them available for diagnostic purposes when building with debugging enabled and hide them otherwise to not spam the kernel log with them. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Vidya Sagar <vidyas@nvidia.com> Tested-by: Vidya Sagar <vidyas@nvidia.com>
2020-03-31PCI: tegra: Add support for PCIe endpoint mode in Tegra194Vidya Sagar1-15/+665
Add support for the endpoint mode of Synopsys DesignWare core based dual mode PCIe controllers present in Tegra194 SoC. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
2019-10-18PCI: tegra: Fix CLKREQ dependency programmingVidya Sagar1-4/+2
Corrects the programming to provide REFCLK to the downstream device when there is no CLKREQ sideband signal routing present from root port to the endpont. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
2019-09-20PCI: tegra: Add support to enable slot regulatorsVidya Sagar1-0/+83
Add support to get regulator information of 3.3V and 12V supplies of a PCIe slot from the respective controller's device-tree node and enable those supplies. This is required in platforms like p2972-0000 where the supplies to x16 slot owned by C5 controller need to be enabled before attempting to enumerate the devices. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
2019-09-20PCI: tegra: Add support to configure sideband pinsVidya Sagar1-2/+10
Add support to configure sideband signal pins when the information is present in the respective controller device-tree node. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [bhelgaas: fold in YueHaibing's fix for build error without CONFIG_PINCTRL; https://lore.kernel.org/r/20190920014807.38288-1-yuehaibing@huawei.com] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
2019-09-08PCI: tegra: Add Tegra194 PCIe supportVidya Sagar1-0/+1641
Add support for Synopsys DesignWare core IP based PCIe host controller present in the Tegra194 SoC. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-28 09:26:03 +0300