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2022-01-02qed: Use dma_set_mask_and_coherent() and simplify codeChristophe JAILLET1-23/+5
Use dma_set_mask_and_coherent() instead of unrolling it with some dma_set_mask()+dma_set_coherent_mask(). Moreover, as stated in [1], dma_set_mask() with a 64-bit mask will never fail if dev->dma_mask is non-NULL. So, if it fails, the 32 bits case will also fail for the same reason. Simplify code and remove some dead code accordingly. Now that qed_set_coherency_mask() is mostly a single call to dma_set_mask_and_coherent(), fold it in its only caller. [1]: https://lkml.org/lkml/2021/6/7/398 Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02chelsio: cxgb: Use dma_set_mask_and_coherent() and simplify codeChristophe JAILLET1-15/+4
Use dma_set_mask_and_coherent() instead of unrolling it with some dma_set_mask()+dma_set_coherent_mask(). Moreover, as stated in [1], dma_set_mask() with a 64-bit mask will never fail if dev->dma_mask is non-NULL. So, if it fails, the 32 bits case will also fail for the same reason. That said, 'pci_using_dac' can only be 1 after a successful dma_set_mask_and_coherent(). Simplify code and remove some dead code accordingly. [1]: https://lkml.org/lkml/2021/6/7/398 Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02sun/cassini: Use dma_set_mask_and_coherent() and simplify codeChristophe JAILLET1-20/+6
Use dma_set_mask_and_coherent() instead of unrolling it with some dma_set_mask()+dma_set_coherent_mask(). Moreover, as stated in [1], dma_set_mask() with a 64-bit mask will never fail if dev->dma_mask is non-NULL. So, if it fails, the 32 bits case will also fail for the same reason. That said, 'pci_using_dac' can only be 1 after a successful dma_set_mask_and_coherent(). Simplify code and remove some dead code accordingly. [1]: https://lkml.org/lkml/2021/6/7/398 Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02rndis_host: support Hytera digital radiosThomas Toye1-0/+5
Hytera makes a range of digital (DMR) radios. These radios can be programmed to a allow a computer to control them over Ethernet over USB, either using NCM or RNDIS. This commit adds support for RNDIS for Hytera radios. I tested with a Hytera PD785 and a Hytera MD785G. When these radios are programmed to set up a Radio to PC Network using RNDIS, an USB interface will be added with class 2 (Communications), subclass 2 (Abstract Modem Control) and an interface protocol of 255 ("vendor specific" - lsusb even hints "MSFT RNDIS?"). This patch is similar to the solution of this StackOverflow user, but that only works for the Hytera MD785: https://stackoverflow.com/a/53550858 To use the "Radio to PC Network" functionality of Hytera DMR radios, the radios need to be programmed correctly in CPS (Hytera's Customer Programming Software). "Forward to PC" should be checked in "Network" (under "General Setting" in "Conventional") and the "USB Network Communication Protocol" should be set to RNDIS. Signed-off-by: Thomas Toye <thomas@toye.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02net: ena: Fix error handling when calculating max IO queues numberArthur Kiyanovski1-4/+0
The role of ena_calc_max_io_queue_num() is to return the number of queues supported by the device, which means the return value should be >=0. The function that calls ena_calc_max_io_queue_num(), checks the return value. If it is 0, it means the device reported it supports 0 IO queues. This case is considered an error and is handled by the calling function accordingly. However the current implementation of ena_calc_max_io_queue_num() is wrong, since when it detects the device supports 0 IO queues, it returns -EFAULT. In such a case the calling function doesn't detect the error, and therefore doesn't handle it. This commit changes ena_calc_max_io_queue_num() to return 0 in case the device reported it supports 0 queues, allowing the calling function to properly handle the error case. Fixes: 736ce3f414cc ("net: ena: make ethtool -l show correct max number of queues") Signed-off-by: Shay Agroskin <shayagr@amazon.com> Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02net: ena: Fix wrong rx request id by resetting deviceArthur Kiyanovski1-2/+9
A wrong request id received from the device is a sign that something is wrong with it, therefore trigger a device reset. Also add some debug info to the "Page is NULL" print to make it easier to debug. Fixes: 1738cd3ed342 ("net: ena: Add a driver for Amazon Elastic Network Adapters (ENA)") Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02net: ena: Fix undefined state when tx request id is out of boundsArthur Kiyanovski1-14/+20
ena_com_tx_comp_req_id_get() checks the req_id of a received completion, and if it is out of bounds returns -EINVAL. This is a sign that something is wrong with the device and it needs to be reset. The current code does not reset the device in this case, which leaves the driver in an undefined state, where this completion is not properly handled. This commit adds a call to handle_invalid_req_id() in ena_clean_tx_irq() and ena_clean_xdp_irq() which resets the device to fix the issue. This commit also removes unnecessary request id checks from validate_tx_req_id() and validate_xdp_req_id(). This check is unneeded because it was already performed in ena_com_tx_comp_req_id_get(), which is called right before these functions. Fixes: 548c4940b9f1 ("net: ena: Implement XDP_TX action") Signed-off-by: Shay Agroskin <shayagr@amazon.com> Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02tehuti: Use dma_set_mask_and_coherent() and simplify codeChristophe JAILLET1-18/+10
Use dma_set_mask_and_coherent() instead of unrolling it with some dma_set_mask()+dma_set_coherent_mask(). Moreover, as stated in [1], dma_set_mask_and_coherent() with a 64-bit mask will never fail if dev->dma_mask is non-NULL. So, if it fails, the 32 bits case will also fail for the same reason. That said, 'pci_using_dac' can only be 1 after a successful dma_set_mask_and_coherent(). Simplify code and remove some dead code accordingly. [1]: https://lkml.org/lkml/2021/6/7/398 Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-02enic: Use dma_set_mask_and_coherent()Christophe JAILLET1-14/+2
Use dma_set_mask_and_coherent() instead of unrolling it with some dma_set_mask()+dma_set_coherent_mask(). This simplifies code and removes some dead code (dma_set_coherent_mask() can not fail after a successful dma_set_mask()) Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-nextDavid S. Miller59-37/+63
Alexei Starovoitov says: ==================== pull-request: bpf-next 2021-12-30 The following pull-request contains BPF updates for your *net-next* tree. We've added 72 non-merge commits during the last 20 day(s) which contain a total of 223 files changed, 3510 insertions(+), 1591 deletions(-). The main changes are: 1) Automatic setrlimit in libbpf when bpf is memcg's in the kernel, from Andrii. 2) Beautify and de-verbose verifier logs, from Christy. 3) Composable verifier types, from Hao. 4) bpf_strncmp helper, from Hou. 5) bpf.h header dependency cleanup, from Jakub. 6) get_func_[arg|ret|arg_cnt] helpers, from Jiri. 7) Sleepable local storage, from KP. 8) Extend kfunc with PTR_TO_CTX, PTR_TO_MEM argument support, from Kumar. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31Merge tag 'mlx5-updates-2021-12-28' of ↵David S. Miller19-273/+1291
git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5 Software steering, New features and optimizations This patch series brings various SW steering features, optimizations and debug-ability focused improvements. 1) Expose debugfs for dumping the SW steering resources 2) Removing unused fields 3) support for matching on new fields 4) steering optimization for RX/TX-only rules 5) Make Software steering the default steering mechanism when available, applies only to Switchdev mode FDB From Yevgeny Kliteynik and Muhammad Sammar: - Patch 1 fixes an error flow in creating matchers - Patch 2 fix lower case macro prefix "mlx5_" to "MLX5_" - Patch 3 removes unused struct member in mlx5dr_matcher - Patch 4 renames list field in matcher struct to list_node to reflect the fact that is field is for list node that is stored on another struct's lists - Patch 5 adds checking for valid Flex parser ID value - Patch 6 adds the missing reserved fields to dr_match_param and aligns it to the format that is defined by HW spec - Patch 7 adds support for dumping SW steering (SMFS) resources using debugfs in CSV format: domain and its tables, matchers and rules - Patch 8 adds support for a new destination type - UPLINK - Patch 9 adds WARN_ON_ONCE on refcount checks in SW steering object destructors - Patches 10, 11, 12 add misc5 flow table match parameters and add support for matching on tunnel headers 0 and 1 - Patch 13 adds support for matching on geneve_tlv_option_0_exist field - Patch 14 implements performance optimization for for empty or RX/TX-only matchers by splitting RX and TX matchers handling: matcher connection in the matchers chain is split into two separate lists (RX only and TX only), which solves a usecase of many RX or TX only rules that create a long chain of RX/TX-only paths w/o the actual rules - Patch 15 ignores modify TTL if device doesn't support it instead of adding and unsupported action - Patch 16 sets SMFS as a default steering mode ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: delete the hclge_cmd.c and hclgevf_cmd.cJie Wang5-66/+42
currently most cmdq APIs are unified in hclge_comm_cmd.c. Newly developed cmdq APIs should also be placed in hclge_comm_cmd.c. So there is no need to keep hclge_cmd.c and hclgevf_cmd.c. This patch moves the hclge(vf)_cmd_send to hclge(vf)_main.c and deletes the source files and makefile scripts. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor VF cmdq init and uninit APIs with new common APIsJie Wang5-204/+36
This patch uses common cmdq init and uninit APIs to replace the old APIs in VF cmdq module init and uninit module. Then the old VF init and uninit APIs is deleted. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor PF cmdq init and uninit APIs with new common APIsJie Wang5-197/+27
This patch uses common cmdq init and uninit APIs to replace the old APIs in PF cmdq module init and uninit modules. Then the old PF init and uninit APIs is deleted. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: create common cmdq init and uninit APIsJie Wang2-0/+163
The PF and VF cmdq init and uninit APIs are also almost same espect the suffixes of API names. This patch creates common cmdq init and uninit APIs needed by PF and VF cmdq modules. The next patch will use the new unified APIs to replace init and uninit APIs in PF module. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor VF cmdq resource APIs with new common APIsJie Wang2-231/+19
This patch uses common cmdq resource allocate/free/query APIs to replace the old APIs in VF cmdq module and deletes the old cmdq resource APIs. Still we kept hclgevf_cmd_setup_basic_desc name as a seam API to avoid too many meaningless replacement. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor PF cmdq resource APIs with new common APIsJie Wang5-323/+63
This patch uses common cmdq resource allocate/free/query APIs to replace the old APIs in PF cmdq module and deletes the old cmdq resource APIs. Still we kept hclge_cmd_setup_basic_desc name as a seam API to avoid too many meaningless replacement. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: create common cmdq resource allocate/free/query APIsJie Wang2-1/+311
The PF and VF cmdq module resource allocate/free/query APIs are almost the same espect the suffixes of API names. These same implementations bring double development and bugfix work. This patch creates common cmdq resource allocate/free/query APIs called by PF and VF cmdq init/uninit APIs. The next patch will use the new unified APIs to replace init/uninit APIs. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor hclgevf_cmd_send with new hclge_comm_cmd_send APIJie Wang5-360/+82
This patch firstly uses new hardware description struct hclge_comm_hw as child member of hclgevf_hw and deletes the old hardware description child members. All the hclgevf_hw variables used in VF module is modified according to the new hclgevf_hw. Secondly hclgevf_cmd_send is refactored to use hclge_comm_cmd_send APIs. The old functions called by hclgevf_cmd_send are all deleted. Still we kept hclgevf_cmd_send to avoid too many meaningless modifications. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor hclge_cmd_send with new hclge_comm_cmd_send APIJie Wang8-373/+100
This patch firstly uses new hardware description struct hclge_comm_hw as child member of hclge_hw and deletes the original child memebers of hclge_hw. All the hclge_hw variables used in PF module is modified according to the new hclge_hw. Secondly hclge_cmd_send is refactored to use hclge_comm_cmd_send APIs. The old functions called by hclge_cmd_send are deleted and hclge_cmd_send is kept to avoid too many meaningless modifications. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: create new set of unified hclge_comm_cmd_send APIsJie Wang2-0/+325
This patch create new set of unified hclge_comm_cmd_send APIs for PF and VF cmdq module. Subfunctions called by hclge_comm_cmd_send are also created include cmdq result check, cmdq return code conversion and ring space opertaion APIs. These new common cmdq APIs will be used to replace the old PF and VF cmdq APIs in next patches. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: use struct hclge_desc to replace hclgevf_desc in VF cmdq moduleJie Wang4-35/+28
This patch use new common struct hclge_desc to replace struct hclgevf_desc in VF cmdq module and then delete the old struct hclgevf_desc. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: create new cmdq hardware description structure hclge_comm_hwJie Wang3-8/+57
Currently PF and VF cmdq APIs use struct hclge(vf)_hw to describe cmdq hardware information needed by hclge(vf)_cmd_send. There are a little differences between its child struct hclge_cmq_ring and hclgevf_cmq_ring. It is redundent to use two sets of structures to support same functions. So this patch creates new set of common cmdq hardware description structures(hclge_comm_hw) to unify PF and VF cmdq functions. The struct hclge_desc is still kept to avoid too many meaningless replacement. These new structures will be used to unify hclge(vf)_hw structures in PF and VF cmdq APIs in next patches. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor hns3 makefile to support hns3_common moduleJie Wang3-25/+11
Currently we plan to refactor PF and VF cmdq module. A new file folder hns3_common will be created to store new common APIs used by PF and VF cmdq module. Thus the PF and VF compilation process will both depends on the hns3_common. This may cause parallel building problems if we add a new makefile building unit. So this patch combined the PF and VF makefile scripts to the top level makefile to support the new hns3_common which will be created in the next patch. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net/mlx5: Set SMFS as a default steering mode if device supports itYevgeny Kliteynik1-0/+5
Set SMFS (SW-managed flow steering) as a default steering mode instead of DMFS (device-managed flow steering) In SMFS, the driver writes the STEs (Steering Table Entries) directly to the device's ICM, which allows for a higher rule insertion rate than through using FW command interface, as it is done in DMFS. SMFS/DMFS steering modes can be configured through devlink param 'flow_steering_mode'. The possible values are 'smfs' or 'dmfs'. The desired 'flow_steering_mode' param value should be set before enabling switchdev mode. Example: # devlink dev param set pci/0000:05:00.0 name flow_steering_mode smfs # devlink dev eswitch set pci/0000:05:00.0 mode switchdev Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Ignore modify TTL if device doesn't support itYevgeny Kliteynik1-3/+18
When modifying TTL, packet's csum has to be recalculated. Due to HW issue in ConnectX-5, csum recalculation for modify TTL is supported through a work-around that is specifically enabled by configuration. If the work-around isn't enabled, ignore the modify TTL action rather than adding an unsupported action. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Improve steering for empty or RX/TX-only matchersYevgeny Kliteynik4-130/+156
Every matcher has RX and TX paths. When a new matcher is created, its RX and TX start/end anchors are connected to the respective RX and TX anchors of the previous and next matchers. This creates a potential performance issue: when a certain rule is added to a matcher, in many cases it is RX or TX only rule, which may create a long chain of RX/TX-only paths w/o the actual rules. This patch aims to handle this issue. RX and TX matchers are now handled separately: matcher connection in the matchers chain is split into two separate lists: RX only and TX only. when a new matcher is created, it is initially created 'detached' - its RX/TX members are not inserted into the table's matcher list. When an actual rule is added, only its appropriate RX or TX nic matchers are then added to the table's nic matchers list and inserted into its place in the chain of matchers. I.e., if the rule that is being added is an RX-only rule, only the RX part of the matcher will be connected to the chain, while TX part of the matcher remains detached and doesn't prolong the TX chain of the matchers. Same goes for rule deletion: when the last RX/TX rule of the nic matcher is destroyed, the nic matcher is removed from its list. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist fieldYevgeny Kliteynik7-1/+86
Match on geneve_tlv_option_0_exist field on devices that support STEv1. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Support matching on tunnel headers 0 and 1Muhammad Sammar7-1/+79
Tunnel headers are generic encapsulation headers, applies for all tunneling protocols identified by the device native parser or by the programmable parser, this support will enable raw matching headers 0 and 1. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add misc5 to match_param structsMuhammad Sammar4-1/+61
Add misc5 match params to enable matching tunnel headers. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
2021-12-31net/mlx5: Add misc5 flow table match parametersMuhammad Sammar1-1/+1
Add support for misc5 match parameter as per HW spec, this will allow matching on tunnel_header fields. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Warn on failure to destroy objects due to refcountYevgeny Kliteynik4-4/+4
Add WARN_ON_ONCE on refcount checks in SW steering object destructors Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for UPLINK destination typeYevgeny Kliteynik4-10/+34
Add support for a new destination type - UPLINK. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for dumping steering infoMuhammad Sammar8-8/+688
Extend mlx5 debugfs support to present Software Steering resources: dr_domain including it's tables, matchers and rules. The interface is read-only. While dump is being presented, new steering rules cannot be inserted/deleted. The steering information is dumped in the CSV form with the following format: <object_type>,<object_ID>, <object_info>,...,<object_info> This data can be read at the following path: /sys/kernel/debug/mlx5/<BDF>/steering/fdb/<domain_handle> Example: # cat /sys/kernel/debug/mlx5/0000:82:00.0/steering/fdb/dmn_000018644 3100,0x55caa4621c50,0xee802,4,65533 3101,0x55caa4621c50,0xe0100008 Changes in V2: - Reduce temp hex buffer size and avoid unnecessary memset - Use bin2hex() instead of DIY loop - Don't check debugfs functions return values Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add missing reserved fields to dr_match_paramMuhammad Sammar1-89/+124
Add the reserved fields to dr_match_param and arrange as mlx5_ifc_dr_match_param_bits. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
2021-12-31net/mlx5: DR, Add check for flex parser ID valueYevgeny Kliteynik2-2/+2
Allow only legal values for flex parser ID - values from 0 to 7. For other values skip the parser, and as a result the matcher creation will fail for using invalid flex parser ID. Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Rename list field in matcher struct to list_nodeYevgeny Kliteynik3-15/+15
In dr_types structs, some list fields are list heads, and some are just list nodes that are stored on the other structs' lists. Rename the appropriate list field to reflect this distinction. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Remove unused struct member in matcherYevgeny Kliteynik1-1/+0
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Fix lower case macro prefix "mlx5_" to "MLX5_"Yevgeny Kliteynik2-2/+2
Macros prefix should be capital letters - fix the prefix in mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Fix error flow in creating matcherYevgeny Kliteynik1-21/+32
The error code of nic matcher init functions wasn't checked. This patch improves the matcher init function and fix error flow bug: the handling of match parameter is moved into a separate function and error flow is simplified. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net: dsa: bcm_sf2: refactor LED regs accessRafał Miłecki3-10/+119
1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs. 2. Add helper for handling non-lineral port <-> reg mappings. 3. Add support for 12 B LED reg blocks on BCM4908 (different layout) Complete support for LEDs setup will be implemented once Linux receives a proper design & implementation for "hardware" LEDs. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-12-30Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski24-133/+312
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c commit 077cdda764c7 ("net/mlx5e: TC, Fix memory leak with rules with internal port") commit 31108d142f36 ("net/mlx5: Fix some error handling paths in 'mlx5e_tc_add_fdb_flow()'") commit 4390c6edc0fb ("net/mlx5: Fix some error handling paths in 'mlx5e_tc_add_fdb_flow()'") https://lore.kernel.org/all/20211229065352.30178-1-saeed@kernel.org/ net/smc/smc_wr.c commit 49dc9013e34b ("net/smc: Use the bitmap API when applicable") commit 349d43127dac ("net/smc: fix kernel panic caused by race of smc_sock") bitmap_zero()/memset() is removed by the fix Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-12-30fsl/fman: Fix missing put_device() call in fman_port_probeMiaoqian Lin1-5/+7
The reference taken by 'of_find_device_by_node()' must be released when not needed anymore. Add the corresponding 'put_device()' in the and error handling paths. Fixes: 18a6c85fcc78 ("fsl/fman: Add FMan Port Support") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-30net: lantiq_etop: remove unnecessary space in castAleksander Jan Bajkowski1-1/+1
As reported by checkpatch.pl, no space is necessary after a cast. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-30net: lantiq_etop: make alignment match open parenthesisAleksander Jan Bajkowski1-17/+17
checkpatch.pl complains as the following: Alignment should match open parenthesis Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-30net: lantiq_etop: remove multiple assignmentsAleksander Jan Bajkowski1-1/+2
Documentation/process/coding-style.rst says (in line 88) "Don't put multiple assignments on a single line either." This patch fixes the coding style issue reported by checkpatch.pl. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-30net: lantiq_etop: avoid precedence issuesAleksander Jan Bajkowski1-2/+2
Add () around macro argument to avoid precedence issues Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-30net: lantiq_etop: replace strlcpy with strscpyAleksander Jan Bajkowski1-3/+3
strlcpy is marked as deprecated in Documentation/process/deprecated.rst, and there is no functional difference when the caller expects truncation (when not checking the return value). strscpy is relatively better as it also avoids scanning the whole source string. This silences the related checkpatch warnings from: commit 5dbdb2d87c29 ("checkpatch: prefer strscpy to strlcpy") Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-30ice: Add flow director support for channel modeKiran Patil8-25/+444
Add support to enable flow-director filter when multiple TCs are configured. Flow director filter can be configured using ethtool (--config-ntuple option). When multiple TCs are configured, each TC is mapped to an unique HW VSI. So VSI corresponding to queue used in filter is identified and flow director context is updated with correct VSI while configuring ntuple filter in HW. Signed-off-by: Kiran Patil <kiran.patil@intel.com> Signed-off-by: Amritha Nambiar <amritha.nambiar@intel.com> Signed-off-by: Sudheer Mogilappagari <sudheer.mogilappagari@intel.com> Tested-by: Bharathi Sreenivas <bharathi.sreenivas@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-30Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-David S. Miller2-45/+291
queue Tony Nguyen says: ==================== 1GbE Intel Wired LAN Driver Updates 2021-12-29 Ruud Bos says: The igb driver provides support for PEROUT and EXTTS pin functions that allow adapter external use of timing signals. At Hottinger Bruel & Kjaer we are using the PEROUT function to feed a PTP corrected 1pps signal into an FPGA as cross system synchronized time source. Support for the PEROUT and EXTTS SDP functions is currently limited to i210/i211 based adapters. This patch series enables these functions also for 82580/i354/i350 based ones. Because the time registers of these adapters do not have the nice split in second rollovers as the i210 has, the implementation is slightly more complex compared to the i210 implementation. The PEROUT function has been successfully tested on an i350 based ethernet adapter. Using the following user space code excerpt, the driver outputs a PTP corrected 1pps signal on the SDP0 pin of an i350: struct ptp_pin_desc desc; memset(&desc, 0, sizeof(desc)); desc.index = 0; desc.func = PTP_PF_PEROUT; desc.chan = 0; if (ioctl(fd, PTP_PIN_SETFUNC, &desc) == 0) { struct timespec ts; if (clock_gettime(clkid, &ts) == 0) { struct ptp_perout_request rq; memset(&rq, 0, sizeof(rq)); rq.index = 0; rq.start.sec = ts.tv_sec + 1; rq.start.nsec = 500000000; rq.period.sec = 1; rq.period.nsec = 0; if (ioctl(fd, PTP_PEROUT_REQUEST, &rq) == 0) { /* 1pps signal is now available on SDP0 */ } } } The added EXTTS function has not been tested. However, looking at the data sheets, the layout of the registers involved match the i210 exactly except for the time registers mentioned before. Hence the almost identical implementation. --- Note: I made changes to fix RCT and checkpatch messages regarding unnecessary parenthesis. ==================== Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>