summaryrefslogtreecommitdiff
path: root/drivers/net/dsa/mv88e6xxx/chip.c
AgeCommit message (Expand)AuthorFilesLines
2017-06-05net: dsa: mv88e6xxx: 6161 uses global 2 for PHY accessAndrew Lunn1-4/+4
2017-06-05net: dsa: mv88e6xxx: rename chip headerVivien Didelot1-1/+1
2017-05-31net: dsa: remove dev arg of dsa_register_switchVivien Didelot1-1/+1
2017-05-31net: dsa: mv88e6xxx: rename PHY PPU accessorsVivien Didelot1-8/+8
2017-05-31net: dsa: mv88e6xxx: provide a PHY setup helperVivien Didelot1-7/+4
2017-05-28net: dsa: mv88e6xxx: handle SERDES error appropriatelyVivien Didelot1-12/+7
2017-05-26dsa: mv88e6xxx: Enable/Disable SERDES on port enable/disableAndrew Lunn1-8/+42
2017-05-26net: dsa: mv88e6xxx: mv88e6390X SERDES supportAndrew Lunn1-0/+6
2017-05-26net: dsa: mv88e6xxx: Refactor mv88e6352 SERDES code into an opAndrew Lunn1-45/+19
2017-05-26net: dsa: mv88e6xxx: Move phy functions into phy.[ch]Andrew Lunn1-231/+2
2017-05-18net: dsa: use switchdev_obj_dump_cb_t everywhereVivien Didelot1-5/+5
2017-05-18net: dsa: include switchdev.h only onceVivien Didelot1-1/+0
2017-05-12net: dsa: mv88e6xxx: add default case to switchGustavo A. R. Silva1-0/+3
2017-05-01net: dsa: mv88e6xxx: add VTU support for 88E6390Vivien Didelot1-0/+18
2017-05-01net: dsa: mv88e6xxx: simplify VTU entry getterVivien Didelot1-38/+24
2017-05-01net: dsa: mv88e6xxx: add VTU Load/Purge operationVivien Didelot1-49/+31
2017-05-01net: dsa: mv88e6xxx: add VTU GetNext operationVivien Didelot1-48/+34
2017-05-01net: dsa: mv88e6xxx: load STU entry with VTU entryVivien Didelot1-104/+4
2017-05-01net: dsa: mv88e6xxx: get STU entry on VTU GetNextVivien Didelot1-1/+1
2017-05-01net: dsa: mv88e6xxx: move STU GetNext operationVivien Didelot1-13/+1
2017-05-01net: dsa: mv88e6xxx: move VTU Data accessorsVivien Didelot1-81/+7
2017-05-01net: dsa: mv88e6xxx: move generic VTU GetNextVivien Didelot1-29/+2
2017-05-01net: dsa: mv88e6xxx: move VTU VID accessorsVivien Didelot1-34/+23
2017-05-01net: dsa: mv88e6xxx: move VTU SID accessorsVivien Didelot1-13/+8
2017-05-01net: dsa: mv88e6xxx: move VTU FID accessorsVivien Didelot1-5/+2
2017-05-01net: dsa: mv88e6xxx: move VTU flushVivien Didelot1-16/+12
2017-05-01net: dsa: mv88e6xxx: move VTU Operation accessorsVivien Didelot1-29/+10
2017-05-01net: dsa: mv88e6xxx: split VTU entry data memberVivien Didelot1-10/+11
2017-05-01net: dsa: mv88e6xxx: add max VID to infoVivien Didelot1-9/+29
2017-04-01net: dsa: mv88e6xxx: add cross-chip bridgingVivien Didelot1-1/+33
2017-04-01net: dsa: mv88e6xxx: remap existing bridge membersVivien Didelot1-0/+20
2017-04-01net: dsa: mv88e6xxx: factorize in-chip bridge mapVivien Didelot1-22/+25
2017-04-01net: dsa: mv88e6xxx: rework in-chip bridgingVivien Didelot1-17/+32
2017-04-01net: dsa: mv88e6xxx: allocate the number of portsVivien Didelot1-1/+1
2017-04-01net: dsa: mv88e6xxx: program the PVT with all onesVivien Didelot1-1/+30
2017-04-01net: dsa: mv88e6xxx: use 4-bit port for PVT dataVivien Didelot1-0/+15
2017-04-01net: dsa: mv88e6xxx: move PVT description in infoVivien Didelot1-0/+22
2017-03-29net: dsa: fix copyright holderVivien Didelot1-0/+3
2017-03-29net: dsa: mv88e6xxx: remove 88E6391 opsVivien Didelot1-30/+0
2017-03-29net: dsa: mv88e6xxx: fix 88E6191 opsVivien Didelot1-1/+1
2017-03-29net: dsa: mv88e6xxx: reorder 88E6341 definitionsVivien Didelot1-31/+31
2017-03-29net: dsa: mv88e6xxx: reorder 88E6141 definitionsVivien Didelot1-46/+46
2017-03-16net: dsa: mv88e6xxx: specify ageing time limitsVivien Didelot1-0/+2
2017-03-13net: dsa: mv88e6xxx: add port priority override opVivien Didelot1-13/+26
2017-03-13net: dsa: mv88e6xxx: add port ATU learn limit opVivien Didelot1-6/+30
2017-03-13net: dsa: mv88e6xxx: fix port egress flooding modeVivien Didelot1-65/+38
2017-03-13net: dsa: mv88e6xxx: rework port mode setupVivien Didelot1-47/+59
2017-03-13net: dsa: mv88e6xxx: rename the port vector memberVivien Didelot1-4/+4
2017-03-13net: dsa: mv88e6xxx: rename new FID helperVivien Didelot1-2/+2
2017-03-13net: dsa: mv88e6xxx: rework ATU RemoveVivien Didelot1-112/+28
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-01 02:30:02 +0300