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path: root/drivers/mtd/spi-nor
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2023-09-19mtd: spi-nor: drop .parse_sfdpMichael Walle9-36/+22
Drop the size parameter to indicate we need to do SFDP, we can do that because it is guaranteed that the size will be set by SFDP and because PARSE_SFDP forced the SFDP parsing it must be overwritten. There is a (very tiny) chance that this might break block protection support: we now rely on the SFDP reported size of the flash for the BP calculation. OTOH, if the flash reports its size wrong, we are in bigger trouble than just having the BP calculation wrong. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-11-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: make sector_size optionalMichael Walle4-7/+16
Most of the (old, non-SFDP) flashes use a sector size of 64k. Make that a default value so it can be optional in the flash_info database. As a preparation for conversion to the new database format, set the sector size to zero if the default value is used. This way, the actual change is happening with this patch ant not with a later conversion patch. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-10-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: push 4k SE handling into spi_nor_select_uniform_erase()Michael Walle1-18/+9
4k sector erase sizes are only a thing with uniform erase types. Push the "we want 4k erase sizes" handling into spi_nor_select_uniform_erase(). One might wonder why the former sector_size isn't used anymore. It is because we either search for the largest erase size or if selected through kconfig, the 4k erase size. Now, why is that correct? For this, we have to differentiate between (1) flashes with SFDP and (2) without SFDP. For (1), we just set one (or two if SECT_4K is set) erase types and wanted_size is exactly one of these. For (2) things are a bit more complicated. For flashes which we don't have in our flash_info database, the generic driver is used and sector_size was already 0, which in turn selected the largest erase size. For flashes which had SFDP and an entry in flash_info, sector_size was always the largest sector and thus the largest erase type. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-9-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: default .n_banks to 1Michael Walle3-7/+5
If .n_banks is not set in the flash_info database, the default value should be 1. This way, we don't have to always set the .n_banks parameter in flash_info. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-8-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: store .n_banks in struct spi_nor_flash_parameterMichael Walle2-3/+6
First, fixups might want to replace the n_banks parameter, thus we need it in the (writable) parameter struct. Secondly, this way we can have a default in the core and just skip setting the n_banks in the flash_info database. Most of the flashes doesn't have more than one bank. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-7-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: default page_size to 256 bytesMichael Walle2-8/+7
The INFO() macro always set the page_size to 256 bytes. Make that an optional parameter. This default is a sane one for all older flashes, newer ones will set the page size by its SFDP tables anyway. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-6-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: convert .n_sectors to .sizeMichael Walle4-11/+12
.n_sectors is rarely used. In fact it is only used in swp.c and to calculate the flash size in the core. The use in swp.c might be converted to use the (largest) flash erase size. For now, we just locally calculate the sector size. Simplify the flash_info database and set the size of the flash directly. This also let us use the SZ_x macros. Verified that there's no flash that specifies BP and sector size of zero to make sure we avoid a division by zero in spi_nor_get_min_prot_length_sr(). We'll protect from a possible division by zero in a further patch by introducing a default value for sector_size. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-5-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: xilinx: remove addr_nbytes from S3AN_INFO()Michael Walle1-1/+0
The default value of addr_nbytes is already 3. Drop it. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-4-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: xilinx: use SPI_NOR_ID() in S3AN_INFO()Michael Walle1-6/+1
In commit 59273180299a ("mtd: spi-nor: Create macros to define chip IDs and geometries") SPI_NOR_ID() were introduced, but it did only update the INFO() macro in core.h. Also use it in S3AN_INFO(). Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-3-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: remove Fujitsu MB85RS1MT supportMichael Walle4-24/+0
This part is not a flash but an EEPROM like FRAM. It is even has a DT binding for the (correct) driver (at25), see Documentation/devicetree/bindings/eeprom/at25.yaml. Just remove it. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-2-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-19mtd: spi-nor: remove catalyst 'flashes'Michael Walle4-27/+0
CAT25xx are actually EEPROMs manufactured by Catalyst. The devices are ancient (DS are from 1998), there are not in-tree users, nor are there any device tree bindings. Remove it. The correct driver is the at25. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-1-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-09-03Merge tag 'mtd/for-6.6' of ↵Linus Torvalds13-184/+293
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "Core MTD changes: - Use refcount to prevent corruption - Call external _get and _put in right order - Fix use-after-free in mtd release - Explicitly include correct DT includes - Clean refcounting with MTD_PARTITIONED_MASTER - mtdblock: make warning messages ratelimited - dt-bindings: Add SEAMA partition bindings Device driver changes: - Use devm helper functions - Fix questionable cast, remove pointless ones. - error handling fixes - add support for new chip versions - update DT bindings - misc cleanups - fix typos, whitespace, indentation" * tag 'mtd/for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (105 commits) dt-bindings: mtd: amlogic,meson-nand: drop unneeded quotes mtd: spear_smi: Use helper function devm_clk_get_enabled() mtd: rawnand: orion: Use helper function devm_clk_get_optional_enabled() mtd: rawnand: vf610_nfc: Use helper function devm_clk_get_enabled() mtd: rawnand: sunxi: Use helper function devm_clk_get_enabled() mtd: rawnand: stm32_fmc2: Use helper function devm_clk_get_enabled() mtd: rawnand: mtk: Use helper function devm_clk_get_enabled() mtd: rawnand: mpc5121: Use helper function devm_clk_get_enabled() mtd: rawnand: lpc32xx_slc: Use helper function devm_clk_get_enabled() mtd: rawnand: intel: Use helper function devm_clk_get_enabled() mtd: rawnand: fsmc: Use helper function devm_clk_get_enabled() mtd: rawnand: arasan: Use helper function devm_clk_get_enabled() mtd: rawnand: qcom: Add read/read_start ops in exec_op path mtd: rawnand: qcom: Clear buf_count and buf_start in raw read mtd: maps: fix -Wvoid-pointer-to-enum-cast warning mtd: rawnand: fix -Wvoid-pointer-to-enum-cast warning mtd: rawnand: fsmc: handle clk prepare error in fsmc_nand_resume() mtd: rawnand: Propagate error and simplify ternary operators for brcmstb_nand_wait_for_completion() mtd: rawnand: qcom: Sort includes alphabetically mtd: rawnand: qcom: Do not override the error no of submit_descs() ...
2023-08-18Merge tag 'spi-nor/for-6.6' into mtd/nextMiquel Raynal13-183/+293
SPI NOR core changes: * fix assumption on enabling quad mode in spi_nor_write_16bit_sr_and_check() * avoid setting SRWD bit in SR if WP# signal not connected as it will configure the SR permanently as read only. Add "no-wp" dt property. * clarify the need for spi-nor compatibles in dt-bindings SPI NOR manufacturer drivers changes: * spansion: - add support for S28HS02GT - switch methods to use vreg_offset from SFDP instead of hardcoding the register value * microchip/sst: - add support for sst26vf032b flash * winbond: - correct flags for Winbond w25q128 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2023-08-18mtd: spi-nor: nxp-spifi: Use helper function devm_clk_get_enabled()Li Zetao1-27/+6
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enable (and possibly prepare) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clock explicitly, so drop the label "dis_clks" and "dis_clk_reg". Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Li Zetao <lizetao1@huawei.com> Link: https://lore.kernel.org/r/20230818074642.308166-12-lizetao1@huawei.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-08-18mtd: spi-nor: Add support for sst26vf032b flashMiquel Raynal1-0/+4
Describe this new part. The datasheet is public. Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/SST26VF032B-SST26VF032BA-2.5V-3.0V-32-Mbit-Serial-Quad-IO-%28SQI%29-Flash-Memory-20005218K.pdf Here are the sfdp tables plus base testing to show it works. $ cat /sys/bus/spi/devices/spi0.0/spi-nor/partname sst26vf032b $ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id bf2642 $ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer sst $ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 53464450060102ff00060110300000ff81000106000100ffbf0001180002 0001fffffffffffffffffffffffffffffffffd20f1ffffffff0144eb086b 083b80bbfeffffffffff00ffffff440b0c200dd80fd810d820914824806f 1d81ed0f773830b030b0f7ffffff29c25cfff030c080ffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffff0004fff37f0000f57f0000f9ff 3d00f57f0000f37f0000ffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffbf2642ffb95ffdff30f260f332ff0a122346ff0f19320f1919ffffff ffffffff00669938ff05013506040232b03072428de89888a585c09faf5a ffff06ec060c0003080bffffffffff07ffff0202ff060300fdfd040600fc 0300fefe0202070e $ md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp e7efddddb3d5ee89ca37bf6b6e789645 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp $ dd if=/dev/urandom of=./qspi_test bs=1M count=1 1+0 records in 1+0 records out $ mtd_debug write /dev/mtd0 0 1048576 qspi_test Copied 1048576 bytes from qspi_test to address 0x00000000 in flash $ mtd_debug erase /dev/mtd0 0 1048576 Erased 1048576 bytes from address 0x00000000 in flash $ mtd_debug read /dev/mtd0 0 1048576 qspi_read Copied 1048576 bytes from address 0x00000000 in flash to qspi_read $ hexdump qspi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0100000 $ mtd_debug write /dev/mtd0 0 1048576 qspi_test Copied 1048576 bytes from qspi_test to address 0x00000000 in flash $ mtd_debug read /dev/mtd0 0 1048576 qspi_read Copied 1048576 bytes from address 0x00000000 in flash to qspi_read $ sha1sum qspi_test qspi_read 2f2f191c7a937eca5db21a1c39e79e7327587cc1 qspi_test 2f2f191c7a937eca5db21a1c39e79e7327587cc1 qspi_read Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230808075001.223150-1-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-08-18mtd: spi-nor: Check bus width while setting QE bitHsin-Yi Wang1-9/+10
spi_nor_write_16bit_sr_and_check() should also check if bus width is 4 before setting QE bit. Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Suggested-by: Michael Walle <michael@walle.cc> Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230818064524.1229100-2-hsinyi@chromium.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-27mtd: Explicitly include correct DT includesRob Herring1-1/+0
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230714174751.4060439-1-robh@kernel.org
2023-07-27mtd: spi-nor: avoid holes in struct spi_mem_opArnd Bergmann1-2/+2
gcc gets confused when -ftrivial-auto-var-init=pattern is used on sparse bit fields such as 'struct spi_mem_op', which caused the previous false positive warning about an uninitialized variable: drivers/mtd/spi-nor/spansion.c: error: 'op' is used uninitialized [-Werror=uninitialized] In fact, the variable is fully initialized and gcc does not see it being used, so the warning is entirely bogus. The problem appears to be a misoptimization in the initialization of single bit fields when the rest of the bytes are not initialized. A previous workaround added another initialization, which ended up shutting up the warning in spansion.c, though it apparently still happens in other files as reported by Peter Foley in the gcc bugzilla. The workaround of adding a fake initialization seems particularly bad because it would set values that can never be correct but prevent the compiler from warning about actually missing initializations. Revert the broken workaround and instead pad the structure to only have bitfields that add up to full bytes, which should avoid this behavior in all drivers. I also filed a new bug against gcc with what I found, so this can hopefully be addressed in future gcc releases. At the moment, only gcc-12 and gcc-13 are affected. Cc: Peter Foley <pefoley2@pefoley.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110743 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108402 Link: https://godbolt.org/z/efMMsG1Kx Fixes: 420c4495b5e56 ("mtd: spi-nor: spansion: make sure local struct does not contain garbage") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230719190045.4007391-1-arnd@kernel.org
2023-07-26mtd: spi-nor: spansion: switch cypress_nor_get_page_size() to use vreg_offsetTudor Ambarus1-65/+48
All users of cypress_nor_get_page_size() but S25FS256T retrieve n_dice and vreg_offset from SFDP. S25FS256T does not define the SCCR map to retrive the vreg_offset, but it does support it: SPINOR_REG_CYPRESS_VREG. Switch cypress_nor_get_page_size() to always use vreg_offset so that we use the same code base for both single and multi chip package flashes. cypress_nor_get_page_size() is now called in the post_sfdp() hook instead of post_bfpt(), as vreg_offset and n_dice are parsed after BFPT. Consequently the null checks on n_dice and vreg_offset are moved to the post_sfdp() hook. Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-12-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: switch s25hx_t to use vreg_offset for quad_enable()Tudor Ambarus1-11/+7
All s25hx_t flashes have single or multi chip flavors and already use n_dice and vreg_offset in cypress_nor_sr_ready_and_clear. Switch s25hx_t to always use vreg_offset for the quad_enable() method, so that we use the same code base for both single and multi chip package flashes. Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-11-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: let SFDP determine the flash and sector sizeTudor Ambarus1-8/+8
sector_size is used to determine the flash size and the erase size in case of uniform erase. n_sectors is used to determine the flash_size. But the flash size and the erase sizes are determined when parsing SFDP, let SFDP determine them. Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-10-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: add support for S28HS02GTTakahiro Kuwano1-5/+15
Add support for S28HS02GT. Infineon S28HS02GT is a 2Gb, multi-chip package, Octal SPI Flash. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-9-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OPTakahiro Kuwano1-1/+7
S28HS02GT uses RD_ANY_REG_OP to read status of each die. In Octal DTR mode, RD_ANY_REG_OP needs dummy cycles (same as params->rdsr_dummy) and data length should be 2. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-8-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: add MCP support in set_octal_dtr()Takahiro Kuwano1-14/+19
Infineon multi-chip package (MCP) devices require the Octal DTR configuraion to be set on each die. We can access to configuration registers in each die by using params->n_dice and params->vreg_offset[] populated from SFDP. Add MCP support in set_octal_dtr(). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-7-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offsetTakahiro Kuwano1-0/+1
s28hx is the sole user of cypress_nor_set_octal_dtr, which already uses vreg_offset to set octal DTR. Switch the ready method to use vreg_offset as well. This is a preparation patch. The goal is to use the same s28hx methods for the multi die version of the flash. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-6-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offsetTakahiro Kuwano1-6/+19
All the Infineon flashes that currently support octal DTR mode define the optional SCCR SFDP table, thus all retrieve vreg_offset. Switch all the available octal DTR Infineon flashes to use the volatile register offset to set the configuration registers. The goal is to have a single pair of methods for both single/multi-chip package devices. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-5-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: prepare octal dtr methods for multi chip supportTakahiro Kuwano1-13/+37
Infineon's multi-chip package (MCP) devices require the octal DTR configuration to be set for each die. Split common code in dedicated methods to ease the octal DDR MCP support addition. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-4-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLATTakahiro Kuwano1-1/+13
CFR2V[7] is assigned to Flash's address mode (3- or 4-ybte) and must not be changed when writing MEMLAT (CFR2V[3:0]). CFR2V shall be used in a read, update, write back fashion. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230726075257.12985-3-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-26mtd: spi-nor: spansion: use CLPEF as an alternative to CLSRTakahiro Kuwano10-32/+103
Infineon S28Hx (SEMPER Octal) and S25FS256T (SEMPER Nano) support Clear Program and Erase Failure Flags (CLPEF, 82h) instead of CLSR(30h). Introduce a new mfr_flag together with the infrastructure to allow manufacturer private data in the core. With this we remove the need to have if checks in the code at runtime and instead set the correct opcodes at probe time. S25Hx (SEMPER QSPI) supports CLSR but it may be disabled by CFR3x[2] while CLPEF is always available. Therefore, the mfr_flag is also applied to S25Hx for safety. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230726075257.12985-2-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-22mtd: spi-nor: spansion: return method directlyTudor Ambarus1-7/+1
Remove unnecessary handling of method's return code and return the method directly. Link: https://lore.kernel.org/r/20230721170911.13502-1-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-18mtd: spi-nor: rename method for enabling or disabling octal DTRTudor Ambarus4-13/+13
Having an *_enable(..., bool enable) definition was misleading as the method is used both to enable and to disable the octal DTR mode. Splitting the method in the core in two, one to enable and another to disable the octal DTR mode does not make sense as the method is straight forward and we'd introduce code duplication. Update the core to use: int (*set_octal_dtr)(struct spi_nor *nor, bool enable); Manufacturer drivers use different sequences of commands to enable and disable the octal DTR mode, thus for clarity they shall implement it as: static int manufacturer_snor_set_octal_dtr(struct spi_nor *nor, bool enable) { return enable ? manufacturer_snor_octal_dtr_enable() : manufacturer_snor_octal_dtr_disable(); } Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230714150757.15372-1-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-18mtd: spi-nor: Correct flags for Winbond w25q128Linus Walleij1-2/+3
The Winbond "w25q128" (actual vendor name W25Q128JV) has exactly the same flags as the sibling device "w25q128jv". The devices both require unlocking to enable write access. The actual product naming between devices vs the Linux strings in winbond.c: 0xef4018: "w25q128" W25Q128JV-IN/IQ/JQ 0xef7018: "w25q128jv" W25Q128JV-IM/JM The latter device, "w25q128jv" supports features named DTQ and QPI, otherwise it is the same. Not having the right flags has the annoying side effect that write access does not work. After this patch I can write to the flash on the Inteno XG6846 router. The flash memory also supports dual and quad SPI modes. This does not currently manifest, but by turning on SFDP parsing, the right SPI modes are emitted in /sys/kernel/debug/spi-nor/spi1.0/capabilities for this chip, so we also turn on this. Since we now have determined that SFDP parsing works on the device, we also detect the geometry using SFDP. After this dmesg and sysfs says: [ 1.062401] spi-nor spi1.0: w25q128 (16384 Kbytes) cat erasesize 65536 (16384*1024)/65536 = 256 sectors spi-nor sysfs: cat jedec_id ef4018 cat manufacturer winbond cat partname w25q128 hexdump -v -C sfdp 00000000 53 46 44 50 05 01 00 ff 00 05 01 10 80 00 00 ff 00000010 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000040 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000050 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000060 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000070 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000080 e5 20 f9 ff ff ff ff 07 44 eb 08 6b 08 3b 42 bb 00000090 fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52 000000a0 10 d8 00 00 36 02 a6 00 82 ea 14 c9 e9 63 76 33 000000b0 7a 75 7a 75 f7 a2 d5 5c 19 f7 4d ff e9 30 f8 80 Cc: stable@vger.kernel.org Suggested-by: Michael Walle <michael@walle.cc> Reviewed-by: Michael Walle <michael@walle.cc> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230718-spi-nor-winbond-w25q128-v5-1-a73653ee46c3@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-07-13mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connectedAmit Kumar Mahapatra4-2/+12
Setting the status register write disable (SRWD) bit in the status register (SR) with WP# signal of the flash left floating or wrongly tied to GND (that includes internal pull-downs), will configure the SR permanently as read-only. If WP# signal is left floating or wrongly tied to GND, avoid setting SRWD bit while writing the SR during flash protection. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230630142233.63585-3-amit.kumar-mahapatra@amd.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-05-26mtd: spi-nor: Fix divide by zero for spi-nor-generic flashesTudor Ambarus1-1/+4
We failed to initialize n_banks for spi-nor-generic flashes, which caused a devide by zero when computing the bank_size. By default we consider that all chips have a single bank. Initialize the default number of banks for spi-nor-generic flashes. Even if the bug is fixed with this simple initialization, check the n_banks value before dividing so that we make sure this kind of bug won't occur again if some other struct instance is created uninitialized. Suggested-by: Todd Brandt <todd.e.brandt@linux.intel.com> Reported-by: Todd Brandt <todd.e.brandt@linux.intel.com> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217448 Fixes: 9d6c5d64f028 ("mtd: spi-nor: Introduce the concept of bank") Link: https://lore.kernel.org/all/20230516225108.29194-1-todd.e.brandt@intel.com/ Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Tested-by: Todd Brandt <todd.e.brandt@linux.intel.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230518085440.2363676-1-tudor.ambarus@linaro.org
2023-05-26mtd: spi-nor: spansion: make sure local struct does not contain garbageTudor Ambarus1-2/+2
Following errors were seen with um-x86_64-gcc12/um-allyesconfig: + /kisskb/src/drivers/mtd/spi-nor/spansion.c: error: 'op' is used uninitialized [-Werror=uninitialized]: => 495:27, 364:27 Initialise local struct spi_mem_op with all zeros at declaration in order to avoid using garbage data for fields that are not explicitly set afterwards. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Fixes: c87c9b11c53ce ("mtd: spi-nor: spansion: Determine current address mode") Fixes: 6afcc84080c41 ("mtd: spi-nor: spansion: Add support for Infineon S25FS256T") Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230509193900.948753-1-tudor.ambarus@linaro.org
2023-04-26Merge tag 'mtd/for-6.4' of ↵Linus Torvalds14-156/+1070
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "Core MTD changes: - dt-bindings: Drop unneeded quotes - mtdblock: Tolerate corrected bit-flips - Use of_property_read_bool() for boolean properties - Avoid magic values - Avoid printing error messages on probe deferrals - Prepare mtd_otp_nvmem_add() to handle -EPROBE_DEFER - Fix error path for nvmem provider - Fix nvmem error reporting - Provide unique name for nvmem device MTD device changes: - lpddr_cmds: Remove unused words variable - bcm63xxpart: Remove MODULE_LICENSE in non-modules SPI NOR core changes: - Introduce Read While Write support for flashes featuring several banks - Set the 4-Byte Address Mode method based on SFDP data - Allow post_sfdp hook to return errors - Parse SCCR MC table and introduce support for multi-chip devices SPI NOR manufacturer drivers changes: - macronix: Add support for mx25uw51245g with RWW - spansion: - Determine current address mode at runtime as it can be changed in a non-volatile way and differ from factory defaults or from what SFDP advertises. - Enable JFFS2 write buffer mode for few ECC'd NOR flashes: S25FS256T, s25hx and s28hx - Add support for s25hl02gt and s25hs02gt Raw NAND core changes: - Convert to platform remove callback returning void - Fix spelling mistake waifunc() -> waitfunc() Raw NAND controller driver changes: - imx: Remove unused is_imx51_nfc and imx53_nfc functions - omap2: Drop obsolete dependency on COMPILE_TEST - orion: Use devm_platform_ioremap_resource() - qcom: - Use of_property_present() for testing DT property presence - Use devm_platform_get_and_ioremap_resource() - stm32_fmc2: Depends on ARCH_STM32 instead of MACH_STM32MP157 - tmio: Remove reference to config MTD_NAND_TMIO in the parsers Raw NAND manufacturer driver changes: - hynix: Fix up bit 0 of sdr_timing_mode SPI-NAND changes: - Add support for ESMT F50x1G41LB" * tag 'mtd/for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (55 commits) mtd: nand: Convert to platform remove callback returning void mtd: onenand: omap2: Drop obsolete dependency on COMPILE_TEST mtd: spi-nor: spansion: Add support for s25hl02gt and s25hs02gt mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip device mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() for multi-chip device support mtd: spi-nor: spansion: Rework cypress_nor_get_page_size() for multi-chip device support mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip device mtd: spi-nor: Extract volatile register offset from SCCR map mtd: spi-nor: Allow post_sfdp hook to return errors mtd: spi-nor: spansion: Rename method to cypress_nor_get_page_size mtd: spi-nor: spansion: Enable JFFS2 write buffer for S25FS256T mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx SEMPER flash mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash mtd: spi-nor: spansion: Determine current address mode mtd: spi-nor: core: Introduce spi_nor_set_4byte_addr_mode() mtd: spi-nor: core: Update flash's current address mode when changing address mode mtd: spi-nor: Stop exporting spi_nor_restore() mtd: spi-nor: Set the 4-Byte Address Mode method based on SFDP data mtd: spi-nor: core: Make spi_nor_set_4byte_addr_mode_brwr public mtd: spi-nor: core: Update name and description of spi_nor_set_4byte_addr_mode ...
2023-04-19Merge tag 'spi-nor/for-6.4' into mtd/nextMiquel Raynal13-154/+1068
SPI NOR core changes: * introduce Read While Write support for flashes featuring several banks * set the 4-Byte Address Mode method based on SFDP data * allow post_sfdp hook to return errors * parse SCCR MC table and introduce support for multi-chip devices SPI NOR manufacturer drivers changes: * macronix: add support for mx25uw51245g with RWW * spansion: - determine current address mode at runtime as it can be changed in a non-volatile way and differ from factory defaults or from what SFDP advertises. - enable JFFS2 write buffer mode for few ECC'd NOR flashes: S25FS256T, s25hx and s28hx - add support for s25hl02gt and s25hs02gt Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2023-04-08mtd: spi-nor: spansion: Add support for s25hl02gt and s25hs02gtTakahiro Kuwano1-0/+12
Add ID, flags, and fixup for s25hl02gt and s25hs02gt. These parts are - Dual-die package parts - Not support chip erase - 4-byte addressing mode by default - Wrong param in SCCR map that needs to be fixed Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/55021d2409bf310692db0ac1c55e71ba406438a7.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip deviceTakahiro Kuwano1-24/+85
For multi-chip devices, we need to make sure the all dice in the device are ready. The cypress_nor_sr_ready_and_clear() reads SR in each die and returns true only when all dice are ready. This function also takes care for program or erase error handling by reusing spansion_nor_clear_sr(). To do that, spansion_nor_clear_sr() is moved to top. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/3e4a64613ee733e002279349c75083433be45bf5.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() for ↵Takahiro Kuwano1-21/+39
multi-chip device support Rework quad method for multi-chip devices by updating CFR1V in all dice in the device. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/1b5606dbcc11b3432c306a75880f05c68e927fb9.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Rework cypress_nor_get_page_size() for multi-chip ↵Takahiro Kuwano1-20/+69
device support For multi-chip devices, we can use 512B page only when the all dice are configured as 512B page size. The volatile register address is calculated by using the volatile register addresses retrieved from the SCCR tables and the (configuration) register offset. The location of cypress_nor_set_page_size() call is moved from post_bfpt_fixup() to post_sfdp_fixup(), because the number of dice and volatile register offset are parsed in the optional SCCR tables. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/6f8272f3e877dee392742d2c8401c4aed57e6d83.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip deviceTakahiro Kuwano1-0/+66
SCCR map for multi-chip devices contains the number of additional dice in the device and register offset values for each additional dice. spi_nor_parse_sccr_mc() is added to determine the number of dice and volatile register offset for each die. The volatile register offset table may already be allocated and contains offset value for die-0 via SCCR map parse. So, we should use devm_krealloc() to expand the table with preserving die-0 offset. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/89c892d52f8cbddbd14373f6a02db496885ae4f1.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: Extract volatile register offset from SCCR mapTakahiro Kuwano2-0/+17
In use of multi-chip devices, we need to access registers in each die for configuration and status check. The number of dice in the device and volatile register offsets for each die are essential to iterate register access ops. The volatile register offset for the first die resides in the 1st DWORD of SCCR map. Allocate the table and copy the offset value. The table may be allocated when the SCCR map for multi-chip is parsed. Since we cannot assume SCCR parse is always in ahead of SCCR multi-chip, we need to check if the table is already allocated or not. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/e2cc39ad6e0e02dd8288c4def9bb201a3f564425.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: Allow post_sfdp hook to return errorsTudor Ambarus4-10/+25
Multi die flashes like s25hl02gt need to determine the page_size at run-time by querying a configuration register for each die. Since the number of dice is determined in an optional SFDP table, SCCR MC, the page size configuration must be done in the post_sfdp hook. Allow post_sfdp to return errors, as reading the configuration register might return errors. Link: https://lore.kernel.org/r/924ab710f128448ec62537cfbb377336e390043c.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Rename method to cypress_nor_get_page_sizeTudor Ambarus1-6/+5
The method queries SPINOR_REG_CYPRESS_CFR3V to determine the page size. Rename the method accordingly, s/set/get. Link: https://lore.kernel.org/r/cd3fb2cbc42a9576377ce4506eec72a58240805d.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Enable JFFS2 write buffer for S25FS256TTakahiro Kuwano1-7/+1
Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. Drop the comment as the same info is now specified in cypress_nor_ecc_init(). Fixes: 6afcc84080c4 ("mtd: spi-nor: spansion: Add support for Infineon S25FS256T") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/641bfb26c6e059915ae920117b7ec278df1a6f0a.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx SEMPER ↵Takahiro Kuwano1-5/+2
flash Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. Fixes: b6b23833fc42 ("mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/a1cc128e094db4ec141f85bd380127598dfef17e.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER ↵Takahiro Kuwano4-1/+17
flash Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. A new SNOR_F_ECC flag is introduced to determine if the part has on-die ECC and if it has, MTD_BIT_WRITEABLE is unset. In vendor specific driver, a common cypress_nor_ecc_init() helper is added. This helper takes care for ECC related initialization for SEMPER flash family by setting up params->writesize and SNOR_F_ECC. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/d586723f6f12aaff44fbcd7b51e674b47ed554ed.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: spansion: Determine current address modeTakahiro Kuwano1-3/+128
Internal address mode (3- or 4-byte) affects to the address length in Read Any Reg op. Read Any Reg op is used in SMPT parse and other setup functions. Current driver assumes that address mode is factory default but users can change it via volatile and non-volatile registers. Current address mode can be checked by CFR2V[7] but Read Any Reg op is needed to read CFR2V (chicken-and-egg). Introduce a way to determine current address mode by comparing status register 1 values read by different address length. Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230331074606.3559258-11-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: core: Introduce spi_nor_set_4byte_addr_mode()Tudor Ambarus2-5/+31
Make the method public, as it will be used as a last resort to enable 4byte address mode when we can't determine the address mode at runtime. Update the addr_nbytes and current address mode while exiting the 4byte address mode too, as it may be used in the future by manufacturer drivers. No functional change. spi_nor_restore didn't update the address mode nbytes, but updating them now doesn't harm as the method is called in the driver's remove and shutdown paths. Link: https://lore.kernel.org/r/20230331074606.3559258-10-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-24 16:56:54 +0300