summaryrefslogtreecommitdiff
path: root/drivers/mtd/spi-nor
AgeCommit message (Collapse)AuthorFilesLines
2023-09-19mtd: spi-nor: Correct flags for Winbond w25q128Linus Walleij1-2/+3
commit 83e824a4a595132f9bd7ac4f5afff857bfc5991e upstream. The Winbond "w25q128" (actual vendor name W25Q128JV) has exactly the same flags as the sibling device "w25q128jv". The devices both require unlocking to enable write access. The actual product naming between devices vs the Linux strings in winbond.c: 0xef4018: "w25q128" W25Q128JV-IN/IQ/JQ 0xef7018: "w25q128jv" W25Q128JV-IM/JM The latter device, "w25q128jv" supports features named DTQ and QPI, otherwise it is the same. Not having the right flags has the annoying side effect that write access does not work. After this patch I can write to the flash on the Inteno XG6846 router. The flash memory also supports dual and quad SPI modes. This does not currently manifest, but by turning on SFDP parsing, the right SPI modes are emitted in /sys/kernel/debug/spi-nor/spi1.0/capabilities for this chip, so we also turn on this. Since we now have determined that SFDP parsing works on the device, we also detect the geometry using SFDP. After this dmesg and sysfs says: [ 1.062401] spi-nor spi1.0: w25q128 (16384 Kbytes) cat erasesize 65536 (16384*1024)/65536 = 256 sectors spi-nor sysfs: cat jedec_id ef4018 cat manufacturer winbond cat partname w25q128 hexdump -v -C sfdp 00000000 53 46 44 50 05 01 00 ff 00 05 01 10 80 00 00 ff 00000010 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000040 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000050 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000060 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000070 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000080 e5 20 f9 ff ff ff ff 07 44 eb 08 6b 08 3b 42 bb 00000090 fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52 000000a0 10 d8 00 00 36 02 a6 00 82 ea 14 c9 e9 63 76 33 000000b0 7a 75 7a 75 f7 a2 d5 5c 19 f7 4d ff e9 30 f8 80 Cc: stable@vger.kernel.org Suggested-by: Michael Walle <michael@walle.cc> Reviewed-by: Michael Walle <michael@walle.cc> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230718-spi-nor-winbond-w25q128-v5-1-a73653ee46c3@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-09-13mtd: spi-nor: Check bus width while setting QE bitHsin-Yi Wang1-9/+10
[ Upstream commit f01d8155a92e33cdaa85d20bfbe6c441907b3c1f ] spi_nor_write_16bit_sr_and_check() should also check if bus width is 4 before setting QE bit. Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Suggested-by: Michael Walle <michael@walle.cc> Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230818064524.1229100-2-hsinyi@chromium.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-05-17mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx SEMPER ↵Takahiro Kuwano1-5/+2
flash [ Upstream commit 4199c1719e24e73be0acc8b0146fc31ad8af9771 ] Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. Fixes: b6b23833fc42 ("mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/a1cc128e094db4ec141f85bd380127598dfef17e.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-05-17mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER ↵Takahiro Kuwano4-1/+17
flash [ Upstream commit 9fd0945fe6fadfb6b54a9cd73be101c02b3e8134 ] Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. A new SNOR_F_ECC flag is introduced to determine if the part has on-die ECC and if it has, MTD_BIT_WRITEABLE is unset. In vendor specific driver, a common cypress_nor_ecc_init() helper is added. This helper takes care for ECC related initialization for SEMPER flash family by setting up params->writesize and SNOR_F_ECC. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/d586723f6f12aaff44fbcd7b51e674b47ed554ed.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-05-17mtd: spi-nor: Add a RWW flagMiquel Raynal3-0/+7
[ Upstream commit 4eddee70140b3ae183398b246a609756546c51f1 ] Introduce a new (no SFDP) flag for the feature that we are about to support: Read While Write. This means, if the chip has several banks and supports RWW, once a page of data to write has been transferred into the chip's internal SRAM, another read operation happening on a different bank can be performed during the tPROG delay. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-7-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Stable-dep-of: 9fd0945fe6fa ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash") Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-05-17mtd: spi-nor: add SFDP fixups for Quad Page ProgramSudip Mukherjee3-0/+9
[ Upstream commit 1799cd8540b67b88514c82f5fae1c75b986bcbd8 ] SFDP table of some flash chips do not advertise support of Quad Input Page Program even though it has support. Use flags and add hardware cap for these chips. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com> [tudor.ambarus@microchip.com: move pp setting in spi_nor_init_default_params] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220920184808.44876-2-sudip.mukherjee@sifive.com Stable-dep-of: 9fd0945fe6fa ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash") Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-05-17mtd: spi-nor: spansion: Remove NO_SFDP_FLAGS from s28hs512t infoTakahiro Kuwano1-9/+8
[ Upstream commit db391efe765cc6cfc0ffc8d8ef146dc8e6816a7e ] Read, Page Program, and Sector Erase settings are done in SFDP so we can remove NO_SFDP_FLAGS from s28hs512t info. Since the default_init() is no longer called after removing NO_SFDP_FLAGS, the initialization in the default_init() is moved to late_init(). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/12e468992f5d0cbd474abff3203100cc8163d4e5.1661915569.git.Takahiro.Kuwano@infineon.com Stable-dep-of: 9fd0945fe6fa ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash") Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-05-11mtd: spi-nor: core: Update flash's current address mode when changing ↵Tudor Ambarus1-1/+3
address mode commit 37513c56139b79dd43c1774513c28f8ab2b05224 upstream. The bug was obswerved while reading code. There are not many users of addr_mode_nbytes. Anyway, we should update the flash's current address mode when changing the address mode, fix it. We don't care for now about the set_4byte_addr_mode(nor, false) from spi_nor_restore(), as it is used at driver remove and shutdown. Fixes: d7931a215063 ("mtd: spi-nor: core: Track flash's internal address mode") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230331074606.3559258-9-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-04-26mtd: spi-nor: fix memory leak when using debugfs_lookup()Greg Kroah-Hartman3-4/+23
[ Upstream commit ec738ca127d07ecac6afae36e2880341ec89150e ] When calling debugfs_lookup() the result must have dput() called on it, otherwise the memory will leak over time. To solve this, remove the lookup and create the directory on the first device found, and then remove it when the module is unloaded. Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: Pratyush Yadav <pratyush@kernel.org> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230208160230.2179905-1-gregkh@linuxfoundation.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-03-10mtd: spi-nor: Fix shift-out-of-bounds in spi_nor_set_erase_typeLouis Rannou3-2/+12
commit f0f0cfdc3a024e21161714f2e05f0df3b84d42ad upstream. spi_nor_set_erase_type() was used either to set or to mask out an erase type. When we used it to mask out an erase type a shift-out-of-bounds was hit: UBSAN: shift-out-of-bounds in drivers/mtd/spi-nor/core.c:2237:24 shift exponent 4294967295 is too large for 32-bit type 'int' The setting of the size_{shift, mask} and of the opcode are unnecessary when the erase size is zero, as throughout the code just the erase size is considered to determine whether an erase type is supported or not. Setting the opcode to 0xFF was wrong too as nobody guarantees that 0xFF is an unused opcode. Thus when masking out an erase type, just set the erase size to zero. This will fix the shift-out-of-bounds. Fixes: 5390a8df769e ("mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories") Cc: stable@vger.kernel.org Reported-by: Alexander Stein <Alexander.Stein@tq-group.com> Signed-off-by: Louis Rannou <lrannou@baylibre.com> Tested-by: Alexander Stein <Alexander.Stein@tq-group.com> Link: https://lore.kernel.org/r/20230203070754.50677-1-tudor.ambarus@linaro.org [ta: refine changes, new commit message, fix compilation error] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-03-10mtd: spi-nor: spansion: Consider reserved bits in CFR5 registerTudor Ambarus1-2/+7
commit 3f592a869f87723314f0cb1ac232bd3bf8245be8 upstream. CFR5[6] is reserved bit and must be always 1. Set it to comply with flash requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_{EN, DS} definition, stop using magic numbers and describe the missing bit fields in CFR5 register. This is useful for both readability and future possible addition of Octal STR mode support. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Cc: stable@vger.kernel.org Reported-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Pratyush Yadav <ptyadav@amazon.de> Tested-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/linux-mtd/20230110164703.83413-1-tudor.ambarus@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-03-10mtd: spi-nor: sfdp: Fix index value for SCCR dwordsTakahiro Kuwano1-1/+1
commit ad9679f3811899fd1c21dc7bdd715e8e1cfb46b9 upstream. Array index for SCCR 22th DOWRD should be 21. Fixes: 981a8d60e01f ("mtd: spi-nor: Parse SFDP SCCR Map") Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Michael Walle <michael@walle.cc> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/d8a2a77c2c95cf776e7dcae6392d29fdcf5d6307.1672026365.git.Takahiro.Kuwano@infineon.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-01-18mtd: cfi: allow building spi-intel standaloneArnd Bergmann1-0/+1
[ Upstream commit d19ab1f785d0b6b9f709799f0938658903821ba1 ] When MTD or MTD_CFI_GEOMETRY is disabled, the spi-intel driver fails to build, as it includes the shared CFI header: include/linux/mtd/cfi.h:62:2: error: #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work. [-Werror=cpp] 62 | #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work. linux/mtd/spi-nor.h does not actually need to include cfi.h, so remove the inclusion here to fix the warning. This uncovers a missing #include in spi-nor/core.c so add that there to prevent a different build issue. Fixes: e23e5a05d1fd ("mtd: spi-nor: intel-spi: Convert to SPI MEM") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Tokunori Ikegami <ikegami.t@gmail.com> Acked-by: Pratyush Yadav <pratyush@kernel.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20221220141352.1486360-1-arnd@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-01-07mtd: spi-nor: gigadevice: gd25q256: replace gd25q256_default_init with ↵Yaliang Wang1-7/+17
gd25q256_post_bfpt commit 4dc49062a7e9c0c7261807fb855df1c611eb78c3 upstream. When utilizing PARSE_SFDP to initialize the flash parameter, the deprecated initializing method spi_nor_init_params_deprecated() and the function spi_nor_manufacturer_init_params() within it will never be executed, which results in the default_init hook function will also never be executed. This is okay for 'D' generation of GD25Q256, because 'D' generation is implementing the JESD216B standards, it has QER field defined in BFPT, parsing the SFDP can properly set the quad_enable function. The 'E' generation also implements the JESD216B standards, and it has the same status register definitions as 'D' generation, parsing the SFDP to set the quad_enable function should also work for 'E' generation. However, the same thing can't apply to 'C' generation. 'C' generation 'GD25Q256C' implements the JESD216 standards, and it doesn't have the QER field defined in BFPT, since it does have QE bit in status register 1, the quad_enable hook needs to be tweaked to properly set the quad_enable function, this can be done in post_bfpt fixup hook. Fixes: 047275f7de18 ("mtd: spi-nor: gigadevice: gd25q256: Init flash based on SFDP") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Yaliang Wang <Yaliang.Wang@windriver.com> [tudor.ambarus@microchip.com: Update comment in gd25q256_post_bfpt] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20221016171901.1483542-2-yaliang.wang@windriver.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-01-07mtd: spi-nor: Check for zero erase size in spi_nor_find_best_erase_type()Alexander Sverdlin1-0/+2
commit 2ebc336be08160debfe27f87660cf550d710f3e9 upstream. Erase can be zeroed in spi_nor_parse_4bait() or spi_nor_init_non_uniform_erase_map(). In practice it happened with mt25qu256a, which supports 4K, 32K, 64K erases with 3b address commands, but only 4K and 64K erase with 4b address commands. Fixes: dc92843159a7 ("mtd: spi-nor: fix erase_type array to indicate current map conf") Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20211119081412.29732-1-alexander.sverdlin@nokia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-12-31mtd: spi-nor: Fix the number of bytes for the dummy cyclesAllen-KH Cheng1-1/+2
[ Upstream commit fdc20370d93e8c6d2f448a539d08c2c064af7694 ] The number of bytes used by spi_nor_spimem_check_readop() may be incorrect for the dummy cycles. Since nor->read_dummy is not initialized before spi_nor_spimem_adjust_hwcaps(). We use both mode and wait state clock cycles instead of nor->read_dummy. Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol") Co-developed-by: Bayi Cheng <bayi.cheng@mediatek.com> Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Dhruva Gole <d-gole@ti.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20221031124633.13189-1-allen-kh.cheng@mediatek.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31mtd: spi-nor: hide jedec_id sysfs attribute if not presentMichael Walle1-0/+14
[ Upstream commit 7d388551b6888f3725e6c957f472526b35161a5b ] Some non-jedec compliant flashes (like the Everspin flashes) don't have an ID at all. Hide the attribute in this case. Fixes: 36ac02286265 ("mtd: spi-nor: add initial sysfs support") Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20220810220654.1297699-2-michael@walle.cc Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-10-18mtd: spi-nor: core: Ignore -ENOTSUPP in spi_nor_init()Mika Westerberg1-1/+3
The Intel SPI-NOR controller does not support the 4-byte address opcode so ->set_4byte_addr_mode() ends up returning -ENOTSUPP and the SPI flash chip probe fail like this: [ 12.291082] spi-nor: probe of spi0.0 failed with error -524 Whereas previously before commit 08412e72afba ("mtd: spi-nor: core: Return error code from set_4byte_addr_mode()") it worked just fine. Fix this by ignoring -ENOTSUPP in spi_nor_init(). Fixes: 08412e72afba ("mtd: spi-nor: core: Return error code from set_4byte_addr_mode()") Cc: stable@vger.kernel.org Reported-by: Hongyu Ning <hongyu.ning@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Michael Walle <michael@walle.cc> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20220923093441.3178-1-mika.westerberg@linux.intel.com
2022-07-28mtd: spi-nor: fix spi_nor_spimem_setup_op() call in ↵Patrice Chotard1-3/+3
spi_nor_erase_{sector,chip}() For erase operations, reg_proto must be used as indicated in struct spi_nor description in spi-nor.h. This issue was found when DT property spi-tx-bus-width is set to 4. In this case the spi_mem_op->addr.buswidth is set to 4 for erase command which is not correct. Tested on stm32mp157c-ev1 board with mx66l51235f spi-nor. Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> [ta: use nor->reg_proto in spi_nor_controller_ops_erase()] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220629133013.3382393-1-patrice.chotard@foss.st.com
2022-07-28mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixupsTakahiro Kuwano1-0/+132
The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI. These Infineon chips support volatile version of configuration registers and it is recommended to update volatile registers in the field application due to a risk of the non-volatile registers corruption by power interrupt. Add support for volatile QE bit. For the single-die package parts (512Mb and 1Gb), only bottom 4KB and uniform sector sizes are supported. This is due to missing or incorrect entries in SMPT. Fixup for other sector sizes configurations will be followed up as needed. Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220725092505.446315-8-tudor.ambarus@microchip.com
2022-07-28mtd: spi-nor: spansion: Add local function to discover page sizeTakahiro Kuwano1-22/+31
The page size check in s28hs512t fixup can be used for s25hs/hl-t as well. Move that to a newly created local function. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220725092505.446315-7-tudor.ambarus@microchip.com
2022-07-28mtd: spi-nor: core: Track flash's internal address modeTudor Ambarus2-1/+8
We need to track the flash's internal address mode as there are flashes that can operate with 4B opcodes but unfortunately do not have a 4B opcode correspondent for all the 3B opcodes. Such an example is the Infineon Semper chips which provide 4B opcodes for read/program/erase but do not provide 4B opcodes for Read/Write Any Register. These registers are indexed by address and require the internal address mode of the flash before Read/Write Any Register opcodes are issued. 4B opcodes are preferred over changing the flash's address mode to 4byte, as set_4byte_addr_mode could be done in a non-volatile way and could break the boot sequence. Thus we need to track the flash's internal address mode so that we can use 4B opcodes together with opcodes that don't have a 4B opcode correspondent. Track flash's internal address mode. addr_mode_nbytes is discovered when parsing BFPT. For the BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 case, one could introduce a method that queries the flash's internal address mode at run-time (works for Winbond). If a run-time querying can not be accomplished or if SFDP is not defined at all, but the address mode is volatile and resets to a default known value at boot, one can change the default addr_mode_nbytes value of 3 by introducing a flash_info flag. If the address mode can not be queried, discovered and it is configured via a non-volatile register, we may introduce a dt property, but it will harm the generic approach of the jedec,spi-nor compatible. All this complexity is not needed now, so let it for future development. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220725092505.446315-6-tudor.ambarus@microchip.com
2022-07-28mtd: spi-nor: core: Return error code from set_4byte_addr_mode()Takahiro Kuwano1-1/+1
The prams->set_4byte_addr_mode returns error code but is not handled in spi_nor_init(). Handle the return code from set_4byte_addr_mode(). Suggested-by: Michael Walle <michael@walle.cc> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220725092505.446315-5-tudor.ambarus@microchip.com
2022-07-28mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing timeTudor Ambarus4-8/+9
At the SFDP parsing time we should not change members of struct spi_nor, but instead fill members of struct spi_nor_flash_parameters which could later on be used by callers. The caller will then decide if SFDP params should be used and more importantly when they should be used. Clean the code flow and don't initialize nor->addr_nbytes at SFDP parsing time. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-4-tudor.ambarus@microchip.com
2022-07-28mtd: spi-nor: core: Shrink the storage size of the flash_info's addr_nbytesTudor Ambarus1-1/+1
The maximum number of address bytes in SPI NOR is 4. Shrink the storage size of the flash_info's addr_nbytes. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-3-tudor.ambarus@microchip.com
2022-07-28mtd: spi-nor: s/addr_width/addr_nbytesTudor Ambarus9-66/+66
Address width was an unfortunate name, as it means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. s/addr_width/addr_nbytes throughout the entire SPI NOR framework. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220725092505.446315-2-tudor.ambarus@microchip.com
2022-07-19mtd: spi-nor: esmt: Use correct name of f25l32qaSungbo Eo1-1/+1
The flash ID of F25L32QA is 0x8c4016, whereas that of F25L32QA(2S) is 0x8c4116. F25L32QA(2S) is the newer version of F25L32QA and its BPn bits are non-volatile, unlike its older version. Signed-off-by: Sungbo Eo <mans0n@gorani.run> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20210723141232.15659-1-mans0n@gorani.run Datasheet: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F25L32QA.pdf Datasheet: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F25L32QA_1(2S).pdf
2022-07-19mtd: spi-nor: micron-st: Skip FSR reading if SPI controller does not support itMika Westerberg1-2/+10
The Intel SPI controller does not support low level operations, like reading the flag status register (FSR). It only exposes a set of high level operations for software to use. For this reason check the return value of micron_st_nor_read_fsr() and if the operation was not supported, use the status register value only. This allows the chip to work even when attached to Intel SPI controller (there are such systems out there). Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220506105158.43613-1-mika.westerberg@linux.intel.com
2022-06-27mtd: spi-nor: move SECT_4K_PMC special handlingMichael Walle3-10/+22
The SECT_4K_PMC flag will set a device specific opcode for the 4k sector erase. Instead of handling it in the core, we can move it to a late_init(). In that late init, loop over all erase types, look for the 4k size and replace the opcode. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220418112650.2791459-1-michael@walle.cc
2022-05-25Merge tag 'spi-v5.19' of ↵Linus Torvalds3-932/+0
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "This is quite a quiet release but some new drivers mean that the diffstat is fairly large. The new drivers include the aspeed driver which is migrated from MTD as part of the ongoing move of controllers with specialised support for SPI flashes into the SPI subsystem. - Support for devices which flip CPHA during recieve only transfers (eg, if MOSI and MISO have inverted polarity). - Overhaul of the i.MX driver, including the addition of PIO support for better performance on small transfers. - Migration of the Aspeed driver from MTD. - Support for Aspeed AST2400, Ingenic JZ4775 and X1/2000 and MediaTek IPM and SFI" * tag 'spi-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (84 commits) spi: spi-au1550: replace ternary operator with min() mtd: spi-nor: aspeed: set the decoding size to at least 2MB for AST2600 spi: aspeed: Calibrate read timings spi: aspeed: Add support for the AST2400 SPI controller spi: aspeed: Workaround AST2500 limitations spi: aspeed: Adjust direct mapping to device size spi: aspeed: Add support for direct mapping spi: spi-mem: Convert Aspeed SMC driver to spi-mem spi: Convert the Aspeed SMC controllers device tree binding spi: spi-cadence: Update ISR status variable type to irqreturn_t spi: Doc fix - Describe add_lock and dma_map_dev in spi_controller spi: cadence-quadspi: Handle spi_unregister_master() in remove() spi: stm32-qspi: Remove SR_BUSY bit check before sending command spi: stm32-qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd() spi: stm32-qspi: Fix wait_cmd timeout in APM mode spi: cadence-quadspi: remove unnecessary (void *) casts spi: cadence-quadspi: Add missing blank line in cqspi_request_mmap_dma() spi: spi-imx: mx51_ecspi_prepare_message(): skip writing MX51_ECSPI_CONFIG register if unchanged spi: spi-imx: add PIO polling support spi: spi-imx: replace struct spi_imx_data::bitbang by pointer to struct spi_controller ...
2022-05-16spi: spi-mem: Convert Aspeed SMC driver to spi-memCédric Le Goater3-932/+0
This SPI driver adds support for the Aspeed static memory controllers of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface. * AST2600 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . Only supports SPI type flash memory . different segment register interface . single, dual and quad mode. * AST2600 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . different segment register interface . single, dual and quad mode. * AST2500 Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver . single, dual mode. * AST2500 SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . single, dual mode. * AST2400 New Static Memory Controller (also referred as FMC) . BMC firmware . New register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. . single, dual and quad mode. Each controller has a memory range on which flash devices contents are mapped. Each device is assigned a window that can be changed at bootime with the Segment Address Registers. Each SPI flash device can then be accessed in two modes: Command and User. When in User mode, SPI transfers are initiated with accesses to the memory segment of a device. When in Command mode, memory operations on the memory segment of a device generate SPI commands automatically using a Control Register for the settings. This initial patch adds support for User mode. Command mode needs a little more work to check that the memory window on the AHB bus fits the device size. It will come later when support for direct mapping is added. Single and dual mode RX transfers are supported. Other types than SPI are not supported. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-4-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-12mtd: spi-nor: debugfs: fix format specifierMichael Walle1-1/+1
The intention was to print the JEDEC ID in the following format: nn nn nn In this case format specifier has to be "%*ph". Fix it. Fixes: 0257be79fc4a ("mtd: spi-nor: expose internal parameters via debugfs") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220512112027.3771734-1-michael@walle.cc
2022-05-09mtd: spi-nor: support eon en25qh256a variantLeon M. George1-1/+2
This patch allows accessing the upper 16m on the A variant (EN25QH256A) of the EN25QH256 that shares same JEDEC ID. Without this patch, addr_with is detected to be '4' but the read_opcode is a plain READ (supporting only 3 byte addresses). Setting PARSE_SFDP is enough to detect the read_opcode READ_4B on the A variant. READ_4B is not available on the no-A variant. Both variants support 4-byte address mode (spi_nor_set_4byte_addr_mode) but that is prone to breaking on unexpected reboots if the reset pin isn't connected (broken-flash-reset). The no-A variant supports a 'high bank latch mode' that affects read, program, and erase commands - similar to the extended address register (EAR). The HBL bit is manipulated using the ENHBL (0x67) and EXHBL (0x98) opcodes. Should it become necessary to distinguish the two variants in the future, the A variant sets the SNOR_HWCAPS_READ_1_1_4 SFDP param - the no-A variant doesn't. Tested with and without fast read on the A variant only. Signed-off-by: Leon M. George <leon@georgemail.eu> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220502233310.791565-2-leon@georgemail.eu
2022-05-09mtd: spi-nor: winbond: add support for W25Q512NW-IMShaik Sajida Bhanu1-0/+3
Add support for winbond W25Q512NW-IM chip. Below are the tests done: 1. Verified flashing binary image on spi card using flashrom tool. 2. Verified OTP support, below are the test results: localhost / # cat /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/spi16/ spi16.0/spi-nor/jedec_id ef8020 localhost / # cat /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/spi16/ spi16.0/spi-nor/manufacturer winbond localhost / # cat /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/spi16/ spi16.0/spi-nor/partname w25q512nwm localhost / # hexdump /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/sp i16/spi16.0/spi-nor/sfdp 0000000 4653 5044 0106 ff01 0600 1001 0080 ff00 0000010 0084 0201 00d0 ff00 ffff ffff ffff ffff 0000020 6800 6c65 6f6c 7720 726f 646c ffff ffff 0000030 ffff ffff ffff ffff ffff ffff ffff ffff * 0000080 20e5 fffb ffff 1fff eb44 6b08 3b08 bb42 0000090 fffe ffff ffff 0000 ffff eb40 200c 520f 00000a0 d810 0000 0233 00a6 e781 d914 63e9 3376 00000b0 757a 757a bdf7 5cd5 f719 ff5d 70e9 a5f9 00000c0 ffff ffff ffff ffff ffff ffff ffff ffff 00000d0 0aff fff0 ff21 ffdc 00000d8 localhost / # md5sum /sys/bus/platform/devices/soc\@0/88dc000.spi/spi_master/spi 16/spi16.0/spi-nor/sfdp 106d89d6c049110bc94c01517cb4ce24 /sys/bus/platform/devices/soc@0/88dc000.spi/ spi_master/spi16/spi16.0/spi-nor/sfdp Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/1651234239-32217-1-git-send-email-quic_c_sbhanu@quicinc.com
2022-05-09mtd: spi-nor: expose internal parameters via debugfsMichael Walle4-0/+259
There is no way to gather all information to verify support for a new flash chip. Also if you want to convert an existing flash chip to the new SFDP parsing, there is not enough information to determine if the flash will work like before. To ease this development, expose internal parameters via the debugfs. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429102018.2361038-2-michael@walle.cc
2022-05-09mtd: spi-nor: export spi_nor_hwcaps_pp2cmd()Michael Walle2-1/+2
The function will also be used by the debugfs module. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429102018.2361038-1-michael@walle.cc
2022-05-02mtd: spi-nor: move spi_nor_write_ear() to winbond moduleMichael Walle3-38/+41
The "Extended Address Register" is winbond specific. If the flash is larger than 16MiB and is used in 3 byte address mode, it is used to set the remaining address bits. Move the write_ear() function, the opcode macros and the spimem op template into the winbond module and rename them accordingly. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220429100153.2338501-1-michael@walle.cc
2022-04-29mtd: spi-nor: amend the rdsr dummy cycles documentationMichael Walle1-2/+3
The rdsr dummy cycles are only used by the 8d-8d-8d mode. Mention that in the documentation. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220418112837.2792242-1-michael@walle.cc
2022-04-27mtd: spi-nor: micron-st: Remove status polling on volatile registers writeTudor Ambarus1-3/+0
Writing volatile registers are instant according to Micron and do not need any status polling. Remove status polling on volatile registers write. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-12-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: spansion: Remove status polling on volatile registers writeTudor Ambarus1-4/+0
Writing volatile registers are instant according to Cypress and do not need any status polling. Remove status polling on volatile registers write. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-11-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: Introduce templates for SPI NOR operationsTudor Ambarus5-107/+158
Clean the op declaration and hide the details of each op. With this it results a cleanner, easier to read code. No functional change expected. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Michael Walle <michael@walle.cc> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220420103427.47867-10-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: spansion: Rework spi_nor_cypress_octal_dtr_enable()Tudor Ambarus1-59/+69
Introduce template operation to remove code duplication. Split spi_nor_cypress_octal_dtr_enable() in spi_nor_cypress_octal_dtr_ena() spi_nor_cypress_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to read. Add debug messages in case spi_nor_read_id() fails. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-9-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable()Tudor Ambarus1-51/+60
Introduce template operation to remove code duplication. Split spi_nor_micron_octal_dtr_enable() in spi_nor_micron_octal_dtr_en() and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to follow. Add dev_dbg messages in case spi_nor_read_id() fails. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-8-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: core: Add helpers to read/write any registerTudor Ambarus2-0/+50
There are manufacturers that use registers indexed by address. Some of them support "read/write any register" opcodes. Provide core methods that can be used by all manufacturers. SPI NOR controller ops are intentionally not supported as we intend to move all the SPI NOR controller drivers under the SPI subsystem. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-7-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: manufacturers: Use spi_nor_read_id() core methodTudor Ambarus2-20/+6
Use spi_nor_read_id() core method to avoid duplication of code. Now the ID is read on the full SPI_NOR_MAX_ID_LEN instead of round_up(nor->info->id_len, 2), but it doesn't harm to read more ID bytes, so the change comes with no secondary effects. dev_dbg messages in case spi_nor_read_id() fails, will be added in a further patch after we split the octal DTR enable/disable methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-6-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: core: Introduce method for RDID opTudor Ambarus2-15/+44
RDID is used in the core to auto detect the flash, but also by some manufacturer drivers that contain flashes that support Octal DTR mode, so that they can read the flash ID after the switch to Octal DTR was made to test if the switch was successful. Introduce a core method for RDID op to avoid code duplication. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-5-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: core: Use auto-detection only onceTudor Ambarus1-3/+1
In case spi_nor_match_name() returned NULL, the auto detection was issued twice. There's no reason to try to detect the same chip twice, do the auto detection only once. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-4-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: Introduce spi_nor_match_id()Tudor Ambarus1-21/+19
Similar to spi_nor_match_name() extend the search of flash_info through all the manufacturers, this time doing the match by ID. There's no reason to limit the search per manufacturer yet, do it globally, search the flash in all the parts of all manufacturers in a single method. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-3-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: Rename method, s/spi_nor_match_id/spi_nor_match_nameTudor Ambarus1-3/+3
The method is matching a flash_info entry by searching by name. Rename the method for better clarity. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-2-tudor.ambarus@microchip.com
2022-04-27mtd: spi-nor: core: Check written SR value in spi_nor_write_16bit_sr_and_check()Chen-Tsung Hsieh1-0/+9
Read back Status Register 1 to ensure that the written byte match the received value and return -EIO if read back test failed. Without this patch, spi_nor_write_16bit_sr_and_check() only check the second half of the 16bit. It causes errors like spi_nor_sr_unlock() return success incorrectly when spi_nor_write_16bit_sr_and_check() doesn't write SR successfully. Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220126073227.3401275-1-chentsung@chromium.org