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2014-01-03mtd: gpmi: Use devm_clk_get()Fabio Estevam1-19/+2
Using devm_clk_get() can make the code smaller and cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-01-03mtd: gpmi: add a new DT property to use the datasheet's minimum required ECCHuang Shijie1-0/+3
In default way, we use the ecc_strength/ecc_step size calculated by ourselves and use all the OOB area. This patch adds a new property : "fsl,use-minimum-ecc" If we enable it, we will firstly try to use the datasheet's minimum required ECC provided by the MTD layer (the ecc_strength_ds/ecc_step_ds fields in the nand_chip{}). So we may have free space in the OOB area by using the minimum ECC, and we may support JFFS2 with some SLC NANDs, such as Micron's SLC NAND. If we fail to use the minimum ECC, we will use the legacy method to calculate the ecc_strength and ecc_step size. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-11-12mtd: gpmi: fix the NULL pointerHuang Shijie1-7/+7
The imx23 board will check the fingerprint, so it will call the mx23_check_transcription_stamp. This function will use @chip->buffers->databuf as its buffer which is allocated in the nand_scan_tail(). Unfortunately, the mx23_check_transcription_stamp is called before the nand_scan_tail(). So we will meet a NULL pointer bug: -------------------------------------------------------------------- [ 1.150000] NAND device: Manufacturer ID: 0xec, Chip ID: 0xd7 (Samsung NAND 4GiB 3,3V 8-bit), 4096MiB, page size: 4096, OOB size: 8 [ 1.160000] Unable to handle kernel NULL pointer dereference at virtual address 000005d0 [ 1.170000] pgd = c0004000 [ 1.170000] [000005d0] *pgd=00000000 [ 1.180000] Internal error: Oops: 5 [#1] ARM [ 1.180000] Modules linked in: [ 1.180000] CPU: 0 PID: 1 Comm: swapper Not tainted 3.12.0 #89 [ 1.180000] task: c7440000 ti: c743a000 task.ti: c743a000 [ 1.180000] PC is at memcmp+0x10/0x54 [ 1.180000] LR is at gpmi_nand_probe+0x42c/0x894 [ 1.180000] pc : [<c025fcb0>] lr : [<c02f6a68>] psr: 20000053 [ 1.180000] sp : c743be2c ip : 600000d3 fp : ffffffff [ 1.180000] r10: 000005d0 r9 : c02f5f08 r8 : 00000000 [ 1.180000] r7 : c75858a8 r6 : c75858a8 r5 : c7585b18 r4 : c7585800 [ 1.180000] r3 : 000005d0 r2 : 00000004 r1 : c05c33e4 r0 : 000005d0 [ 1.180000] Flags: nzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment kernel [ 1.180000] Control: 0005317f Table: 40004000 DAC: 00000017 [ 1.180000] Process swapper (pid: 1, stack limit = 0xc743a1c0) -------------------------------------------------------------------- This patch rearrange the init procedure: Set the NAND_SKIP_BBTSCAN to skip the nand scan firstly, and after we set the proper settings, we will call the chip->scan_bbt() manually. Cc: stable@vger.kernel.org # 3.12 Signed-off-by: Huang Shijie <b32955@freescale.com> Reported-by: Fabio Estevam <festevam@gmail.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-11-11mtd: gpmi: fix kernel BUG due to racing DMA operationsHuang Shijie1-2/+2
[1] The gpmi uses the nand_command_lp to issue the commands to NAND chips. The gpmi issues a DMA operation with gpmi_cmd_ctrl when it handles a NAND_CMD_NONE control command. So when we read a page(NAND_CMD_READ0) from the NAND, we may send two DMA operations back-to-back. If we do not serialize the two DMA operations, we will meet a bug when 1.1) we enable CONFIG_DMA_API_DEBUG, CONFIG_DMADEVICES_DEBUG, and CONFIG_DEBUG_SG. 1.2) Use the following commands in an UART console and a SSH console: cmd 1: while true;do dd if=/dev/mtd0 of=/dev/null;done cmd 1: while true;do dd if=/dev/mmcblk0 of=/dev/null;done The kernel log shows below: ----------------------------------------------------------------- kernel BUG at lib/scatterlist.c:28! Unable to handle kernel NULL pointer dereference at virtual address 00000000 ......................... [<80044a0c>] (__bug+0x18/0x24) from [<80249b74>] (sg_next+0x48/0x4c) [<80249b74>] (sg_next+0x48/0x4c) from [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4) [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4) from [<8004af58>] (dma_unmap_sg+0x14/0x6c) [<8004af58>] (dma_unmap_sg+0x14/0x6c) from [<8027e594>] (mxs_dma_tasklet+0x18/0x1c) [<8027e594>] (mxs_dma_tasklet+0x18/0x1c) from [<8007d444>] (tasklet_action+0x114/0x164) ----------------------------------------------------------------- 1.3) Assume the two DMA operations is X (first) and Y (second). The root cause of the bug: Assume process P issues DMA X, and sleep on the completion @this->dma_done. X's tasklet callback is dma_irq_callback. It firstly wake up the process sleeping on the completion @this->dma_done, and then trid to unmap the scatterlist S. The waked process P will issue Y in another ARM core. Y initializes S->sg_magic to zero with sg_init_one(), while dma_irq_callback is unmapping S at the same time. See the diagram: ARM core 0 | ARM core 1 ------------------------------------------------------------- (P issues DMA X, then sleep) --> | | (X's tasklet wakes P) --> | | | <-- (P begin to issue DMA Y) | (X's tasklet unmap the | scatterlist S with dma_unmap_sg) --> | <-- (Y calls sg_init_one() to init | scatterlist S) | [2] This patch serialize both the X and Y in the following way: Unmap the DMA scatterlist S firstly, and wake up the process at the end of the DMA callback, in such a way, Y will be executed after X. After this patch: ARM core 0 | ARM core 1 ------------------------------------------------------------- (P issues DMA X, then sleep) --> | | (X's tasklet unmap the | scatterlist S with dma_unmap_sg) --> | | (X's tasklet wakes P) --> | | | <-- (P begin to issue DMA Y) | | <-- (Y calls sg_init_one() to init | scatterlist S) | Cc: stable@vger.kernel.org # 3.2 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-11-11mtd: gpmi: only scan two chips for imx6Huang Shijie1-1/+1
We cannot scan two chips for imx23 and imx28: imx23: the Ready-Busy1 line is not connected for some board. imx28: we do not set the pinctrl for Ready-Busy1 So we only scan two chips for imx6. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-11-07mtd: gpmi: Use devm_kzalloc()Fabio Estevam1-3/+1
Using devm_kzalloc() can make the code simpler. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-11-07mtd: gpmi: scan two nand chipsHuang Shijie1-1/+1
Some nand chip has two DIEs in a single chip, such as Micron MT29F32G08QAA. Each die has its own chip select pin, so this chip acts as two nand chips. If we only scan one chip, we may find that we only get 2G for this chip, but in actually, this chip's size is 4G. So scan two chips by default. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-11-07mtd: gpmi: use DMA channel 0 for all the nand chipsHuang Shijie1-3/+2
We only have one DMA channel : the channel 0. Use DMA channel 0 to access all the nand chips. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-10-28mtd: gpmi: rewrite the gpmi_ecc_write_oob() to support the jffs2Huang Shijie1-9/+20
When we use the ECC info which is get from the nand chip's datasheet, we may have some freed oob area now. This patch rewrites the gpmi_ecc_write_oob() to implement the ecc.write_oob(). We also update the comment for gpmi_hw_ecclayout. Yes! We can support the JFFS2 for the SLC nand now. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2013-10-28mtd: nand: gpmi-nand: janitorial cleanup: (commas after last element of ↵Lothar Waßmann1-4/+4
struct initializer) Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2013-10-25mtd: gpmi: fix ECC regressionDavid Woodhouse1-1/+1
The "legacy" ECC layout used until 3.12-rc1 uses all the OOB area by computing the ECC strength and ECC step size ourselves. Commit 2febcdf84b ("mtd: gpmi: set the BCHs geometry with the ecc info") makes the driver use the ECC info (ECC strength and ECC step size) provided by the MTD code, and creates a different NAND ECC layout for the BCH, and use the new ECC layout. This causes a regression: We can not mount the ubifs which was created by the old NAND ECC layout. This patch fixes this issue by reverting to the legacy ECC layout. We will probably introduce a new device-tree property to indicate that the new ECC layout can be used. For now though, for the imminent 3.12 release, we just unconditionally revert to the 3.11 behaviour. This leaves a harmless cosmetic warning about an unused function. At this point in the cycle I really don't care. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
2013-08-31mtd: gpmi: remove the nand_scan()Huang Shijie1-30/+35
In order to make the nand_scan() work, the current code uses the hack code to init the @nand_chip->ecc.size and the @nand_chip->ecc.strength. and re-init some the ECC info in the gpmi_pre_bbt_scan(). This code is really a little ugly. The patch does following changes: (1) Use the nand_scan_ident()/nand_scan_tail() to replace the nand_scan(). (2) Init all the necessary values in the gpmi_init_last() before we call the nand_scan_tail(). (3) remove the code setting the ECC info, let the mtd layer to do the real job. (4) remove the gpmi_scan_bbt(). we do not need this function any more. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-31mtd: gpmi: set the BCH's geometry with the ecc infoHuang Shijie1-1/+131
If the nand chip provides us the ECC info, we can use it firstly. The set_geometry_by_ecc_info() will use the ECC info, and calculate the parameters we need. Rename the old code to legacy_set_geometry() which will takes effect when there is no ECC info from the nand chip or we fails in the ECC info case. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-31mtd: nand: gpmi-nand: use more sensible error codes at various placesLothar Waßmann1-3/+3
Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-30mtd: nand: refactor chip->block_markbad interfaceBrian Norris1-28/+16
The chip->block_markbad pointer should really only be responsible for writing a bad block marker for new bad blocks. It should not take care of BBT-related functionality, nor should it handle bookkeeping of bad block stats. This patch refactors the 3 users of the block_markbad interface (plus the default nand_base implementation) so that the common code is kept in nand_block_markbad_lowlevel(). It removes some inconsistencies between the various implementations and should allow for more centralized improvements in the future. Because gpmi-nand no longer needs the nand_update_bbt() function, let's stop exporting it as well. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> (for gpmi-nand parts) Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-06mtd: gpmi-nand: don't use devm_pinctrl_get_select_default() in probeWolfram Sang1-9/+0
Since commit ab78029 (drivers/pinctrl: grab default handles from device core), we can rely on device core for setting the default pins. Compile tested only. Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-05mtd: nand: gpmi-nand: remove unnecessary platform_set_drvdata()Jingoo Han1-2/+0
The driver core clears the driver data to NULL after device_release or on probe failure, since commit 0998d0631001288a5974afc0b2a5f568bcdecb4d (device-core: Ensure drvdata = NULL when no driver is bound). Thus, it is not needed to manually clear the device driver data to NULL. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-08-05mtd: gpmi-nand: fix error return from gpmi_get_clks()Michał Mirosław1-4/+8
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2013-04-04mtd: gpmi: move to use generic DMA helperShawn Guo1-50/+1
With the generic DMA device tree helper supported by mxs-dma driver, client devices only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2013-02-04mtd: gpmi: add sanity check for the ECCHuang Shijie1-2/+26
We do the check based on the following two facts: [1] The mx23/mx28 can only support 20-bits ECC, while the mx6 can supports 40-bits ECC. [2] The mx23/mx28 can only support the GF13, while the mx6 can supports GF13 and GF14. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2013-02-04mtd: gpmi: set the Golois Field bit for mx6q's BCHHuang Shijie1-2/+4
The GF13 can be only used in the following case: The ECC data chunk is less then 1K bytes. In mx23/mx28, the ecc data chunk is 512 bytes. So it is okay. But in mx6q, we begin to use some large nand chip whose ecc data chunk maybe 1K bytes long. So when the data chunk is 1K bytes, we have to use the GF14. This patch sets the Golois Field bit when the GF14 is needed. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2013-02-04mtd: gpmi: fix a dereferencing freed memory errorHuang Shijie1-1/+1
The patch "490e280 mtd: gpmi-nand: Convert to module_platform_driver()" introduced a "dereferencing freed memory" error. This patch fixes it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2013-02-04mtd: gpmi: Always report ECC stats and return max_bitflipsZach Sadecki1-19/+8
Always report corrected and failed ECC stats back up to the MTD layer. Also return max_bitflips from read_page() as is expected from NAND drivers now. Signed-off-by: Zach Sadecki <zsadecki@itwatchdogs.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2013-01-04Drivers: mtd: remove __dev* attributes.Greg Kroah-Hartman1-4/+3
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: David Woodhouse <dwmw2@infradead.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-11-22mtd: remove use of __devexitBill Pemberton1-1/+1
CONFIG_HOTPLUG is going away as an option so __devexit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-22mtd: remove use of __devinitBill Pemberton1-8/+8
CONFIG_HOTPLUG is going away as an option so __devinit is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-22mtd: remove use of __devexit_pBill Pemberton1-1/+1
CONFIG_HOTPLUG is going away as an option so __devexit_p is no longer needed. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-15mtd: gpmi: remove unneccessary headerHuang Shijie1-1/+6
The whole gpmi-nand driver has turned to pure devicetree supported. So the linux/mtd/gpmi-nand.h is not neccessary now. Just remove it, and move some macros to the gpmi-nand driver itself. Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-11-15mtd: gpmi-nand: make debug prints more clearVikram Narayanan1-6/+8
Make the error messages more debugging friendly Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2012-09-29mtd: gpmi: add EDO feature for imx6qHuang Shijie1-0/+8
When the frequency on the nand chip pins is above 33MHz, the nand EDO(extended Data Out) timing could be applied. The GPMI implements a Feedback read strobe to sample the read data in the EDO timing mode. This patch adds the EDO feature for the gpmi-nand driver. For some onfi nand chips, the mode 4 is the fastest; while for other onfi nand chips, the mode 5 is the fastest. This patch only adds the support for the fastest asynchronous timing mode. So this patch only supports the mode 4 and mode 5. I tested several Micron's ONFI nand chips with EDO enabled, take Micron MT29F32G08MAA for example (in mode 5, 100MHz): 1) The test result BEFORE we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 3632 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 3554 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 3592 KiB/s ....................................... ================================================= 2) The test result AFTER we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 19555 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 17319 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 18339 KiB/s ....................................... ================================================= 3) The read data performance is much improved by more then 5 times. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: do not set the default values for the extra clocksHuang Shijie1-10/+5
The default frequencies of the extra clocks are 200MHz. The current code sets the extra clocks to 44.5MHz. When i add the EDO feature to gpmi, i have to revert the extra clocks to 200MHz. So it is better that we do not set the default values for the extra clocks. The driver runs well even when we do not set the default values for extra clocks. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi-nand: Convert to module_platform_driver()Fabio Estevam1-22/+7
Using module_platform_driver() makes the code smaller and cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi-nand: Improve logging styleFabio Estevam1-3/+6
Improve logging style by prefixing the pr_ messages with "gpmi_nand". Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: fix the compiler warningsHuang Shijie1-12/+8
Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: change the code for clocksHuang Shijie1-9/+73
The gpmi nand driver may needs several clocks(MX6Q needs five clocks). In the old clock framework, all these clocks are chained together, all you need is to manipulate the first clock. But the kernel uses the common clk framework now, which forces us to get the clocks one by one. When we use them, we have to enable them one by one too. Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-07-17mtd: gpmi: update the bitflip_thresholdHuang Shijie1-0/+1
The origin code misses to update the bitflip_threshold when we have already get the right ecc_strength. The patch fixes it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-07-17mtd: gpmi: add on-flash BBT support for gpmi nandHuang Shijie1-0/+3
add the on flash bbt support for gpmi nand driver. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-07-06mtd: nand: teach write_page and write_page_raw return an error codeJosh Wu1-2/+4
There is an implemention of hardware ECC write page function which may return an error indication. For instance, using Atmel HW PMECC to write one page into a nand flash, the hardware engine will compute the BCH ecc code for this page. so we need read a the status register to theck whether the ecc code is generated. But we cannot assume the status register always can be ready, for example, incorrect hardware configuration or hardware issue, in such case we need write_page() to return a error code. Since the definition of 'write_page' function in struct nand_ecc_ctrl is 'void'. So this patch will: 1. add return 'int' value for 'write_page' function. 2. to be consitent, add return 'int' value for 'write_page_raw' fuctions too. 3. add code to test the return value, and if negative, indicate an error happend when write page with ECC. 4. fix the compile warning in all impacted nand flash driver. Note: I couldn't compile-test all of these easily, as some had ARCH dependencies. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-07-06mtd: nand: gpmi: need to use {read,write}_oob_rawBrian Norris1-0/+3
This patch is simply an added warning in the comments. Ideally, this patch need not be merged, but rather, a developer will write a proper solution that can use the ecc.read_oob_raw and ecc.write_oob_raw interfaces. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-07-06mtd: gpmi-nand: fix read page when reading to vmalloced areaSascha Hauer1-5/+5
The gpmi-nand driver uses virt_addr_valid() to check whether a buffer is suitable for dma. If it's not, a driver allocated buffer is used instead. Then after a page read the driver allocated buffer must be copied to the user supplied buffer. This does not happen since commit 7725cc85932bd02dd12c23108e0ef748c551ccba. This patch fixes the issue. The bug is encountered with UBI which uses a vmalloced buffer for the volume table. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: snijsure@grid-net.com Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-06-02Merge tag 'for-linus-3.5-20120601' of git://git.infradead.org/linux-mtdLinus Torvalds1-89/+95
Pull mtd update from David Woodhouse: - More robust parsing especially of xattr data in JFFS2 - Updates to mxc_nand and gpmi drivers to support new boards and device tree - Improve consistency of information about ECC strength in NAND devices - Clean up partition handling of plat_nand - Support NAND drivers without dedicated access to OOB area - BCH hardware ECC support for OMAP - Other fixes and cleanups, and a few new device IDs Fixed trivial conflict in drivers/mtd/nand/gpmi-nand/gpmi-nand.c due to added include files next to each other. * tag 'for-linus-3.5-20120601' of git://git.infradead.org/linux-mtd: (75 commits) mtd: mxc_nand: move ecc strengh setup before nand_scan_tail mtd: block2mtd: fix recursive call of mtd_writev mtd: gpmi-nand: define ecc.strength mtd: of_parts: fix breakage in Kconfig mtd: nand: fix scan_read_raw_oob mtd: docg3 fix in-middle of blocks reads mtd: cfi_cmdset_0002: Slight cleanup of fixup messages mtd: add fixup for S29NS512P NOR flash. jffs2: allow to complete xattr integrity check on first GC scan jffs2: allow to discriminate between recoverable and non-recoverable errors mtd: nand: omap: add support for hardware BCH ecc ARM: OMAP3: gpmc: add BCH ecc api and modes mtd: nand: check the return code of 'read_oob/read_oob_raw' mtd: nand: remove 'sndcmd' parameter of 'read_oob/read_oob_raw' mtd: m25p80: Add support for Winbond W25Q80BW jffs2: get rid of jffs2_sync_super jffs2: remove unnecessary GC pass on sync jffs2: remove unnecessary GC pass on umount jffs2: remove lock_super mtd: gpmi: add gpmi support for mx6q ...
2012-06-01mtd: gpmi-nand: define ecc.strengthMarek Vasut1-0/+5
Fix an issue which was introduced by the recent addition of ecc.strength. The ecc.strength wasn't set in gpmi-nand, resulting in the following crash: [ 2.550000] kernel BUG at drivers/mtd/nand/nand_base.c:3347! ... [ 2.550000] [<c020841c>] (nand_scan_tail+0x328/0x650) from [<c02f68e0>] (gpmi_nand_probe+0x43c/0x5a4) [ 2.550000] [<c02f68e0>] (gpmi_nand_probe+0x43c/0x5a4) from [<c01f6618>] (platform_drv_probe+0x14/0x18) [ 2.550000] [<c01f6618>] (platform_drv_probe+0x14/0x18) from [<c01f55b0>] (driver_probe_device+0x74/0x1fc) [ 2.550000] [<c01f55b0>] (driver_probe_device+0x74/0x1fc) from [<c01f57cc>] (__driver_attach+0x94/0x98) [ 2.550000] [<c01f57cc>] (__driver_attach+0x94/0x98) from [<c01f3d40>] (bus_for_each_dev+0x50/0x80) [ 2.550000] [<c01f3d40>] (bus_for_each_dev+0x50/0x80) from [<c01f4e18>] (bus_add_driver+0x188/0x25c) [ 2.550000] [<c01f4e18>] (bus_add_driver+0x188/0x25c) from [<c01f5a70>] (driver_register+0x78/0x138) [ 2.550000] [<c01f5a70>] (driver_register+0x78/0x138) from [<c043dc7c>] (gpmi_nand_init+0xc/0x30) [ 2.550000] [<c043dc7c>] (gpmi_nand_init+0xc/0x30) from [<c0008824>] (do_one_initcall+0x108/0x17c) [ 2.550000] [<c0008824>] (do_one_initcall+0x108/0x17c) from [<c042a8b8>] (kernel_init+0xfc/0x1bc) [ 2.550000] [<c042a8b8>] (kernel_init+0xfc/0x1bc) from [<c000fab4>] (kernel_thread_exit+0x0/0x8) Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-05-19mtd: nand: gpmi: fix compile error caused by pinctrl callShawn Guo1-1/+1
Fix following compile error caused by commit 39febc0 (mtd: nand: gpmi: adopt pinctrl support). CC drivers/mtd/nand/gpmi-nand/gpmi-nand.o drivers/mtd/nand/gpmi-nand/gpmi-nand.c: In function ‘acquire_resources’: drivers/mtd/nand/gpmi-nand/gpmi-nand.c:499:45: error: ‘pdev’ undeclared (first use in this function) Reported-by: Subodh Nijsure <snijsure@grid-net.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-05-14mtd: nand: remove 'sndcmd' parameter of 'read_oob/read_oob_raw'Shmulik Ladkani1-6/+2
As of [mtd: nand: remove autoincrement 'sndcmd' code], the NAND_CMD_READ0 command is issued unconditionally. Thus, read_oob/read_oob_raw's 'sndcmd' argument is no longer needed, as well as their return code. Remove the 'sndcmd' parameter, and set the return code to 0. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-05-14mtd: gpmi: add gpmi support for mx6qHuang Shijie1-0/+4
add gpmi support for mx6q. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-05-14mtd: gpmi: add device tree support to gpmi-nandHuang Shijie1-64/+62
This patch just adds the DT support to gpmi-nand. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-05-14mtd: gpmi-nand: utilize oob_requested parameterBrian Norris1-15/+18
Don't read OOB if the caller didn't request it. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-05-14mtd: nand: add 'oob_required' argument to NAND {read,write}_page interfacesBrian Norris1-4/+4
New NAND controllers can perform read/write via HW engines which don't expose OOB data in their DMA mode. To reflect this, we should rework the nand_chip / nand_ecc_ctrl interfaces that assume that drivers will always read/write OOB data in the nand_chip.oob_poi buffer. A better interface includes a boolean argument that explicitly tells the callee when OOB data is requested by the calling layer (for reading/writing to/from nand_chip.oob_poi). This patch adds the 'oob_required' parameter to each relevant {read,write}_page interface; all 'oob_required' parameters are left unused for now. The next patch will set the parameter properly in the nand_base.c callers, and follow-up patches will make use of 'oob_required' in some of the callee functions. Note that currently, there is no harm in ignoring the 'oob_required' parameter and *always* utilizing nand_chip.oob_poi, but there can be performance/complexity/design benefits from avoiding filling oob_poi in the common case. I will try to implement this for some drivers which can be ported easily. Note: I couldn't compile-test all of these easily, as some had ARCH dependencies. [dwmw2: Merge later 1/0 vs. true/false cleanup] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Acked-by: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-05-12mtd: nand: gpmi: adopt pinctrl supportShawn Guo1-0/+9
Cc: linux-mtd@lists.infradead.org Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-04-20dma: mxs-dma: enable channel in device_issue_pending callShawn Guo1-0/+1
Enable channel in device_issue_pending call, so that the order between cookie assignment and channel enabling can be ensured naturally. It fixes the mxs gpmi-nand breakage which is caused by the incorrect order of cookie assigning and channel enabling. Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Huang Shijie <b32955@freescale.com> Tested-by <samgandhi9@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-17 14:21:02 +0300