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2018-10-08mmc: renesas_sdhi_internal_dmac: set scatter/gather max segment sizeNiklas Söderlund1-0/+8
Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a device_dma_parameters structure and filling in the max segment size. The size used is the result of a discussion with Renesas hardware engineers and unfortunately not found in the datasheet. renesas_sdhi_internal_dmac ee140000.sd: DMA-API: mapping sg segment longer than device claims to support [len=126976] [max=65536] Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> [wsa: simplified some logic after validating intended dma_parms life cycle and added comment] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sunxi: Use new timing mode for A64 eMMC controllerChen-Yu Tsai1-0/+1
The eMMC controller is also a new timing mode controller, but it doesn't have the timing mode switch. It does however have signal delay and calibration controls, typical of Allwinner MMC controllers that support the new timing mode. Enable the new timing mode setting for the A64 eMMC controller. This also enables MMC HS-DDR modes, which gives higher throughput for eMMC chips that support it, and can deliver such throughput. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sunxi: Clarify new timing mode usage and implementationChen-Yu Tsai1-6/+17
Newer sunxi mmc controller variants support what they call the "new timing mode". Support for this was implemented in two ways, according to the hardware that was seen at the time. The first type retained the old timing mode, and both the clock and mmc controllers had switches to select which mode was used. Both switches had to be set to the same setting. This variant was denoted with the .has_timings_switch field in the sunxi_mmc_cfg structure. This hardware is only seen on the A83T. The second type did away with the old timing mode. The clock controller no longer had the mode selection or clock delay setting bits. In some cases the mmc controller retained its mode selection bit, but this always needed to be set to the new mode, or instabilities would occur. In a few cases, such as the A64 and H6 eMMC controller, the mode selection bit is gone, but the controller still behaves like the new timing mode, requiring the module clock to be double the card clock in DDR transfer modes. This variant is denoted with the .needs_new_timings field. This patch adds more comments explaining the two fields, as well as the possibly nonexistent mode switch in the mmc controller. The .has_timings_switch is renamed to .ccu_has_timings_switch to clarify its meaning. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci-sprd: Add Spreadtrum's initial host controllerChunyan Zhang3-0/+512
This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu <billows.wu@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: SDMA may use Auto-CMD23 in v4 modeChunyan Zhang1-2/+5
When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: Add Auto CMD Auto Select supportChunyan Zhang2-10/+41
As SD Host Controller Specification v4.10 documents: Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. This patch add this new mode support. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: Add 32-bit block count support for v4 modeChunyan Zhang2-1/+21
Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: Add ADMA2 64-bit addressing support for V4 modeChunyan Zhang2-26/+78
ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> [Ulf: Fixed conflict while applying] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: Change SDMA address register for v4 modeChunyan Zhang1-10/+20
According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: Add sd host v4 modeChunyan Zhang2-0/+32
For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduced an interface to enable v4 mode. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: Add version V4 definitionChunyan Zhang2-1/+4
Added definitions for v400, v410, v420. Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: fix inconsistent IS_ERR and PTR_ERRYueHaibing1-1/+1
Fix inconsistent IS_ERR and PTR_ERR in tegra_sdhci_init_pinctrl_info, the proper pointer to be passed as argument is 'pinctrl_state_1v8' Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Aapo Vienamo <aapo.vienamo@iki.fi> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Implement periodic pad calibrationAapo Vienamo1-0/+22
Rerun the pad calibration procedure before sdhci_request() if the 100 ms recalibration interval has been exceeded. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Implement HS400 delay line calibrationAapo Vienamo1-0/+29
Implement HS400 specific delay line calibration procedure. This is a Tegra specific procedure and has to be performed regardless whether enhanced strobe or HS400 tuning is used. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Implement HS400 enhanced strobeAapo Vienamo1-0/+23
Implement eMMC HS400 enhanced strobe. Enhanced strobe is an alternative mechanism to the HS400 tuning procedure. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Parse and program DQS trim valueAapo Vienamo1-3/+29
Parse and program the HS400 DQS trim value from DT. Program a fallback value in case the property is missing. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Enable UHS and HS200 modes for Tegra186Aapo Vienamo1-1/+3
Set nvquirks to enable higher speed modes. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Enable UHS and HS200 modes for Tegra210Aapo Vienamo1-1/+3
Set nvquirks to enable higher speed modes. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Disable card clock during tuning cmd on Tegra210Aapo Vienamo1-23/+58
Implement tegra210_sdhci_writew() to disable card clock and issue a reset when the tuning command is sent. This is done to prevent an intermittent hang with around 10 % failure rate during tuning. Add tegra186_sdhci_ops because this workaround is specific to Tegra210. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Remove tegra_sdhci_writew() from tegra210_sdhci_opsAapo Vienamo1-1/+0
tegra_sdhci_writew() defers the write to SDHCI_TRANSFER_MODE until SDHCI_COMMAND is written. This is not necessary on Tegra210 and Tegra186 and it breaks read-modify-write operations on SDHCI_TRANSFER_MODE because writes to SDHCI_TRANSFER_MODE aren't visible until SDHCI_COMMAND has been written to. This results in tuning failures on Tegra210. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186Aapo Vienamo1-2/+15
Add a new sdhci_ops struct for Tegra210 and Tegra186 which doesn't set the custom tuning callback used on previous SoC generations. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Configure default trim value on resetAapo Vienamo1-1/+6
Program the outbound sampling trim value in tegra_sdhci_reset(). Unlike the outbound tap value this does not depend on the signaling mode and needs to be only programmed once. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Configure default tap valuesAapo Vienamo1-55/+77
Set the default inbound timing adjustment tap value on reset and on non-tunable modes. The default tap value is not programmed on tunable modes because the tuning sequence is used instead to determine the tap value. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Parse default trim and tap from dtAapo Vienamo1-0/+22
Parse the default inbound and outbound sampling trimmer values from the device tree. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Add a workaround for tap value change glitchAapo Vienamo1-2/+28
Add quirk to disable the card clock during configuration of the tap value in tegra_sdhci_set_tap() and issue sdhci_reset() after value change. This is a workaround to avoid propagation of a potential glitch caused by setting the tap value. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Enable pad calibration on Tegra210 and Tegra186Aapo Vienamo1-2/+4
Set NVQUIRK_HAS_PADCALIB on Tegra210 and Tegra186 to enable automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Perform pad calibration after voltage switchAapo Vienamo1-0/+5
Run the automatic pad calibration after voltage switching if tegra_host->pad_calib_required is set. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Program pad autocal offsets from dtAapo Vienamo1-1/+151
Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Disable card clock during pad calibrationAapo Vienamo1-0/+26
Disable the card clock during automatic pad drive strength calibration and re-enable it afterwards. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Power on the calibration padAapo Vienamo1-0/+26
Automatic pad drive strength calibration is performed on a separate pad identical to the ones used for driving the actual bus. Power on the calibration pad during the calibration procedure and power it off afterwards to save power. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Set calibration pad voltage referenceAapo Vienamo1-23/+33
Configure the voltage reference used by the automatic pad drive strength calibration procedure. The value is a magic number from the TRM. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Poll for calibration completionAapo Vienamo1-5/+17
Implement polling with 10 ms timeout for automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Reconfigure pad voltages during voltage switchingAapo Vienamo1-7/+129
Parse the pinctrl state and nvidia,only-1-8-v properties from the device tree. Validate the pinctrl and regulator configuration before unmasking UHS modes. Implement pad voltage state reconfiguration in the mmc start_signal_voltage_switch() callback. Add NVQUIRK_NEEDS_PAD_CONTROL and add set it for Tegra210 and Tegra186. The pad configuration is done in the mmc callback because the order of pad reconfiguration and sdhci voltage switch depend on the voltage to which the transition occurs. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tmio: remove now unused variableWolfram Sang1-1/+1
This variable is unused now after some refactoring. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tmio: more concise clk calculationWolfram Sang1-8/+3
Concise, but still readable. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tmio: Fix SCC error detectionMasaharu Hayakawa1-2/+2
SDR104, HS200 and HS400 need to check for SCC error. If SCC error is detected, retuning is necessary. Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> [Niklas: update commit message] Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: renesas_sdhi: skip SCC error check when retuningMasaharu Hayakawa1-0/+13
Checking for SCC error during retuning is unnecessary. Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> [Niklas: fix small style issue] Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tmio: refactor CLK_CTL bit calculationMasahiro Yamada1-5/+13
for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) clock <<= 1; ... is too tricky, hence I replaced with roundup_pow_of_two(divisor) >> 2 '(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but it is not clear. 'divisor <= 1' is easier to understand. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clockMasahiro Yamada1-26/+12
renesas_sdhi_clk_start() and renesas_sdhi_clk_stop() are now only called from renesas_sdhi_set_clock(). Merge them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci-of-dwcmshc: solve 128MB DMA boundary limitationJisheng Zhang1-0/+39
When using DMA, if the DMA addr spans 128MB boundary, we have to split the DMA transfer into two so that each one doesn't exceed the boundary. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_opsJisheng Zhang2-14/+27
Add this hook so that it can be overridden with driver specific implementations. We also let the original sdhci_adma_write_desc() accept &desc so that the function can set its new value. Then export the function so that it could be reused by driver's specific implementations. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: add adma_table_cnt member to struct sdhci_hostJisheng Zhang2-8/+12
This patch adds adma_table_cnt member to struct sdhci_host to give more flexibility to drivers to control the ADMA table count. Default value of adma_table_cnt is set to (SDHCI_MAX_SEGS * 2 + 1). Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: Convert to using %pOFn instead of device_node.nameRob Herring1-2/+2
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Hu Ziji <huziji@marvell.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-mmc@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: Export sdhci_request()Aapo Vienamo2-1/+3
Allow SDHCI drivers to hook code before and after sdhci_request() by making it externally visible. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08sdhci: acpi: add qcom sdhci host reset quirk fixWang Dongsheng1-0/+60
After host requests RESET_FOR_ALL action, the hardware output an interrupt for OS and waiting for the OS to approve. Before writing this fix, ACPI GED has handled the interrupt. But the ACPI GED belongs to a slow process, and sometimes the handling process time is more than 100ms(Mutex wait more than 100ms). So drop the GED solution and add this quirk fix. Signed-off-by: Wang Dongsheng <dongsheng.wang@hxt-semitech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08sdhci: acpi: add free_slot callbackWang Dongsheng1-0/+8
The device specific resource can be free in free_slot after removing host controller. Signed-off-by: Wang Dongsheng <dongsheng.wang@hxt-semitech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci-of-esdhc: add erratum A008171 supportYinbo Zhu2-1/+44
In tuning mode of operation, when TBCTL[TB_EN] is set, eSDHC may report one of the following errors : 1)Tuning error while running tuning operation where SYSCTL2[SAMPCLKSEL] will not get set even when SYSCTL2[EXTN] is reset. OR 2)Data transaction error (e.g. IRQSTAT[DCE], IRQSTAT[DEBE]) during data transaction errors. This issue occurs when the data window sampled within eSDHC is in full cycle. So, in that case, eSDHC is not able to find out the start and end points of the data window and sets the sampling pointer at default location (which is middle of the internal SD clock). If this sampling point coincides with the data eye boundary, then it can result in the above mentioned errors. Impact: Tuning mode of operation for SDR50, SDR104 or HS200 speed modes may not work properly Workaround: In case eSDHC reports tuning error or data errors in tuning mode of operation, by add the erratum A008171 support to fix the issue. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci: add tuning error codesYinbo Zhu2-4/+6
This patch is to add tuning error codes to judge tuning state Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: uniphier-sd: add UniPhier SD/eMMC controller driverMasahiro Yamada3-0/+704
Here is another TMIO MMC variant found in Socionext UniPhier SoCs. As commit b6147490e6aa ("mmc: tmio: split core functionality, DMA and MFD glue") said, these MMC controllers use the IP from Panasonic. However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip was the first upstreamed user of this IP. The common driver code for this IP is now called 'tmio-mmc-core' in Linux although it is a historical misnomer. Anyway, this driver select's MMC_TMIO_CORE to borrow the common code from tmio-mmc-core.c Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine like renesas_sdhi_sys_dmac.c. The difference is UniPhier SoCs use a single DMA channel whereas Renesas chips request separate channels for RX and TX. Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine like renesas_sdhi_internal_dmac.c The register map is almost the same, so I guess Renesas and Socionext use the same internal DMA hardware. The main difference is, the register offsets are doubled for Renesas. Renesas Socionext SDHI UniPhier DM_CM_DTRAN_MODE 0x820 0x410 DM_CM_DTRAN_CTRL 0x828 0x414 DM_CM_RST 0x830 0x418 DM_CM_INFO1 0x840 0x420 DM_CM_INFO1_MASK 0x848 0x424 DM_CM_INFO2 0x850 0x428 DM_CM_INFO2_MASK 0x858 0x42c DM_DTRAN_ADDR 0x880 0x440 DM_DTRAN_ADDREX --- 0x444 This comes from the difference of host->bus_shift; 2 for Renesas SoCs, and 1 for UniPhier SoCs. Also, the datasheet for UniPhier SoCs defines DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers. It could be possible to factor out the DMA common code by introducing some hooks to cope with platform quirks, but this patch does not touch that for now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tmio: move tmio_mmc_set_clock() to platform hookMasahiro Yamada4-89/+117
tmio_mmc_set_clock() is full of quirks because different SoC vendors extended this in different ways. The original IP defines the divisor range 1/2 ... 1/512. bit 7 is set: 1/512 bit 6 is set: 1/256 ... bit 0 is set: 1/4 all bits clear: 1/2 It is platform-dependent how to achieve the 1/1 clock. I guess the TMIO-MFD variant uses the clock selector outside of this IP, as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c I guess bit[7:0]=0xff is Renesas-specific extension. Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer versions of UniPhier SoC variants use bit 16 for 1/1024. host->clk_update() is only used by the Renesas variants, whereas host->set_clk_div() is only used by the TMIO-MFD variants. To cope with this mess, promote tmio_mmc_set_clock() to a new platform hook ->set_clock(), and melt the old two hooks into it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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