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2024-10-14mmc: core: Add Ext memory addressing for eraseAvri Altman1-0/+12
CMD22 shall precede CMD32 and CMD33 to configure 38-bit erase start address and 38 bit erase stop address. Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Avri Altman <avri.altman@wdc.com> Link: https://lore.kernel.org/r/20241006051148.160278-7-avri.altman@wdc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: core: Allow mmc erase to carry large addressesAvri Altman3-21/+34
Preparing for SDUC, Allow the erase address to be larger beyond a 32 bit address. Tested-by: Ricky WU <ricky_wu@realtek.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Avri Altman <avri.altman@wdc.com> Link: https://lore.kernel.org/r/20241006051148.160278-6-avri.altman@wdc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: core: Add open-ended Ext memory addressingAvri Altman2-0/+8
For open-ended read/write - just send CMD22 before issuing the command. Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Avri Altman <avri.altman@wdc.com> Link: https://lore.kernel.org/r/20241006051148.160278-5-avri.altman@wdc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: core: Don't use close-ended rw for SDUCAvri Altman1-1/+1
The SDUC spec expects CMD22 to get squeezed between CMD23 and the read/write command, e.g. CMD23->CMD22->CMD18 and CMD23->CMD22->CMD25. At this early stage of adoption, we want to avoid an amid stream of fixes & quirks of bogus hw, that tends to apply extra logic specifically around auto-cmd12 & auto-cmd23. Let's leave close-ended out for now, and re-consider this should those cards become ubiquitous, if any. It also means that BLK_FEAT_FUA will not be used for I/O, but instead we will rely on BLK_FEAT_WRITE_CACHE. Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Avri Altman <avri.altman@wdc.com> Link: https://lore.kernel.org/r/20241006051148.160278-4-avri.altman@wdc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: sd: Add Extension memory addressingAvri Altman2-0/+16
SDUC memory addressing spans beyond 2TB and up to 128TB. Therefore, 38 bits are required to access the entire memory space of all sectors. Those extra 6 bits are to be carried by CMD22 prior of sending read/write/erase commands: CMD17, CMD18, CMD24, CMD25, CMD32, and CMD33. CMD22 will carry the higher order 6 bits, and must precedes any of the above commands even if it targets sector < 2TB. No error related to address or length is indicated in CMD22 but rather in the read/write command itself. Tested-by: Ricky WU <ricky_wu@realtek.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Avri Altman <avri.altman@wdc.com> Link: https://lore.kernel.org/r/20241006051148.160278-3-avri.altman@wdc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: sd: SDUC Support RecognitionAvri Altman5-14/+25
Ultra Capacity SD cards (SDUC) was already introduced in SD7.0. Those cards support capacity larger than 2TB and up to including 128TB. ACMD41 was extended to support the host-card handshake during initialization. The card expects that the HCS & HO2T bits to be set in the command argument, and sets the applicable bits in the R3 returned response. On the contrary, if a SDUC card is inserted to a non-supporting host, it will never respond to this ACMD41 until eventually, the host will timed out and give up. Also, add SD CSD version 3.0 - designated for SDUC, and properly parse the csd register as the c_size field got expanded to 28 bits. Do not enable SDUC for now - leave it to the last patch in the series. Tested-by: Ricky WU <ricky_wu@realtek.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Avri Altman <avri.altman@wdc.com> Link: https://lore.kernel.org/r/20241006051148.160278-2-avri.altman@wdc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: Switch back to struct platform_driver::remove()Uwe Kleine-König74-75/+75
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/mmc to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20240927145832.754697-2-u.kleine-koenig@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: sdhci-esdhc-imx: enable quirks SDHCI_QUIRK_NO_LEDPeng Fan1-0/+6
Enable SDHCI_QUIRK_NO_LED for i.MX7ULP, i.MX8MM, i.MX8QXP and i.MXRT1050. Even there is LCTL register bit, there is no IOMUX PAD for it. So there is no sense to enable LED for SDHCI for these SoCs. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240923062016.1165868-1-peng.fan@oss.nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: sdhci_am654: Add sdhci_am654_start_signal_voltage_switchJudith Mendez1-0/+30
The sdhci_start_signal_voltage_switch function sets V1P8_SIGNAL_ENA by default after switching to 1v8 signaling. V1P8_SIGNAL_ENA determines whether to launch cmd/data on neg edge or pos edge of clock. Due to some eMMC and SD failures seen across am62x platform, do not set V1P8_SIGNAL_ENA by default, only enable the bit for devices that require this bit in order to switch to 1v8 voltage for uhs modes. Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240913185403.1339115-1-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-14mmc: core: Add SD card quirk for broken poweroff notificationKeita Aihara3-1/+17
GIGASTONE Gaming Plus microSD cards manufactured on 02/2022 report that they support poweroff notification and cache, but they are not working correctly. Flush Cache bit never gets cleared in sd_flush_cache() and Poweroff Notification Ready bit also never gets set to 1 within 1 second from the end of busy of CMD49 in sd_poweroff_notify(). This leads to I/O error and runtime PM error state. I observed that the same card manufactured on 01/2024 works as expected. This problem seems similar to the Kingston cards fixed with commit c467c8f08185 ("mmc: Add MMC_QUIRK_BROKEN_SD_CACHE for Kingston Canvas Go Plus from 11/2019") and should be handled using quirks. CID for the problematic card is here. 12345641535443002000000145016200 Manufacturer ID is 0x12 and defined as CID_MANFID_GIGASTONE as of now, but would like comments on what naming is appropriate because MID list is not public and not sure it's right. Signed-off-by: Keita Aihara <keita.aihara@sony.com> Link: https://lore.kernel.org/r/20240913094417.GA4191647@sony.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-11Merge tag 'mmc-v6.12-rc1' of ↵Linus Torvalds3-54/+28
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: "MMC core: - Prevent splat from warning when setting maximum DMA segment MMC host: - mvsdio: Drop sg_miter support for PIO as it didn't work - sdhci-of-dwcmshc: Prevent stale interrupt for the T-Head 1520 variant" * tag 'mmc-v6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-of-dwcmshc: Prevent stale command interrupt handling Revert "mmc: mvsdio: Use sg_miter for PIO" mmc: core: Only set maximum DMA segment size if DMA is supported
2024-10-10mmc: sdhci-of-dwcmshc: Prevent stale command interrupt handlingMichal Wilczynski1-0/+8
While working with the T-Head 1520 LicheePi4A SoC, certain conditions arose that allowed me to reproduce a race issue in the sdhci code. To reproduce the bug, you need to enable the sdio1 controller in the device tree file `arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi` as follows: &sdio1 { bus-width = <4>; max-frequency = <100000000>; no-sd; no-mmc; broken-cd; cap-sd-highspeed; post-power-on-delay-ms = <50>; status = "okay"; wakeup-source; keep-power-in-suspend; }; When resetting the SoC using the reset button, the following messages appear in the dmesg log: [ 8.164898] mmc2: Got command interrupt 0x00000001 even though no command operation was in progress. [ 8.174054] mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== [ 8.180503] mmc2: sdhci: Sys addr: 0x00000000 | Version: 0x00000005 [ 8.186950] mmc2: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 [ 8.193395] mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 [ 8.199841] mmc2: sdhci: Present: 0x03da0000 | Host ctl: 0x00000000 [ 8.206287] mmc2: sdhci: Power: 0x0000000f | Blk gap: 0x00000000 [ 8.212733] mmc2: sdhci: Wake-up: 0x00000000 | Clock: 0x0000decf [ 8.219178] mmc2: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 [ 8.225622] mmc2: sdhci: Int enab: 0x00ff1003 | Sig enab: 0x00ff1003 [ 8.232068] mmc2: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 [ 8.238513] mmc2: sdhci: Caps: 0x3f69c881 | Caps_1: 0x08008177 [ 8.244959] mmc2: sdhci: Cmd: 0x00000502 | Max curr: 0x00191919 [ 8.254115] mmc2: sdhci: Resp[0]: 0x00001009 | Resp[1]: 0x00000000 [ 8.260561] mmc2: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 [ 8.267005] mmc2: sdhci: Host ctl2: 0x00001000 [ 8.271453] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000 [ 8.278594] mmc2: sdhci: ============================================ I also enabled some traces to better understand the problem: kworker/3:1-62 [003] ..... 8.163538: mmc_request_start: mmc2: start struct mmc_request[000000000d30cc0c]: cmd_opcode=5 cmd_arg=0x0 cmd_flags=0x2e1 cmd_retries=0 stop_opcode=0 stop_arg=0x0 stop_flags=0x0 stop_retries=0 sbc_opcode=0 sbc_arg=0x0 sbc_flags=0x0 sbc_retires=0 blocks=0 block_size=0 blk_addr=0 data_flags=0x0 tag=0 can_retune=0 doing_retune=0 retune_now=0 need_retune=0 hold_retune=1 retune_period=0 <idle>-0 [000] d.h2. 8.164816: sdhci_cmd_irq: hw_name=ffe70a0000.mmc quirks=0x2008008 quirks2=0x8 intmask=0x10000 intmask_p=0x18000 irq/24-mmc2-96 [000] ..... 8.164840: sdhci_thread_irq: msg= irq/24-mmc2-96 [000] d.h2. 8.164896: sdhci_cmd_irq: hw_name=ffe70a0000.mmc quirks=0x2008008 quirks2=0x8 intmask=0x1 intmask_p=0x1 irq/24-mmc2-96 [000] ..... 8.285142: mmc_request_done: mmc2: end struct mmc_request[000000000d30cc0c]: cmd_opcode=5 cmd_err=-110 cmd_resp=0x0 0x0 0x0 0x0 cmd_retries=0 stop_opcode=0 stop_err=0 stop_resp=0x0 0x0 0x0 0x0 stop_retries=0 sbc_opcode=0 sbc_err=0 sbc_resp=0x0 0x0 0x0 0x0 sbc_retries=0 bytes_xfered=0 data_err=0 tag=0 can_retune=0 doing_retune=0 retune_now=0 need_retune=0 hold_retune=1 retune_period=0 Here's what happens: the __mmc_start_request function is called with opcode 5. Since the power to the Wi-Fi card, which resides on this SDIO bus, is initially off after the reset, an interrupt SDHCI_INT_TIMEOUT is triggered. Immediately after that, a second interrupt SDHCI_INT_RESPONSE is triggered. Depending on the exact timing, these conditions can trigger the following race problem: 1) The sdhci_cmd_irq top half handles the command as an error. It sets host->cmd to NULL and host->pending_reset to true. 2) The sdhci_thread_irq bottom half is scheduled next and executes faster than the second interrupt handler for SDHCI_INT_RESPONSE. It clears host->pending_reset before the SDHCI_INT_RESPONSE handler runs. 3) The pending interrupt SDHCI_INT_RESPONSE handler gets called, triggering a code path that prints: "mmc2: Got command interrupt 0x00000001 even though no command operation was in progress." To solve this issue, we need to clear pending interrupts when resetting host->pending_reset. This ensures that after sdhci_threaded_irq restores interrupts, there are no pending stale interrupts. The behavior observed here is non-compliant with the SDHCI standard. Place the code in the sdhci-of-dwcmshc driver to account for a hardware-specific quirk instead of the core SDHCI code. Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: 43658a542ebf ("mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20241008100327.4108895-1-m.wilczynski@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-03Revert "mmc: mvsdio: Use sg_miter for PIO"Linus Walleij1-53/+18
This reverts commit 2761822c00e8c271f10a10affdbd4917d900d7ea. When testing on real hardware the patch does not work. Revert, try to acquire real hardware, and retry. These systems typically don't have highmem anyway so the impact is likely zero. Cc: stable@vger.kernel.org Reported-by: Charlie <g4sra@protonmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20240927-kirkwood-mmc-regression-v1-1-2e55bbbb7b19@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-03mmc: core: Only set maximum DMA segment size if DMA is supportedGuenter Roeck1-1/+2
Since upstream commit 334304ac2bac ("dma-mapping: don't return errors from dma_set_max_seg_size") calling dma_set_max_seg_size() on a device not supporting DMA results in a warning traceback. This is seen when booting the sifive_u machine from SD. The underlying SPI controller (sifive,spi0 compatible) explicitly sets dma_mask to NULL. Avoid the backtrace by only calling dma_set_max_seg_size() if DMA is supported. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Fixes: 334304ac2bac ("dma-mapping: don't return errors from dma_set_max_seg_size") Link: https://lore.kernel.org/r/20240924210123.2288529-1-linux@roeck-us.net Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-10-03move asm/unaligned.h to linux/unaligned.hAl Viro5-5/+5
asm/unaligned.h is always an include of asm-generic/unaligned.h; might as well move that thing to linux/unaligned.h and include that - there's nothing arch-specific in that header. auto-generated by the following: for i in `git grep -l -w asm/unaligned.h`; do sed -i -e "s/asm\/unaligned.h/linux\/unaligned.h/" $i done for i in `git grep -l -w asm-generic/unaligned.h`; do sed -i -e "s/asm-generic\/unaligned.h/linux\/unaligned.h/" $i done git mv include/asm-generic/unaligned.h include/linux/unaligned.h git mv tools/include/asm-generic/unaligned.h tools/include/linux/unaligned.h sed -i -e "/unaligned.h/d" include/asm-generic/Kbuild sed -i -e "s/__ASM_GENERIC/__LINUX/" include/linux/unaligned.h tools/include/linux/unaligned.h
2024-09-27[tree-wide] finally take no_llseek outAl Viro1-1/+0
no_llseek had been defined to NULL two years ago, in commit 868941b14441 ("fs: remove no_llseek") To quote that commit, At -rc1 we'll need do a mechanical removal of no_llseek - git grep -l -w no_llseek | grep -v porting.rst | while read i; do sed -i '/\<no_llseek\>/d' $i done would do it. Unfortunately, that hadn't been done. Linus, could you do that now, so that we could finally put that thing to rest? All instances are of the form .llseek = no_llseek, so it's obviously safe. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-09-19Merge tag 'dma-mapping-6.12-2024-09-19' of ↵Linus Torvalds1-1/+2
git://git.infradead.org/users/hch/dma-mapping Pull dma-mapping updates from Christoph Hellwig: - support DMA zones for arm64 systems where memory starts at > 4GB (Baruch Siach, Catalin Marinas) - support direct calls into dma-iommu and thus obsolete dma_map_ops for many common configurations (Leon Romanovsky) - add DMA-API tracing (Sean Anderson) - remove the not very useful return value from various dma_set_* APIs (Christoph Hellwig) - misc cleanups and minor optimizations (Chen Y, Yosry Ahmed, Christoph Hellwig) * tag 'dma-mapping-6.12-2024-09-19' of git://git.infradead.org/users/hch/dma-mapping: dma-mapping: reflow dma_supported dma-mapping: reliably inform about DMA support for IOMMU dma-mapping: add tracing for dma-mapping API calls dma-mapping: use IOMMU DMA calls for common alloc/free page calls dma-direct: optimize page freeing when it is not addressable dma-mapping: clearly mark DMA ops as an architecture feature vdpa_sim: don't select DMA_OPS arm64: mm: keep low RAM dma zone dma-mapping: don't return errors from dma_set_max_seg_size dma-mapping: don't return errors from dma_set_seg_boundary dma-mapping: don't return errors from dma_set_min_align_mask scsi: check that busses support the DMA API before setting dma parameters arm64: mm: fix DMA zone when dma-ranges is missing dma-mapping: direct calls for dma-iommu dma-mapping: call ->unmap_page and ->unmap_sg unconditionally arm64: support DMA zone above 4GB dma-mapping: replace zone_dma_bits by zone_dma_limit dma-mapping: use bit masking to check VM_DMA_COHERENT
2024-09-13mmc: core: Use dev_err_probe for deferred regulatorsAlexander Stein1-2/+6
In case vmmc or vqmmc regulator is not available yet, use dev_err_probe in order to set a deferred probe reason. This is a helpful hint in /sys/kernel/debug/devices_deferred Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20240911090910.3060749-1-alexander.stein@ew.tq-group.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-05mmc: sdhci_am654: Add prints to tuning algorithmJudith Mendez1-1/+10
Add debug prints to tuning algorithm for debugging. Also add error print if we fail tuning. Signed-off-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20240904232512.830778-3-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-05mmc: sdhci_am654: Add retry tuningJudith Mendez1-12/+35
Add retry tuning up to 10 times if we fail to find a failing region or no passing itapdly. This is necessary since some eMMC has been observed to never find a failing itapdly on the first couple of tuning iterations, but eventually does. Keep count of current tuning iteration using tuning_loop. It has been observed that the tuning algorithm does not need to loop more than 10 times before finding a failing itapdly. Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240904232512.830778-2-jm@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: block: add RPMB dependencyJens Wiklander1-0/+1
Prevent build error when CONFIG_RPMB=m and CONFIG_MMC_BLOCK=y by adding a dependency to CONFIG_RPMB for CONFIG_MMC_BLOCK block so the RPMB subsystem always is reachable if configured. This means that CONFIG_MMC_BLOCK automatically becomes compiled as a module if CONFIG_RPMB is compiled as a module. If CONFIG_RPMB isn't configured or is configured as built-in, CONFIG_MMC_BLOCK will remain unchanged. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202409021448.RSvcBPzt-lkp@intel.com/ Fixes: 7852028a35f0 ("mmc: block: register RPMB partition with the RPMB subsystem") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20240902151231.3705204-1-jens.wiklander@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: core Convert UNSTUFF_BITS macro to inline functionAvri Altman3-127/+113
The UNSTUFF_BITS macro, which is defined in both drivers/mmc/core/mmc.c and drivers/mmc/core/sd.c, has been converted to an inline function to improve readability, maintainability, and type safety. Signed-off-by: Avri Altman <avri.altman@wdc.com> Link: https://lore.kernel.org/r/20240902123331.3566447-1-avri.altman@wdc.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: core: Convert simple_stroul to kstroulRiyan Dhiman1-3/+3
simple_strtoul() is obsolete and lacks proper error handling, making it unsafe for converting strings to unsigned long values. Replace it with kstrtoul(), which provides robust error checking and better safety. This change improves the reliability of the string-to-integer conversion and aligns with current kernel coding standards. Error handling is added to catch conversion failures, returning -EINVAL when input is invalid. Issue reported by checkpatch: - WARNING: simple_strtoul is obsolete, use kstrtoul instead Signed-off-by: Riyan Dhiman <riyandhiman14@gmail.com> Link: https://lore.kernel.org/r/20240901182244.45543-1-riyandhiman14@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: core: Calculate size from pointerRiyan Dhiman1-1/+1
Calculate the size from pointer instead of struct to adhere to linux kernel coding style. Issue reported by checkpatch. This commit has no functional changes. Signed-off-by: Riyan Dhiman <riyandhiman14@gmail.com> Link: https://lore.kernel.org/r/20240901173309.7124-1-riyandhiman14@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: cqhci: Make use of cqhci_halted() routineSeunghwan Baek1-7/+7
Make use of cqhci_halted() in couple places to avoid open-coding. Signed-off-by: Seunghwan Baek <sh8267.baek@samsung.com> Reviewed-by: Ritesh Harjani <ritesh.list@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240829061823.3718-3-sh8267.baek@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: Merge branch fixes into nextUlf Hansson1-1/+1
Merge the mmc fixes for v6.11-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.12. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: cqhci: Fix checking of CQHCI_HALT stateSeunghwan Baek1-1/+1
To check if mmc cqe is in halt state, need to check set/clear of CQHCI_HALT bit. At this time, we need to check with &, not &&. Fixes: a4080225f51d ("mmc: cqhci: support for command queue enabled host") Cc: stable@vger.kernel.org Signed-off-by: Seunghwan Baek <sh8267.baek@samsung.com> Reviewed-by: Ritesh Harjani <ritesh.list@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240829061823.3718-2-sh8267.baek@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: core: Replace the argument of mmc_sd_switch() with definesChanwoo Lee2-7/+9
Replace with already defined values for readability. While at it, let's also change the mode-parameter from an int to bool, as the only used values are 0 or 1. Signed-off-by: Chanwoo Lee <cw9316.lee@samsung.com> Link: https://lore.kernel.org/r/20240829024709.402285-1-cw9316.lee@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: dw_mmc-rockchip: Add support for rk3576 SoCsDetlev Casanova1-5/+43
On rk3576 the tunable clocks are inside the controller itself, removing the need for the "ciu-drive" and "ciu-sample" clocks. That makes it a new type of controller that has its own dt_parse function. Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/010201919997044d-c3a008d1-afbc-462f-a928-fc1ece785bdb-000000@eu-west-1.amazonses.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-09-03mmc: dw_mmc-rockchip: Add internal phase supportShawn Lin1-11/+160
Some Rockchip devices put the phase settings into the dw_mmc controller. When the feature is present, the ciu-drive and ciu-sample clocks are not used and the phase configuration is done directly through the mmc controller. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/010201919996fdae-8a9f843e-00a8-4131-98bf-a9da4ed04bfd-000000@eu-west-1.amazonses.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-29dma-mapping: don't return errors from dma_set_max_seg_sizeChristoph Hellwig1-1/+2
A NULL dev->dma_parms indicates either a bus that is not DMA capable or grave bug in the implementation of the bus code. There isn't much the driver can do in terms of error handling for either case, so just warn and continue as DMA operations will fail anyway. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC
2024-08-28mmc: Merge branch fixes into nextUlf Hansson2-2/+3
Merge the mmc fixes for v6.11-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.12. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-28mmc: dw_mmc: Fix IDMAC operation with pages bigger than 4KSam Protsenko1-2/+2
Commit 616f87661792 ("mmc: pass queue_limits to blk_mq_alloc_disk") [1] revealed the long living issue in dw_mmc.c driver, existing since the time when it was first introduced in commit f95f3850f7a9 ("mmc: dw_mmc: Add Synopsys DesignWare mmc host driver."), also making kernel boot broken on platforms using dw_mmc driver with 16K or 64K pages enabled, with this message in dmesg: mmcblk: probe of mmc0:0001 failed with error -22 That's happening because mmc_blk_probe() fails when it calls blk_validate_limits() consequently, which returns the error due to failed max_segment_size check in this code: /* * The maximum segment size has an odd historic 64k default that * drivers probably should override. Just like the I/O size we * require drivers to at least handle a full page per segment. */ ... if (WARN_ON_ONCE(lim->max_segment_size < PAGE_SIZE)) return -EINVAL; In case when IDMAC (Internal DMA Controller) is used, dw_mmc.c always sets .max_seg_size to 4 KiB: mmc->max_seg_size = 0x1000; The comment in the code above explains why it's incorrect. Arnd suggested setting .max_seg_size to .max_req_size to fix it, which is also what some other drivers are doing: $ grep -rl 'max_seg_size.*=.*max_req_size' drivers/mmc/host/ | \ wc -l 18 This change is not only fixing the boot with 16K/64K pages, but also leads to a better MMC performance. The linear write performance was tested on E850-96 board (eMMC only), before commit [1] (where it's possible to boot with 16K/64K pages without this fix, to be able to do a comparison). It was tested with this command: # dd if=/dev/zero of=somefile bs=1M count=500 oflag=sync Test results are as follows: - 4K pages, .max_seg_size = 4 KiB: 94.2 MB/s - 4K pages, .max_seg_size = .max_req_size = 512 KiB: 96.9 MB/s - 16K pages, .max_seg_size = 4 KiB: 126 MB/s - 16K pages, .max_seg_size = .max_req_size = 2 MiB: 128 MB/s - 64K pages, .max_seg_size = 4 KiB: 138 MB/s - 64K pages, .max_seg_size = .max_req_size = 8 MiB: 138 MB/s Unfortunately, SD card controller is not enabled in E850-96 yet, so it wasn't possible for me to run the test on some cheap SD cards to check this patch's impact on those. But it's possible that this change might also reduce the writes count, thus improving SD/eMMC longevity. All credit for the analysis and the suggested solution goes to Arnd. [1] https://lore.kernel.org/all/20240215070300.2200308-18-hch@lst.de/ Fixes: f95f3850f7a9 ("mmc: dw_mmc: Add Synopsys DesignWare mmc host driver.") Suggested-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Linux Kernel Functional Testing <lkft@linaro.org> Closes: https://lore.kernel.org/all/CA+G9fYtddf2Fd3be+YShHP6CmSDNcn0ptW8qg+stUKW+Cn0rjQ@mail.gmail.com/ Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240306232052.21317-1-semen.protsenko@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-28mmc: sdhci-of-dwcmshc: Add hw_reset() support for BlueField-3 SoCLiming Sun1-1/+28
The eMMC RST_N register is implemented as secure register on the BlueField-3 SoC and controlled by TF-A. This commit adds the hw_reset() support which sends an SMC call to TF-A for the eMMC HW reset. Reviewed-by: David Thompson <davthompson@nvidia.com> Signed-off-by: Liming Sun <limings@nvidia.com> Link: https://lore.kernel.org/r/20240827164016.237617-1-limings@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-28mmc: sdhci-of-aspeed: fix module autoloadingLiao Chen1-0/+1
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded based on the alias from of_device_id table. Signed-off-by: Liao Chen <liaochen4@huawei.com> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au> Fixes: bb7b8ec62dfb ("mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240826124851.379759-1-liaochen4@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: block: register RPMB partition with the RPMB subsystemJens Wiklander1-2/+240
Register eMMC RPMB partition with the RPMB subsystem and provide an implementation for the RPMB access operations abstracting the actual multi step process. Add a callback to extract the needed device information at registration to avoid accessing the struct mmc_card at a later stage as we're not holding a reference counter for this struct. Taking the needed reference to md->disk in mmc_blk_alloc_rpmb_part() instead of in mmc_rpmb_chrdev_open(). This is needed by the route_frames() function pointer in struct rpmb_ops. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Manuel Traut <manut@mecka.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20240814153558.708365-3-jens.wiklander@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: Merge branch fixes into nextUlf Hansson2-9/+17
Merge the mmc fixes for v6.11-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.12. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: core: apply SD quirks earlier during probeJonathan Bell2-9/+17
Applying MMC_QUIRK_BROKEN_SD_CACHE is broken, as the card's SD quirks are referenced in sd_parse_ext_reg_perf() prior to the quirks being initialized in mmc_blk_probe(). To fix this problem, let's split out an SD-specific list of quirks and apply in mmc_sd_init_card() instead. In this way, sd_read_ext_regs() to has the available information for not assigning the SD_EXT_PERF_CACHE as one of the (un)supported features, which in turn allows mmc_sd_init_card() to properly skip execution of sd_enable_cache(). Fixes: c467c8f08185 ("mmc: Add MMC_QUIRK_BROKEN_SD_CACHE for Kingston Canvas Go Plus from 11/2019") Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com> Co-developed-by: Keita Aihara <keita.aihara@sony.com> Signed-off-by: Keita Aihara <keita.aihara@sony.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Avri Altman <avri.altman@wdc.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240820230631.GA436523@sony.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: mtk-sd: Improve data type in msdc_timeout_cal()Thorsten Blum1-6/+5
The local variable clk_ns uses at most 32 bits and can be a u32. Replace the 64-by-32 do_div() division with a standard divison. Since do_div() casts the divisor to u32 anyway, changing the data type of clk_ns to u32 also removes the following Coccinelle/coccicheck warning reported by do_div.cocci: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead Use min_t(u32,,) to simplify the code and improve its readability. Signed-off-by: Thorsten Blum <thorsten.blum@toblux.com> Link: https://lore.kernel.org/r/20240818142300.64156-2-thorsten.blum@toblux.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: Add support for Sophgo SG2042Chen Wang1-7/+118
Add support for the mmc controller of Sophgo SG2042. SG2042 uses Synopsys PHY the same as TH1520 so we reuse the tuning logic from TH1520. Besides this, this patch implement some SG2042 specific work, such as clocks and reset ops. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/eb21847528a6487af54bb80f1ce94adff289cdb0.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: add dwcmshc_pltfm_dataChen Wang1-33/+48
Abstract dwcmshc_pltfm_data to hold the sdhci_pltfm_data plus some comoon operations of soc such as init/postinit. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/cb2c68c594286e9588c53acb76163e60c140c02b.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: factor out code into dwcmshc_rk35xx_initChen Wang1-18/+16
Continue factor out code fron probe into dwcmshc_rk35xx_init. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/4f1f2fa403ce7f0b4d79afb7d7e8a1690cde5d6c.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: factor out code for th1520_init()Chen Wang1-21/+30
Different socs have initialization operations in the probe process, which are summarized as functions. This patch first factor out init function for th1520. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Drew Fustini <drew@pdp7.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/23c6a81052a6dd3660d60348731229d60a209b32.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: move two rk35xx functionsChen Wang1-45/+45
This patch just move dwcmshc_rk35xx_init() and dwcmshc_rk35xx_postinit() to put the functions of rk35xx together as much as possible. This change is an intermediate process before further modification. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/54204702d5febd3e867eb3544c36919fe4140a88.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-dwcmshc: add common bulk optional clocks supportChen Wang1-42/+48
In addition to the required core clock and optional bus clock, the soc will expand its own clocks, so the bulk clock mechanism is abstracted. Note, I call the bulk clocks as "other clocks" due to the bus clock has been called as "optional". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Drew Fustini <drew@pdp7.com> # TH1520 Tested-by: Inochi Amaoto <inochiama@outlook.com> # Duo and Huashan Pi Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/e57e8c51da81f176b49608269a884f840903e78e.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: renesas_sdhi: Add RZ/V2H(P) compatible stringLad Prabhakar1-0/+1
The SD/MMC block on the RZ/V2H(P) ("R9A09G057") SoC is similar to that of the R-Car Gen3, but it has some differences: - HS400 is not supported. - It has additional SD_STATUS register to control voltage, power enable and reset. - It supports fixed address mode. To accommodate these differences, a SoC-specific 'renesas,sdhi-r9a09g057' compatible string is added. Note for RZ/V2H(P), we are using the `of_rzg2l_compatible` OF data as it already handles no HS400 and fixed address mode support. Since the SDxIOVS and SDxPWEN pins can always be used as GPIO pins on the RZ/V2H(P) SoC, no driver changes are done to control the SD_STATUS register. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20240724182119.652080-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: tmio: Use MMC core APIs to control the vqmmc regulatorLad Prabhakar1-4/+3
Use the mmc_regulator_enable_vqmmc() and mmc_regulator_disable_vqmmc() APIs to enable/disable the vqmmc regulator. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Link: https://lore.kernel.org/r/20240724182119.652080-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-pxav2: Remove unnecessary null pointer checkDoug Brown1-1/+1
There is no need to check for a null mrq->cmd in pxav1_request_done. mmc_request_done already assumes it's not null, and it's always called in this path by every SDHCI driver. This was caught by Smatch. Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/9ddaef2a-05bb-4fe7-98c5-da40a0813027@stanley.mountain/ Signed-off-by: Doug Brown <doug@schmorgal.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240714155510.48880-1-doug@schmorgal.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-26mmc: sdhci-of-ma35d1: Add Nuvoton MA35D1 SDHCI driverShan-Chun Hung3-0/+327
Add the SDHCI driver for the MA35D1 platform. It is based upon the SDHCI interface, but requires some extra initialization. Signed-off-by: Shan-Chun Hung <shanchun1218@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20240716004527.20378-3-shanchun1218@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-08-20mmc: mmc_test: Fix NULL dereference on allocation failureDan Carpenter1-4/+5
If the "test->highmem = alloc_pages()" allocation fails then calling __free_pages(test->highmem) will result in a NULL dereference. Also change the error code to -ENOMEM instead of returning success. Fixes: 2661081f5ab9 ("mmc_test: highmem tests") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/8c90be28-67b4-4b0d-a105-034dc72a0b31@stanley.mountain Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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