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path: root/drivers/mmc/host/sunxi-mmc.c
AgeCommit message (Expand)AuthorFilesLines
2018-10-08mmc: sunxi: Use new timing mode for A64 eMMC controllerChen-Yu Tsai1-0/+1
2018-10-08mmc: sunxi: Clarify new timing mode usage and implementationChen-Yu Tsai1-6/+17
2018-08-01mmc: sunxi: remove output of virtual base addressAndre Przywara1-1/+4
2018-08-01mmc: sunxi: allow 3.3V DDR when DDR is availableIcenowy Zheng1-1/+1
2018-07-05mmc: sunxi: Disable irq during pm_suspendStefan Mavrodiev1-0/+7
2018-05-30mmc: sunxi: Use ifdef rather than __maybe_unusedUlf Hansson1-2/+4
2018-05-29mmc: sunxi: mark PM functions as __maybe_unusedArnd Bergmann1-2/+2
2018-05-02mmc: sunxi: Drop the init / reset of the controller from set_iosMaxime Ripard1-7/+4
2018-05-02mmc: sunxi: Add runtime_pm supportMaxime Ripard1-0/+48
2018-05-02mmc: sunxi: Move the card power configuration to a functionMaxime Ripard1-15/+25
2018-05-02mmc: sunxi: Move clock configuration to a functionMaxime Ripard1-15/+18
2018-05-02mmc: sunxi: Move bus width configuration to a functionMaxime Ripard1-12/+17
2018-05-02mmc: sunxi: Change sunxi_mmc_init_host argument typeMaxime Ripard1-3/+2
2018-05-02mmc: sunxi: Reorder the headersMaxime Ripard1-23/+20
2018-03-15mmc: sunxi: Set our device drvdata earlierMaxime Ripard1-1/+1
2018-03-15mmc: sunxi: Move the reset deassertion before enabling the clocksMaxime Ripard1-18/+18
2018-03-15mmc: sunxi: Move resources management to separate functionsMaxime Ripard1-60/+82
2017-12-15mmc: sunxi-mmc: Handle return value of platform_get_irqArvind Yadav1-0/+5
2017-12-11mmc: sunxi: fix mojibake in module metadataAdam Borowski1-2/+2
2017-10-30mmc: sunxi: drop superfluous error messageWolfram Sang1-4/+1
2017-08-30mmc: sunxi: Reset the device at probe timeMaxime Ripard1-1/+1
2017-08-30mmc: sunxi: Fix clock rate passed to sunxi_mmc_clk_set_phaseChen-Yu Tsai1-1/+5
2017-08-30mmc: sunxi: fix support for new timings mode only SoCsIcenowy Zheng1-1/+1
2017-08-30mmc: sunxi: Fix NULL pointer reference on clk_delaysChen-Yu Tsai1-0/+5
2017-08-30mmc: sunxi: Add support for A83T eMMC (MMC2)Chen-Yu Tsai1-0/+8
2017-08-30mmc: sunxi: Support MMC DDR52 transfer mode with new timing modeChen-Yu Tsai1-12/+18
2017-08-30mmc: sunxi: Support controllers that can use both old and new timingsChen-Yu Tsai1-2/+43
2017-08-30mmc: sunxi: constify mmc_host_ops structuresJulia Lawall1-1/+1
2017-08-30mmc: sunxi: explicitly request exclusive reset controlPhilipp Zabel1-1/+2
2017-07-17mmc: sunxi: Keep default timing phase settings for new timing modeChen-Yu Tsai1-2/+6
2017-04-24mmc: use new core function mmc_get_dma_dirHeiner Kallweit1-11/+3
2017-04-24mmc: sunxi: change controller error info to debug levelIcenowy Zheng1-1/+1
2017-02-13mmc: sunxi: Add more debug informationsMaxime Ripard1-4/+19
2017-02-13mmc: sunxi: Add EMMC (MMC2) controller compatibleMaxime Ripard1-0/+8
2017-02-13mmc: sunxi: Mask DATA0 when updating the clockMaxime Ripard1-1/+13
2017-02-13mmc: sunxi: Enable the new timings for the A64 MMC controllersMaxime Ripard1-0/+6
2017-02-13mmc: sunxi: Always set signal delay to 0 for A64Maxime Ripard1-33/+17
2017-02-13mmc: sunxi: Gate the clock when rate is 0Maxime Ripard1-1/+4
2017-02-13mmc: sunxi: Fix clock frequency change sequenceMaxime Ripard1-4/+4
2016-11-29mmc: sunxi: Prevent against null dereference for vmmcMaxime Ripard1-5/+10
2016-09-26mmc: sunxi: add support for A64 mmc controllerIcenowy Zheng1-0/+79
2016-09-26mmc: sunxi-mmc: change idma descriptor to __le32Michael Weiser1-12/+15
2016-09-26mmc: sunxi: Check the value returned by clk_round_rateJean-Francois Moine1-3/+9
2016-09-26mmc: sunxi: sun4i / sun5i do not have sample clocksHans de Goede1-11/+24
2016-09-26mmc: sunxi: Factor out clock phase setting code into a helper functionHans de Goede1-28/+33
2016-09-26mmc: sunxi: Introduce a sunxi_mmc_cfg structHans de Goede1-32/+45
2016-09-26mmc: sunxi: Disable sample clks on removeHans de Goede1-0/+2
2016-06-02mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80Chen-Yu Tsai1-5/+0
2016-06-02mmc: sunxi: Fix DDR MMC timings for A80Chen-Yu Tsai1-2/+2
2016-04-28mmc: sunxi: Disable eMMC HS-DDR (MMC_CAP_1_8V_DDR) for Allwinner A80Chen-Yu Tsai1-0/+5
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