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path: root/drivers/mfd/lpc_ich.c
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2023-11-01mfd: lpc_ich: Mark *_gpio_offsets data with constAndy Shevchenko1-3/+3
There is no reason why the GPIO resource offsets should not be const. Mark them accordingly and update a qualifier in struct lpc_ich_gpio_info definition. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231024160650.3898959-1-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-11-01mfd: lpc_ich: Add a platform device for pinctrl DenvertonAndy Shevchenko1-0/+49
This is to cater the need in non-ACPI system whereby a platform device has to be created in order to bind with the Denverton pinctrl driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230926190834.932233-4-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-11-01mfd: lpc_ich: Move APL GPIO resources to a custom structureAndy Shevchenko1-11/+41
We are expecting more platforms that want to instantiate the GPIO device via P2SB. For them prepare the custom structure and move Apollo Lake data there. Refactor the code accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230926190834.932233-3-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-11-01mfd: lpc_ich: Make struct lpc_ich_priv use enum for chipset memberAndy Shevchenko1-13/+13
We have a specific enum for the supported chipsets. Make struct lpc_ich_priv use better type for the chipset member. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230926190834.932233-1-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2022-09-28mfd: Move from strlcpy with unused retval to strscpyWolfram Sang1-1/+1
Follow the advice of the below link and prefer 'strscpy' in this subsystem. Conversion is 1:1 because the return value is not used. Generated by a coccinelle script. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20220818210030.7012-1-wsa+renesas@sang-engineering.com
2022-07-14mfd: lpc_ich: Add support for pinctrl in non-ACPI systemTan Jui Nee1-1/+104
Add support for non-ACPI systems, such as system that uses Advanced Boot Loader (ABL) whereby a platform device has to be created in order to bind with pin control and GPIO. At the moment, Intel Apollo Lake In-Vehicle Infotainment (IVI) system requires a driver to hide and unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO. Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com> Co-developed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Henning Schild <henning.schild@siemens.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org>
2022-07-14mfd: lpc_ich: Switch to generic p2sb_bar()Andy Shevchenko1-19/+8
Instead of open coding p2sb_bar() functionality we are going to use generic library. There is one more user en route. This is more than just a clean-up. It also fixes a potential issue seen when SPI BAR is 64-bit. The current code works if and only if the PCI BAR of the hidden device is inside 4G address space. In case when firmware decides to go above 4G, we will get a wrong address. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Henning Schild <henning.schild@siemens.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org>
2022-07-14mfd: lpc_ich: Factor out lpc_ich_enable_spi_write()Andy Shevchenko1-17/+14
Factor out duplicate code to lpc_ich_enable_spi_write() helper function. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Henning Schild <henning.schild@siemens.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org>
2022-02-14mtd: spi-nor: intel-spi: Disable write protection only if askedMika Westerberg1-5/+54
Currently the driver tries to disable the BIOS write protection automatically even if this is not what the user wants. For this reason modify the driver so that by default it does not touch the write protection. Only if specifically asked by the user (setting writeable=1 command line parameter) the driver tries to disable the BIOS write protection. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mauro Lima <mauro.lima@eclypsium.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220209122706.42439-2-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-07-20mfd: lpc_ich: Enable GPIO driver for DH89xxCCChris Blake1-0/+1
Based on the Intel Datasheet for the DH89xxCC PCH, the GPIO driver is the same as ICH_v5_GPIO, minus the fact the DH89xxCC also has blink support. However, blink support isn't supported by the GPIO driver so we should use ICH_v5_GPIO. Tested and working on a Meraki MX100-HW. Signed-off-by: Chris Blake <chrisrblake93@gmail.com> Co-developed-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 294Thomas Gleixner1-9/+1
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation this program is distributed in the hope that it [would] be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 9 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.804956444@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-01-08mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Apollo LakeMika Westerberg1-5/+0
Just to be on the safe side, don't touch the bit. If write access to the flash chip is needed, the BIOS needs to enable it explicitly. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-10-24mfd: lpc_ich: Avoton/Rangeley uses SPI_BYT methodJoakim Tjernlund1-0/+1
Avoton/Rangeley are based on Silvermount micro-architecture, like Bay Trail, and uses the INTEL_SPI_BYT method to drive SPI. Cc: stable@vger.kernel.org Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-09-05mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/BroadwellMika Westerberg1-10/+0
At least on Lenovo Thinkpad Yoga, the BIOS seems to monitor the SPI-NOR write protection bit and if it is flipped to read/write it assumes the BIOS configuration was changed on next reboot. It then, for unknown reasons, resets the BIOS settings back to default. We can prevent this by just leaving the write protection bit intact and let the SPI-NOR driver know whether the device is writable or not. In case of this particular Lenovo the SPI-NOR flash will be exposed as read-only. Fixes: ff00d7a32a1b ("mfd: lpc_ich: Add support for SPI serial flash host controller") Link: https://bugzilla.kernel.org/show_bug.cgi?id=195951 Reported-by: Abdó Roig-Marange <abdo.roig@gmail.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-04-27mfd: lpc_ich: Add support for Intel Gemini Lake SoCMika Westerberg1-0/+6
Like Intel Apollo Lake, Gemini Lake exposes the serial SPI flash device BAR through hidden P2SB PCI device. We use the same mechanism than Apollo Lake to read the BAR and pass it to the driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-04-27mfd: lpc_ich: Add PCI ID for Intel Cougar Mountain SoCPriyalee Kushwaha1-0/+6
This patches adds the first minimal support to the upstream Linux tree. Signed-off-by: Priyalee Kushwaha <priyalee.kushwaha@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-02-13mfd: lpc_ich: Enable watchdog on Intel Apollo Lake PCHTan Jui Nee1-0/+1
Assign iTCO_version which effectively enables watchdog device on Intel Apollo Lake PCH. Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-02-13mfd: lpc_ich: Remove useless comments in core partAndy Shevchenko1-16/+0
First of all, remove stalled references to datasheets. If someone knows the document numbers, it would be added later. Second, remove FSF snail address since it's subject to change. Actual information can be found on FSF site on the internet. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-01-03mfd: lpc_ich: Add support for Intel Apollo Lake SoCMika Westerberg1-0/+39
Intel Apollo Lake SoC exposes serial SPI flash through the LPC device. The SPI flash host controller is not discoverable through PCI config cycles because P2SB (function 0 of the device 13) is hidden by the BIOS. We unhide the device briefly in order to read BAR 0 of the SPI host controller. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-01-03mfd: lpc_ich: Add support for SPI serial flash host controllerMika Westerberg1-0/+92
Many Intel CPUs including Haswell, Broadwell and Baytrail have SPI serial flash host controller as part of the LPC device. This will populate an MFD cell suitable for the SPI host controller driver if we know that the LPC device has one. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-21mfd: lpc_ich: Use gpio-ich driver for 8-series and 9-series Intel PCH devicesDan Gora1-0/+2
The Intel 8-series and 9-series PCH devices, described by the descriptors LPC_LPT and LPC_9S although codenamed 'lynxpoint' do not use the same GPIO register layout which is used by the gpio-lynxpoint driver. They use the same ICH_V5_GPIO layout as the gpio-ich driver. See: http://www.intel.com/content/www/us/en/chipsets/8-series-chipset-pch-datasheet.html http://www.intel.com/content/www/us/en/chipsets/9-series-chipset-pch-datasheet.html The devices described by "Mobile 4th Generation Intel Core Processor Family I/O" manual use the gpio-lynxpoint driver and are described by the LPC_LPT_LP descriptor. See: http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html Signed-off-by: Dan Gora <dg@adax.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-09-29mfd: lpc_ich: Do not create iTCO watchdog when WDAT table existsMika Westerberg1-0/+4
ACPI WDAT table is the preferred way to use hardware watchdog over the native iTCO_wdt. Windows only uses this table for its hardware watchdog implementation so we should be relatively safe to trust it has been validated by OEMs Prevent iTCO watchdog creation if we detect that there is ACPI WDAT table. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2015-11-24mfd: lpc_ich: Intel device IDs for PCHAlexandra Yates1-0/+15
Adding Intel codename Lewisburg platform device IDs for PCH. Signed-off-by: Alexandra Yates <alexandra.yates@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-10-30mfd: lpc_ich: Separate device cells for clarityAaron Sierra1-24/+18
The lpc_ich_cells array gives the wrong impression about the relationship between the watchdog and GPIO devices. They are completely distinct devices, so this patch separates the array into distinct mfd_cell structs per device. A side effect of removing the array, is that the lpc_cells enum is no longer needed. Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-08-11mfd: watchdog: iTCO_wdt: Expose watchdog properties using platform dataMatt Fleming1-3/+29
Intel Sunrisepoint (Skylake PCH) has the iTCO watchdog accessible across the SMBus, unlike previous generations of PCH/ICH where it was on the LPC bus. Because it's on the SMBus, it doesn't make sense to pass around a 'struct lpc_ich_info', and leaking the type of bus into the iTCO watchdog driver is kind of backwards anyway. This change introduces a new 'struct itco_wdt_platform_data' for use inside the iTCO watchdog driver and by the upcoming Intel Sunrisepoint code, which neatly avoids having to include lpc_ich headers in the i801 i2c driver. This change is overdue because lpc_ich_info has already found its way into other TCO watchdog users, notably the intel_pmc_ipc driver where the watchdog actually isn't on the LPC bus as far as I can see. A simple translation layer is provided for converting from the existing 'struct lpc_ich_info' inside the lpc_ich mfd driver. Signed-off-by: Matt Fleming <matt.fleming@intel.com> Acked-by: Darren Hart <dvhart@linux.intel.com> [drivers/x86 refactoring] Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-06-22mfd: lpc_ich: Assign subdevice ids automaticallyMika Westerberg1-4/+4
Using -1 as platform device id means that the platform driver core will not assign any id to the device (the device name will not have id at all). This results problems on systems that have multiple PCHs (Platform Controller HUBs) because all of them also include their own copy of LPC device. All the subsequent device creations will fail because there already exists platform device with the same name. Fix this by passing PLATFORM_DEVID_AUTO as platform device id. This makes the platform device core to allocate new ids automatically. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-04-09mfd: lpc_ich: Sort IDsAndy Shevchenko1-9/+9
The patch sorts IDs in the table for easier maintenance. There is no functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-03-30mfd: lpc_ich: Sort IDsAndy Shevchenko1-86/+86
This patch just sorts IDs in the table for better maintenance. There is no functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-09-26mfd: lpc_ich: Add Device IDs for Intel 9 Series PCHJames Ralston1-0/+11
This patch adds the LPC Device IDs for the Intel 9 Series PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-09-26mfd: lpc_ich: Add PCI ID for Intel BraswellAlan Cox1-0/+6
This is the same as used in Baytrail so add the new PCI ID to the driver's list of supported IDs. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-06-03mfd: lpc_ich: Enable GPIO for Panther PointGuenter Roeck1-0/+1
Panther Point PCH GPIO configuration is similar to V5 PCHs. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: lpc_ich: Add support for Intel Bay Trail SoCPeter Tyser1-0/+6
This patch adds the LPC Controller Device IDs for Watchdog and GPIO for the Intel Bay Trail Atom SoC. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: lpc_ich: Add support for NM10 GPIOPeter Tyser1-0/+1
The NM10's GPIO is compatible with ICH v7 GPIO. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Dan Weinlader <danw@vs-networks.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: lpc_ich: Change Avoton to iTCO v3Peter Tyser1-1/+1
The register layout of the Avoton is compatible with the iTCO v3 register layout. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Rajat Jain <rajatjain@juniper.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: lpc_ich: Add support for iTCO v3Peter Tyser1-14/+67
Some newer Atom CPUs, eg Avoton and Bay Trail, use slightly different register layouts for the iTCO than the current v1 and v2 iTCO. Differences from previous iTCO versions include: - The ACPI space is enabled in the "ACPI base address" register instead of the "ACPI control register" - The "no reboot" functionality is set in the "Power Management Configuration" register instead of the "General Control and Status" (GCS) register or PCI configuration space. - The "ACPI Control Register" is not present on v3. The "Power Management Configuration Base Address" register resides at the same address is Avoton/Bay Trail. To differentiate these newer chipsets create a new v3 iTCO version and update the MFD driver to support them. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Rajat Jain <rajatjain@juniper.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: lpc_ich: Remove lpc_ich_cfg struct usePeter Tyser1-31/+32
Future chipsets will use different register layouts that don't map cleanly to the lpc_ich_cfg fields. Remove the lpc_ich_cfg struct and add explicit fields to the higher level lpc_ich_priv structure. This change should have no functional impact. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Rajat Jain <rajatjain@juniper.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: lpc_ich: Only configure watchdog or GPIO when presentPeter Tyser1-6/+10
Some chipsets don't currently have GPIO support enabled. For these chipsets don't go through the process of initializing the GPIO region. Make the same change for the watchdog initialization for chipsets which may not enable the WDT in the future. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Rajat Jain <rajatjain@juniper.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: lpc_ich: Fix ACPI enable bitmaskPeter Tyser1-1/+1
The original bitmask of 0x10 was incorrect and would result in a write to a reserved read-only bit instead of enabling the ACPI I/O region. Update it to the proper value of 0x80. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Rajat Jain <rajatjain@juniper.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: lpc_ich: Add support for Intel Avoton GPIOsVincent Donnefort1-0/+1
Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-19mfd: Delete non-required instances of include <linux/init.h>Paul Gortmaker1-1/+0
None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-01-21mfd: Remove DEFINE_PCI_DEVICE_TABLE macroJingoo Han1-1/+1
Don't use DEFINE_PCI_DEVICE_TABLE macro, because this macro is not preferred. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2013-11-27mfd: lpc_ich: Fix Wildcat Point info name fieldJames Ralston1-1/+1
Fix a copy paste error from the WPT support initial patch. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2013-11-04mfd: lpc_ich: Add Device IDs for Intel Wildcat Point-LP PCHJames Ralston1-0/+13
This patch adds the TCO Watchdog Device IDs for the Intel Wildcat Point-LP PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2013-10-23mfd: lpc_ich: Remove unnecessary pci_set_drvdata()Jingoo Han1-2/+0
The driver core clears the driver data to NULL after device_release or on probe failure. Thus, it is not needed to manually clear the device driver data to NULL. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2013-08-01mfd: lpc_ich: Staticize struct 'lpc_chipset_info'Jingoo Han1-1/+1
'lpc_chipset_info' is used only in this file. Fix the following sparse warning: drivers/mfd/lpc_ich.c:216:21: warning: symbol 'lpc_chipset_info' was not declared. Should it be static? Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2013-06-20mfd: lpc_ich: iTCO_wdt patch for Intel Coleto Creek DeviceIDsSeth Heasley1-0/+7
This patch adds the LPC Controller DeviceIDs for iTCO Watchdog for the Intel Coleto Creek PCH. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2013-06-18mfd: lpc_ich: Convert to module_pci_driverLibo Chen1-12/+1
use module_pci_driver instead of init/exit, make code cleaner. Signed-off-by: Libo Chen <libo.chen@huawei.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2013-06-11mfd: lpc_ich: Add support for Intel Avoton SoCJames Ralston1-0/+10
This patch adds the LPC Controller Device IDs for Watchdog and GPIO for Intel Avoton SoC, to the lpc_ich driver. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2013-02-15mfd: lpc_ich: Use devres API to allocate private dataAaron Sierra1-5/+2
And fix a kzalloc argument inversion bug while converting to devres. Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
2013-02-14mfd: lpc_ich: Add Device IDs for Intel Wellsburg PCHJames Ralston1-0/+38
This patch adds the Watchdog Timer Device IDs for the Intel Wellsburg PCH Signed-off-by: James Ralston <james.d.ralston@intel.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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