index
:
kernel/linux.git
linux-2.6.11.y
linux-2.6.12.y
linux-2.6.13.y
linux-2.6.14.y
linux-2.6.15.y
linux-2.6.16.y
linux-2.6.17.y
linux-2.6.18.y
linux-2.6.19.y
linux-2.6.20.y
linux-2.6.21.y
linux-2.6.22.y
linux-2.6.23.y
linux-2.6.24.y
linux-2.6.25.y
linux-2.6.26.y
linux-2.6.27.y
linux-2.6.28.y
linux-2.6.29.y
linux-2.6.30.y
linux-2.6.31.y
linux-2.6.32.y
linux-2.6.33.y
linux-2.6.34.y
linux-2.6.35.y
linux-2.6.36.y
linux-2.6.37.y
linux-2.6.38.y
linux-2.6.39.y
linux-3.0.y
linux-3.1.y
linux-3.10.y
linux-3.11.y
linux-3.12.y
linux-3.13.y
linux-3.14.y
linux-3.15.y
linux-3.16.y
linux-3.17.y
linux-3.18.y
linux-3.19.y
linux-3.2.y
linux-3.3.y
linux-3.4.y
linux-3.5.y
linux-3.6.y
linux-3.7.y
linux-3.8.y
linux-3.9.y
linux-4.0.y
linux-4.1.y
linux-4.10.y
linux-4.11.y
linux-4.12.y
linux-4.13.y
linux-4.14.y
linux-4.15.y
linux-4.16.y
linux-4.17.y
linux-4.18.y
linux-4.19.y
linux-4.2.y
linux-4.20.y
linux-4.3.y
linux-4.4.y
linux-4.5.y
linux-4.6.y
linux-4.7.y
linux-4.8.y
linux-4.9.y
linux-5.0.y
linux-5.1.y
linux-5.10.y
linux-5.11.y
linux-5.12.y
linux-5.13.y
linux-5.14.y
linux-5.15.y
linux-5.16.y
linux-5.17.y
linux-5.18.y
linux-5.19.y
linux-5.2.y
linux-5.3.y
linux-5.4.y
linux-5.5.y
linux-5.6.y
linux-5.7.y
linux-5.8.y
linux-5.9.y
linux-6.0.y
linux-6.1.y
linux-6.10.y
linux-6.11.y
linux-6.12.y
linux-6.2.y
linux-6.3.y
linux-6.4.y
linux-6.5.y
linux-6.6.y
linux-6.7.y
linux-6.8.y
linux-6.9.y
linux-rockchip-6.1.y
linux-rockchip-6.5.y
linux-rolling-lts
linux-rolling-stable
master
Linux kernel stable tree (mirror)
Andrey V.Kosteltsev
summary
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log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
media
/
i2c
Age
Commit message (
Expand
)
Author
Files
Lines
2020-12-07
media: ccs: Add support for obtaining C-PHY configuration from firmware
Sakari Ailus
1
-0
/
+4
2020-12-07
media: ccs-pll: Print pixel rates
Sakari Ailus
1
-0
/
+5
2020-12-07
media: ccs: Print written register values
Sakari Ailus
1
-0
/
+4
2020-12-07
media: ccs: Add support for DDR OP SYS and OP PIX clocks
Sakari Ailus
1
-1
/
+8
2020-12-07
media: ccs-pll: Add support for DDR OP system and pixel clocks
Sakari Ailus
2
-20
/
+46
2020-12-07
media: ccs: Dual PLL support
Sakari Ailus
2
-3
/
+51
2020-12-07
media: ccs-pll: Add trivial dual PLL support
Sakari Ailus
2
-22
/
+196
2020-12-07
media: ccs-pll: Separate VT divisor limit calculation from the rest
Sakari Ailus
1
-27
/
+37
2020-12-07
media: ccs-pll: Fix VT post-PLL divisor calculation
Sakari Ailus
1
-5
/
+7
2020-12-07
media: ccs-pll: Make VT divisors 16-bit
Sakari Ailus
1
-26
/
+25
2020-12-07
media: ccs-pll: Rework bounds checks
Sakari Ailus
2
-57
/
+95
2020-12-07
media: ccs-pll: Print relevant information on PLL tree
Sakari Ailus
1
-19
/
+66
2020-12-07
media: ccs-pll: Better separate OP and VT sub-tree calculation
Sakari Ailus
1
-23
/
+31
2020-12-07
media: ccs-pll: Check for derating and overrating, support non-derating sensors
Sakari Ailus
3
-29
/
+64
2020-12-07
media: ccs-pll: Split off VT subtree calculation
Sakari Ailus
1
-124
/
+131
2020-12-07
media: ccs-pll: Add C-PHY support
Sakari Ailus
1
-9
/
+26
2020-12-07
media: ccs-pll: Add sanity checks
Sakari Ailus
1
-0
/
+9
2020-12-07
media: ccs-pll: Add support flexible OP PLL pixel clock divider
Sakari Ailus
3
-8
/
+23
2020-12-07
media: ccs-pll: Support two cycles per pixel on OP domain
Sakari Ailus
3
-6
/
+16
2020-12-07
media: ccs-pll: Add support for extended input PLL clock divider
Sakari Ailus
3
-1
/
+7
2020-12-07
media: ccs-pll: Add support for decoupled OP domain calculation
Sakari Ailus
4
-19
/
+23
2020-12-07
media: ccs: Add support for lane speed model
Sakari Ailus
1
-1
/
+10
2020-12-07
media: ccs-pll: Add support for lane speed model
Sakari Ailus
2
-11
/
+31
2020-12-07
media: ccs-pll: Use explicit 32-bit unsigned type
Sakari Ailus
1
-2
/
+2
2020-12-07
media: ccs-pll: Fix check for PLL multiplier upper bound
Sakari Ailus
1
-2
/
+1
2020-12-07
media: ccs-pll: Fix comment on check against maximum PLL multiplier
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
Sakari Ailus
1
-2
/
+9
2020-12-07
media: ccs-pll: Fix condition for pre-PLL divider lower bound
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Begin calculation from OP system clock frequency
Sakari Ailus
1
-8
/
+4
2020-12-07
media: ccs-pll: Use the BIT macro
Sakari Ailus
1
-2
/
+5
2020-12-07
media: ccs-pll: Document the structs in the header as well as the function
Sakari Ailus
1
-0
/
+89
2020-12-07
media: ccs-pll: Move the flags field down, away from 8-bit fields
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
Sakari Ailus
3
-3
/
+4
2020-12-07
media: ccs-pll: Remove parallel bus support
Sakari Ailus
2
-15
/
+4
2020-12-07
media: ccs-pll: End search if there are no better values available
Sakari Ailus
1
-2
/
+8
2020-12-07
media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor
Sakari Ailus
1
-2
/
+2
2020-12-07
media: ccs-pll: Split limits and PLL configuration into front and back parts
Sakari Ailus
3
-188
/
+209
2020-12-07
media: ccs-pll: Don't use div_u64 to divide a 32-bit number
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs: Fix return value from probe
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs: avoid printing an uninitialized variable
Arnd Bergmann
1
-2
/
+1
2020-12-07
media: i2c: fix an uninitialized error code
Arnd Bergmann
1
-1
/
+3
2020-12-03
media: ccs: Use all regulators
Sakari Ailus
2
-8
/
+24
2020-12-03
media: ccs: Remove unnecessary delays from power-up sequence
Sakari Ailus
1
-2
/
+0
2020-12-03
media: ccs: Use longer pre-I²C sleep for CCS compliant devices
Sakari Ailus
1
-1
/
+6
2020-12-03
media: ccs: Wrap long lines, unwrap short ones
Sakari Ailus
1
-27
/
+18
2020-12-03
media: ccs: Clean up runtime PM usage
Sakari Ailus
1
-5
/
+2
2020-12-03
media: ccs: Use static data read-only registers
Sakari Ailus
1
-4
/
+60
2020-12-03
media: ccs: Add support for manufacturer regs from sensor and module files
Sakari Ailus
3
-22
/
+97
2020-12-03
media: ccs: Allow range in between I²C retries
Sakari Ailus
1
-2
/
+2
2020-12-03
media: ccs: Change my e-mail address
Sakari Ailus
8
-11
/
+11
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