summaryrefslogtreecommitdiff
path: root/drivers/irqchip
AgeCommit message (Collapse)AuthorFilesLines
2015-07-16irqchip/mmp: Prepare icu_mux_irq_demux for irq argument removalThomas Gleixner1-1/+2
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr>
2015-07-16irqchip/keystone: Prepare keystone_irq_handler for irq argument removalThomas Gleixner1-1/+2
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr>
2015-07-16irqchip/imgpdc: Prepare pdc_intc_perip_isr for irq argument removalThomas Gleixner1-1/+2
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr>
2015-07-16irqchip/brcmstb-l2: Prepare brcmstb_l2_intc_irq_handle for irq argument removalThomas Gleixner1-1/+3
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr>
2015-07-16irqchip/exynos: Prepare combiner_handle_cascade_irq for irq argument removalThomas Gleixner1-1/+3
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr>
2015-07-12Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-10/+0
Pull MIPS fixes from Ralf Baechle: "A fair number of 4.2 fixes also because Markos opened the flood gates. - Patch up the math used calculate the location for the page bitmap. - The FDC (Not what you think, FDC stands for Fast Debug Channel) IRQ around was causing issues on non-Malta platforms, so move the code to a Malta specific location. - A spelling fix replicated through several files. - Fix to the emulation of an R2 instruction for R6 cores. - Fix the JR emulation for R6. - Further patching of mindless 64 bit issues. - Ensure the kernel won't crash on CPUs with L2 caches with >= 8 ways. - Use compat_sys_getsockopt for O32 ABI on 64 bit kernels. - Fix cache flushing for multithreaded cores. - A build fix" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: O32: Use compat_sys_getsockopt. MIPS: c-r4k: Extend way_string array MIPS: Pistachio: Support CDMM & Fast Debug Channel MIPS: Malta: Make GIC FDC IRQ workaround Malta specific MIPS: c-r4k: Fix cache flushing for MT cores Revert "MIPS: Kconfig: Disable SMP/CPS for 64-bit" MIPS: cps-vec: Use macros for various arithmetics and memory operations MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0 MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bit MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2 MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer casting MIPS: Fix erroneous JR emulation for MIPS R6 MIPS: Fix branch emulation for BLTC and BGEC instructions MIPS: kernel: traps: Fix broken indentation MIPS: bootmem: Don't use memory holes for page bitmap MIPS: O32: Do not handle require 32 bytes from the stack to be readable. MIPS, CPUFREQ: Fix spelling of Institute. MIPS: Lemote 2F: Fix build caused by recent mass rename.
2015-07-12irqchip/mips-gic: Use irq_set_chip_handler_name_lockedThomas Gleixner1-9/+6
Use irq_set_handler_name_locked() as it avoids a redundant lookup of the irq descriptor. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net>
2015-07-12irqchip/metag-ext: Use irq_set_chip_handler_name_locked()Thomas Gleixner1-5/+4
Hand in irq_data and avoid the redundant lookup of irq_desc. Originally-from: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-12irqchip/vt8500: Use irq_set_handler_locked()Thomas Gleixner1-3/+3
Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle: @@ struct irq_data *d; expression E1; @@ -__irq_set_handler_locked(d->irq, E1); +irq_set_handler_locked(d, E1); Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Julia Lawall <julia.lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net>
2015-07-12irqchip: Use irq_desc_get_xxx() to avoid redundant lookup of irq_descJiang Liu6-8/+8
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we already have a pointer to corresponding irq_desc. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Link: http://lkml.kernel.org/r/1433391238-19471-11-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-12irqchip/mips-gic: Use access helper irq_data_get_affinity_mask()Jiang Liu1-1/+1
Use access helper irq_data_get_affinity_mask() to hide implementation details of struct irq_desc. [ tglx: Verified with coccinelle ] Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1433145945-789-30-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-12irqchip/vic: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net>
2015-07-12irqchip/versatile: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net>
2015-07-12irqchip/tb10x: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net>
2015-07-12irqchip/sunxi-nmi: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+1
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org
2015-07-12irqchip/orion: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net>
2015-07-12irqchip/metag: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+1
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: James Hogan <james.hogan@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-metag@vger.kernel.org
2015-07-12irqchip/imgpdc: Consolidate chained IRQ handler install/removeThomas Gleixner1-4/+4
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net>
2015-07-12irqchip/gic: Consolidate chained IRQ handler install/removeThomas Gleixner1-3/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net>
2015-07-12irqchip/brcmstb-l2: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org
2015-07-12irqchip/bcm7120-l2: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org
2015-07-12irqchip/bcm7038-l1: Consolidate chained IRQ handler install/removeThomas Gleixner1-2/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org
2015-07-12irqchip/exynos-combiner: Consolidate chained IRQ handler install/removeThomas Gleixner1-3/+2
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); | -irq_set_handler_data(E1, E2); ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_handler_data(E1, E2) != 0) - BUG(); ... | -irq_set_handler_data(E1, E2); ... ) -irq_set_chained_handler(E1, E3); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org
2015-07-12irqchip: Prepare for local stub header removalJoel Porquet44-79/+42
The IRQCHIP_DECLARE macro moved to to 'include/linux/irqchip.h', so the local irqchip.h became an empty shell, which solely includes include/linux/irqchip.h Include the global header in all irqchip drivers instead of the local header, so we can remove it. Signed-off-by: Joel Porquet <joel@porquet.org> Cc: vgupta@synopsys.com Cc: monstr@monstr.eu Cc: ralf@linux-mips.org Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1882096.X39jVG8e0D@joel-zenbook Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-12irqchip/sirfsoc: Fix generic chip allocation wreckageThomas Gleixner1-23/+25
irq_alloc_domain_generic_chips() can only be called once for an irqdomain. The sirfsoc init calls it twice and because the return value is not checked it does not notice the wreckage. The code works by chance because the first call already allocates two chips and therefor the second call to sirfsoc_alloc_gc() operates on the proper generic chip instance. Use a single call and setup the two chips in the obvious correct way. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Barry Song <baohua@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Olof Johansson <olof@lixom.net> Link: http://lkml.kernel.org/r/20150706101543.470696950@linutronix.de
2015-07-12irqchip/dw-apb-ictl: Fix generic domain chip wreckageThomas Gleixner1-31/+22
The num_ct argument of irq_alloc_domain_generic_chips() tells the core code how many chip types (for different control flows, e.g. edge/level) should be allocated. It does not control how many generic chip instances are created because that's determined from the irq domain size and the number of interrupts per chip. The dw-apb init abuses the num_ct argument for allocating one or two chip types depending on the number of interrupts. That's completely wrong because the alternate type is never used. This code was obviously never tested on a system which has more than 32 interrupts as that would have never worked due to the unitialized second generic chip instance. Hand in the proper num_ct=1 and fixup the chip initialization along with the interrupt handler. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Jisheng Zhang <jszhang@marvell.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/20150706101543.373582262@linutronix.de
2015-07-10MIPS: Malta: Make GIC FDC IRQ workaround Malta specificJames Hogan1-10/+0
Wider testing reveals that the Fast Debug Channel (FDC) interrupt is routed through the GIC just fine on Pistachio SoC, even though it contains interAptiv cores. Clearly the FDC interrupt routing problems previously observed on interAptiv and proAptiv cores are specific to the Malta FPGA bitstreams. Move the workaround for interAptiv and proAptiv out of gic_get_c0_fdc_int() in the GIC irqchip driver into Malta's get_c0_fdc_int() platform callback, to allow the Pistachio SoC to use the FDC interrupt. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/9748/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-07ACPI / ARM64 : use the new BAD_MADT_GICC_ENTRY macroAl Stone1-1/+1
For those parts of the arm64 ACPI code that need to check GICC subtables in the MADT, use the new BAD_MADT_GICC_ENTRY macro instead of the previous BAD_MADT_ENTRY. The new macro takes into account differences in the size of the GICC subtable that the old macro did not; this caused failures even though the subtable entries are valid. Fixes: aeb823bbacc2 ("ACPICA: ACPI 6.0: Add changes for FADT table.") Signed-off-by: Al Stone <al.stone@linaro.org> Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: "Rafael J. Wysocki" <rjw@rjwysocki.net> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-07-04Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds1-18/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq update from Thomas Gleixner: "The last update for 4.2 is just moving a macro from a local header to the global one, so it can be used in architecture code as well. Cleanup of the now empty local header is 4.3 material" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: Move IRQCHIP_DECLARE macro to include/linux/irqchip.h
2015-07-02irqchip: Move IRQCHIP_DECLARE macro to include/linux/irqchip.hJoel Porquet1-18/+1
At the moment the IRQCHIP_DECLARE macro is only declared locally in drivers/irqchip/irqchip.h. It prevents from using it directly in arch/* directories whenever irqchip drivers only exist there, which happens in a few cases (e.g. arc, arm, microblaze and mips). This patch makes the macro to be globally defined, i.e. in include/linux/irqchip.h, and thus usable for arch-specific declarations of irqchip drivers. In this way, it is very similar to what clocksource does (ie CLOCKSOURCE_OF_DECLARE is defined in include/linux/clocksource.h). For now, this patch only moves the declaration of the macro IRQCHIP_DECLARE to the global header 'include/linux/irqchip.h' and make 'drivers/irqchip/irqchip.h' include 'include/linux/irqchip.h'. Later, other patches will get rid of 'drivers/irqchip/irqchip.h' and modify all the impacted irqchip drivers. Signed-off-by: Joel Porquet <joel@porquet.org> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1435865565-14114-1-git-send-email-joel@porquet.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-27Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds4-1/+362
Pull MIPS updates from Ralf Baechle: - Improvements to the tlb_dump code - KVM fixes - Add support for appended DTB - Minor improvements to the R12000 support - Minor improvements to the R12000 support - Various platform improvments for BCM47xx - The usual pile of minor cleanups - A number of BPF fixes and improvments - Some improvments to the support for R3000 and DECstations - Some improvments to the ATH79 platform support - A major patchset for the JZ4740 SOC adding support for the CI20 platform - Add support for the Pistachio SOC - Minor BMIPS/BCM63xx platform support improvments. - Avoid "SYNC 0" as memory barrier when unlocking spinlocks - Add support for the XWR-1750 board. - Paul's __cpuinit/__cpuinitdata cleanups. - New Malta CPU board support large memory so enable ZONE_DMA32. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits) MIPS: spinlock: Adjust arch_spin_lock back-off time MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA MIPS: BCM47xx: Simplify handling SPROM revisions MIPS: Cobalt Don't use module_init in non-modular MTD registration. MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/ MIPS: use for_each_sg() MIPS: BCM47xx: Don't select BCMA_HOST_PCI MIPS: BCM47xx: Add helper variable for storing NVRAM length MIPS: IRQ/IP27: Move IRQ allocation API to platform code. MIPS: Replace smp_mb with release barrier function in unlocks. MIPS: i8259: DT support MIPS: Malta: Basic DT plumbing MIPS: include errno.h for ENODEV in mips-cm.h MIPS: Define GCR_GIC_STATUS register fields MIPS: BPF: Introduce BPF ASM helpers MIPS: BPF: Use BPF register names to describe the ABI MIPS: BPF: Move register definition to the BPF header MIPS: net: BPF: Replace RSIZE with SZREG MIPS: BPF: Free up some callee-saved registers MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers ...
2015-06-26Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds2-0/+176
Pull ARM updates from Russell King: "Bigger items included in this update are: - A series of updates from Arnd for ARM randconfig build failures - Updates from Dmitry for StrongARM SA-1100 to move IRQ handling to drivers/irqchip/ - Move ARMs SP804 timer to drivers/clocksource/ - Perf updates from Mark Rutland in preparation to move the ARM perf code into drivers/ so it can be shared with ARM64. - MCPM updates from Nicolas - Add support for taking platform serial number from DT - Re-implement Keystone2 physical address space switch to conform to architecture requirements - Clean up ARMv7 LPAE code, which goes in hand with the Keystone2 changes. - L2C cleanups to avoid unlocking caches if we're prevented by the secure support to unlock. - Avoid cleaning a potentially dirty cache containing stale data on CPU initialisation - Add ARM-only entry point for secondary startup (for machines that can only call into a Thumb kernel in ARM mode). Same thing is also done for the resume entry point. - Provide arch_irqs_disabled via asm-generic - Enlarge ARMv7M vector table - Always use BFD linker for VDSO, as gold doesn't accept some of the options we need. - Fix an incorrect BSYM (for Thumb symbols) usage, and convert all BSYM compiler macros to a "badr" (for branch address). - Shut up compiler warnings provoked by our cmpxchg() implementation. - Ensure bad xchg sizes fail to link" * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (75 commits) ARM: Fix build if CLKDEV_LOOKUP is not configured ARM: fix new BSYM() usage introduced via for-arm-soc branch ARM: 8383/1: nommu: avoid deprecated source register on mov ARM: 8391/1: l2c: add options to overwrite prefetching behavior ARM: 8390/1: irqflags: Get arch_irqs_disabled from asm-generic ARM: 8387/1: arm/mm/dma-mapping.c: Add arm_coherent_dma_mmap ARM: 8388/1: tcm: Don't crash when TCM banks are protected by TrustZone ARM: 8384/1: VDSO: force use of BFD linker ARM: 8385/1: VDSO: group link options ARM: cmpxchg: avoid warnings from macro-ized cmpxchg() implementations ARM: remove __bad_xchg definition ARM: 8369/1: ARMv7M: define size of vector table for Vybrid ARM: 8382/1: clocksource: make ARM_TIMER_SP804 depend on GENERIC_SCHED_CLOCK ARM: 8366/1: move Dual-Timer SP804 driver to drivers/clocksource ARM: 8365/1: introduce sp804_timer_disable and remove arm_timer.h inclusion ARM: 8364/1: fix BE32 module loading ARM: 8360/1: add secondary_startup_arm prototype in header file ARM: 8359/1: correct secondary_startup_arm mode ARM: proc-v7: sanitise and document registers around errata ARM: proc-v7: clean up MIDR access ...
2015-06-25Merge tag 'for-4.2' of git://git.sourceforge.jp/gitroot/uclinux-h8/linuxLinus Torvalds4-0/+206
Pull Renesas H8/300 architecture re-introduction from Yoshinori Sato. We dropped arch/h8300 two years ago as stale and old, this is a new and more modern rewritten arch support for the same architecture. * tag 'for-4.2' of git://git.sourceforge.jp/gitroot/uclinux-h8/linux: (27 commits) h8300: fix typo. h8300: Always build dtb h8300: Remove ARCH_WANT_IPC_PARSE_VERSION sh-sci: Get register size from platform device clk: h8300: fix error handling in h8s2678_pll_clk_setup() h8300: Symbol name fix h8300: devicetree source h8300: configs h8300: IRQ chip driver h8300: clocksource h8300: clock driver h8300: Build scripts h8300: library functions h8300: Memory management h8300: miscellaneous functions h8300: process helpers h8300: compressed image support h8300: Low level entry h8300: kernel startup h8300: Interrupt and exceptions ...
2015-06-23h8300: IRQ chip driverYoshinori Sato4-0/+206
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
2015-06-23Merge branch 'irq-core-for-linus' of ↵Linus Torvalds23-68/+137
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "The irq departement delivers: - plug a potential race related to chained interrupt handlers - core updates which address the needs of the x86 irqdomain conversion - new irqchip callback to support affinity settings for VCPUs - the usual pile of updates to interrupt chip drivers - a few helper functions to allow further cleanups and simplifications I have a largish pile of coccinelle scripted/verified cleanups and simplifications pending on top of that, but I prefer to send that towards the end of the merge window when the arch/driver changes have hit your tree to avoid API change wreckage as far as possible" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits) genirq: Remove bogus restriction in irq_move_mask_irq() irqchip: atmel-aic5: Add sama5d2 support irq: spear-shirq: Fix race in installing chained IRQ handler irq: irq-keystone: Fix race in installing chained IRQ handler gpio: gpio-tegra: Fix race in installing chained IRQ handler gpio: gpio-mxs: Fix race in installing chained IRQ handler gpio: gpio-mxc: Fix race in installing chained IRQ handler ARM: gemini: Fix race in installing GPIO chained IRQ handler GPU: ipu: Fix race in installing IPU chained IRQ handler ARM: sa1100: convert SA11x0 related code to use new chained handler helper irq: Add irq_set_chained_handler_and_data() irqchip: exynos-combiner: Save IRQ enable set on suspend genirq: Introduce helper function irq_data_get_affinity_mask() genirq: Introduce helper function irq_data_get_node() genirq: Introduce struct irq_common_data to host shared irq data genirq: Prevent crash in irq_move_irq() genirq: Enhance irq_data_to_desc() to support hierarchy irqdomain irqchip: gic: Simplify gic_configure_irq by using IRQCHIP_SET_TYPE_MASKED irqchip: renesas: intc-irqpin: Improve binding documentation genirq: Set IRQCHIP_SKIP_SET_WAKE for no_irq_chip ...
2015-06-21MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchipPaul Burton3-0/+183
Move the driver for Ingenic SoC interrupt controllers into drivers/irqchip where it belongs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10147/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21IRQCHIP: irq_cpu: declare irqchip table entryPaul Burton1-0/+3
Allow the MIPS CPU interrupt controller to be probed from DT using the generic __irqchip_of_table for platforms which use irqchip_init. This will avoid such platforms needing to duplicate the compatible string & init function pointer. [ralf@linux-mips.org: Resolved conflict due the preceeding commit that moves irq-cpu.c. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Cc: Felix Fietkau <nbd@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/10131/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.Ralf Baechle3-0/+175
While at it, rename it because in drivers/irqchip no longer every CPU is a MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-18irqchip: atmel-aic5: Add sama5d2 supportNicolas Ferre1-0/+9
Add sama5d2 support to irq-atmel-aic5. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Boris BREZILLON <boris.brezillon@free-electrons.com> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com> Cc: Ludovic Desroches <ludovic.desroches@atmel.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: <linux-arm-kernel@lists.infradead.org> Link: http://lkml.kernel.org/r/1434632855-27272-1-git-send-email-nicolas.ferre@atmel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-18irq: spear-shirq: Fix race in installing chained IRQ handlerRussell King1-2/+1
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Lee Jones <lee.jones@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/E1Z4z0X-0002T1-6U@rmk-PC.arm.linux.org.uk Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-18irq: irq-keystone: Fix race in installing chained IRQ handlerRussell King1-2/+1
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Lee Jones <lee.jones@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/E1Z4z0S-0002Ss-1V@rmk-PC.arm.linux.org.uk Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-16irqchip: exynos-combiner: Save IRQ enable set on suspendJavier Martinez Canillas1-5/+59
The Exynos interrupt combiner IP loses its state when the SoC enters into a low power state during a Suspend-to-RAM. This means that if a IRQ is used as a source, the interrupts for the devices are disabled when the system is resumed from a sleep state so are not triggered. Save the interrupt enable set register for each combiner group and restore it after resume to make sure that the interrupts are enabled. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Kukjin Kim <kgene@kernel.org> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Doug Anderson <dianders@chromium.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Peter Chubb <peter.chubb@nicta.com.au> Cc: Shuah Khan <shuahkhan@gmail.com> Cc: Chanho Park <parkch98@gmail.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Link: http://lkml.kernel.org/r/1434087795-13990-1-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-15Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-7/+14
Pull more MIPS fixes from Ralf Baechle: "Another round of 4.1 MIPS fixes, one fix to a MIPS-specific #if condition in lib/mpi, one fix to the MIPS GIC irqchip driver and one SSB fix. Details: - fix handling of clock in chipco SSB driver. - fix two MIPS-specific #if conditions to correctly work for GCC 5.1. - fix damage to R6 pgtable bits done by XPA support. - fix possible crash due to unloading modules that contain statically defined platform devices. - fix disabling of the MSA ASE on context switch to also work correctly when a new thread/process has the CPU for the very first time. This is part of linux-next and has been beaten to death on Imagination's test farm. While things are not looking too grim this pull request also means the rate of fixes for 4.1 remains nearly constant so I'd not be unhappy if you'd delay the release" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MPI: MIPS: Fix compilation error with GCC 5.1 IRQCHIP: mips-gic: Don't nest calls to do_IRQ() MIPS: MSA: bugfix - disable MSA correctly for new threads/processes. MIPS: Loongson: Do not register 8250 platform device from module. MIPS: Cobalt: Do not build MTD platform device registration code as module. SSB: Fix handling of ssb_pmu_get_alp_clock() MIPS: pgtable-bits: Fix XPA damage to R6 definitions.
2015-06-13IRQCHIP: mips-gic: Don't nest calls to do_IRQ()Rabin Vincent1-7/+14
The GIC chained handlers use do_IRQ() to call the subhandlers. This means that irq_enter() calls get nested, which leads to preempt count looking like we're in nested interrupts, which in turn leads to all system time being accounted as IRQ time in account_system_time(). Fix it by using generic_handle_irq(). Since these same functions are used in some systems (if cpu_has_veic) from a low-level vectored interrupt handler which does not go throught do_IRQ(), we need to do it conditionally. Signed-off-by: Rabin Vincent <rabin.vincent@axis.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Patchwork: https://patchwork.linux-mips.org/patch/10545/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-12Merge branch 'sa1100' into for-nextRussell King2-0/+176
2015-06-08irqchip: sunxi-nmi: Fix off-by-one error in irq iteratorAxel Lin1-1/+1
Fixes: 6058bb362818 'ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller' Signed-off-by: Axel Lin <axel.lin@ingics.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Carlo Caione <carlo@caione.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/1433684009.9134.1.camel@ingics.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-05irqchip: gic: Simplify gic_configure_irq by using IRQCHIP_SET_TYPE_MASKEDSudeep Holla4-17/+3
GIC requires to disable the interrupt before changing the trigger type. irqchip core provides IRQCHIP_SET_TYPE_MASKED flag and ensures that the interrupt is masked before calling chip.irq_set_type() if the irqchip sets the flag. This patch adds IRQCHIP_SET_TYPE_MASKED to GIC irqchip so that the core can manage disabling the interrupt while changing the trigger type. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1433501997-19205-1-git-send-email-sudeep.holla@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-05Merge branch 'linus' into irq/coreThomas Gleixner2-71/+2
Get the urgent fixes from upstream to avoid conflicts.
2015-05-28ARM: 8368/1: sa1100: move irq driver to drivers/irqchip/Dmitry Eremin-Solenikov2-0/+176
Move current sa11x0 IRQ driver to the irqchip subsystem. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-05-22irqchip: mtk-sysirq: Make mtk_sysirq_of_init return error if ioremap failsAxel Lin1-1/+1
PTR_ERR(NULL) returns 0 so current code returns 0 if ioremap fails, fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: linux-mediatek@lists.infradead.org <linux-mediatek@lists.infradead.org> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1432220254.29544.1.camel@ingics.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-17 00:25:08 +0300