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2022-03-14Merge tag 'irqchip-5.18' of ↵Thomas Gleixner20-366/+1272
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates from Marc Zyngier: - Add support for the STM32MP13 variant - Move parent device away from struct irq_chip - Remove all instances of non-const strings assigned to struct irq_chip::name, enabling a nice cleanup for VIC and GIC) - Simplify the Qualcomm PDC driver - A bunch of SiFive PLIC cleanups - Add support for a new variant of the Meson GPIO block - Add support for the irqchip side of the Apple M1 PMU - Add support for the Apple M1 Pro/Max AICv2 irqchip - Add support for the Qualcomm MPM wakeup gadget - Move the Xilinx driver over to the generic irqdomain handling - Tiny speedup for IPIs on GICv3 systems - The usual odd cleanups Link: https://lore.kernel.org/all/20220313105142.704579-1-maz@kernel.org
2022-03-11Merge branch irq/qcom-mpm into irq/irqchip-nextMarc Zyngier3-0/+470
* irq/qcom-mpm: : . : Add support for Qualcomm's MPM wakeup controller, courtesy : of Shawn Guo. : . irqchip: Add Qualcomm MPM controller driver dt-bindings: interrupt-controller: Add Qualcomm MPM support Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-03-11irqchip: Add Qualcomm MPM controller driverShawn Guo3-0/+470
Qualcomm SoCs based on the RPM architecture have a MSM Power Manager (MPM) in always-on domain. In addition to managing resources during sleep, the hardware also has an interrupt controller that monitors the interrupts when the system is asleep, wakes up the APSS when one of these interrupts occur and replays it to GIC after it becomes operational. It adds an irqchip driver for this interrupt controller, and here are some notes about it. - For given SoC, a fixed number of MPM pins are supported, e.g. 96 pins on QCM2290. Each of these MPM pins can be either a MPM_GIC pin or a MPM_GPIO pin. The mapping between MPM_GIC pin and GIC interrupt is defined by SoC, as well as the mapping between MPM_GPIO pin and GPIO number. The former mapping is retrieved from device tree, while the latter is defined in TLMM pinctrl driver. - The power domain (PD) .power_off hook is used to notify RPM that APSS is about to power collapse. This requires MPM PD be the parent PD of CPU cluster. - When SoC gets awake from sleep mode, the driver will receive an interrupt from RPM, so that it can replay interrupt for particular polarity. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220308080534.3384532-3-shawn.guo@linaro.org
2022-03-11Merge branch irq/aic-v2 into irq/irqchip-nextMarc Zyngier1-88/+375
* irq/aic-v2: : . : Add support for the interrupt controller found is the latest : incarnation of Apple M1 systems, courtesy of Hector Martin. : . irqchip/apple-aic: Add support for AICv2 irqchip/apple-aic: Support multiple dies irqchip/apple-aic: Dynamically compute register offsets irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs irqchip/apple-aic: Add Fast IPI support dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2 PCI: apple: Change MSI handling to handle 4-cell AIC fwspec form Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-03-11irqchip/apple-aic: Add support for AICv2Hector Martin1-33/+148
Introduce support for the new AICv2 hardware block in t6000/t6001 SoCs. It seems these blocks are missing the information required to compute the event register offset in the capability registers, so we specify that in the DT as a second reg entry. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-8-marcan@marcan.st
2022-03-11irqchip/apple-aic: Support multiple diesHector Martin1-23/+54
Multi-die support in AICv2 uses several sets of IRQ registers. Introduce a die count and compute the register group offset based on the die ID field of the hwirq number, as reported by the hardware. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-7-marcan@marcan.st
2022-03-11irqchip/apple-aic: Dynamically compute register offsetsHector Martin1-17/+55
This allows us to support AIC variants with different numbers of IRQs based on capability registers. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-6-marcan@marcan.st
2022-03-11irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqsHector Martin1-32/+39
This allows us to directly use the hardware event number as the hwirq number. Since IRQ events have bit 16 set (type=1), FIQs now move to starting at hwirq number 0. This will become more important once multi-die support is introduced in a later commit. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-5-marcan@marcan.st
2022-03-11irqchip/apple-aic: Add Fast IPI supportHector Martin1-13/+109
The newer AICv2 present in t600x SoCs does not have legacy IPI support at all. Since t8103 also supports Fast IPIs, implement support for this first. The legacy IPI code is left as a fallback, so it can be potentially used by older SoCs in the future. The vIPI code is shared; only the IPI firing/acking bits change for Fast IPIs. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220309192123.152028-4-marcan@marcan.st
2022-03-10Merge branch irq/aic-pmu into irq/irqchip-nextMarc Zyngier1-22/+72
* irq/aic-pmu: : . : Prefix branch for the M1 PMU support, adding the required : irqchip changes. Shared with the arm64 tree. : . irqchip/apple-aic: Fix cpumask allocation for FIQs irqchip/apple-aic: Move PMU-specific registers to their own include file arm64: dts: apple: Add t8303 PMU nodes arm64: dts: apple: Add t8103 PMU interrupt affinities irqchip/apple-aic: Wire PMU interrupts irqchip/apple-aic: Parse FIQ affinities from device-tree dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts dt-bindings: arm-pmu: Document Apple PMU compatible strings Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-03-10irqchip/apple-aic: Fix cpumask allocation for FIQsMarc Zyngier1-1/+1
An emparassing typo: allocating a pointer instead of the object pointed to. No harm done, as the pointer is large enough for what we are using the object for, but still... Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220310050238.4478-1-guozhengkui@vivo.com
2022-03-09Merge branch irq/meson-gpio into irq/irqchip-nextMarc Zyngier1-16/+90
* irq/meson-gpio: : . : Expand meson-gpio support to deal with the new Meson-S4 SoC : . irqchip/meson-gpio: Add support for meson s4 SoCs irqchip/meson-gpio: add select trigger type callback irqchip/meson-gpio: support more than 8 channels gpio irq dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-03-09irqchip/meson-gpio: Add support for meson s4 SoCsQianggui Song1-0/+65
The meson s4 SoCs support 12 gpio irq lines compared with previous serial chips and have something different, details are as below. IRQ Number: - 80:68 13 pins on bank Z - 67:48 20 pins on bank X - 47:36 12 pins on bank H - 35:24 12 pins on bank D - 23:22 2 pins on bank E - 21:14 8 pins on bank C - 13:0 13 pins on bank B Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> [maz: fixed some W=1 build warnings] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220225055207.1048-5-qianggui.song@amlogic.com
2022-03-04irqchip/meson-gpio: add select trigger type callbackQianggui Song1-7/+13
Due to some chips may use different registers and offset, provide a set trigger type call back and add one for old controller. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220225055207.1048-4-qianggui.song@amlogic.com
2022-03-04irqchip/meson-gpio: support more than 8 channels gpio irqQianggui Song1-9/+12
Current meson gpio irqchip driver only support 8 channels for gpio irq line, later chips may have more then 8 channels, so need to modify code to support more. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220225055207.1048-3-qianggui.song@amlogic.com
2022-03-04Merge branch irq/misc-5.18 into irq/irqchip-nextMarc Zyngier3-15/+19
* irq/misc-5.18: : . : Misc irq chip changes for 5.18 : : - GICv3: Relax ordering of previous stores to only include the ISH domain : : - nvic: Unmap MMIo region on probe failure : : - xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER when used on microblaze : . irqchip/xilinx: Switch to GENERIC_IRQ_MULTI_HANDLER irqchip/nvic: Release nvic_base upon failure irqchip/gic-v3: Use dsb(ishst) to order writes with ICC_SGI1R_EL1 accesses Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-03-04Merge branch irq/plic-cleanups into irq/irqchip-nextMarc Zyngier1-12/+26
* irq/plic-cleanups: : . : SiFive PLIC cleanups from Niklas Cassel: : : - Clarify some of the namings in the driver : : - Make sure S-mode interrupts are disabled when running in M-mode : . irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode irqchip/sifive-plic: Improve naming scheme for per context offsets Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-03-04irqchip/xilinx: Switch to GENERIC_IRQ_MULTI_HANDLERMichal Simek1-14/+16
Register the Xilinx driver as the root interrupt controller using the GENERIC_IRQ_MULTI_HANDLER API, instead of the arch-specific hack. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Stefan Asserhall <stefan.asserhall@xilinx.com> [maz: repainted commit message] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/e6c6595a81f662bf839cee3109d0fa58a596ea47.1646380284.git.michal.simek@xilinx.com
2022-03-02irqchip/sifive-plic: Disable S-mode IRQs if running in M-modeNiklas Cassel1-5/+19
When detecting a context for a privilege mode different from the current running privilege mode, we simply skip to the next context register. This means that we never clear the S-mode enable bits when running in M-mode. On canaan k210, a bunch of S-mode interrupts are enabled by the bootrom. These S-mode specific interrupts should never trigger, since we never set the mie.SEIE bit in the parent interrupt controller (riscv-intc). However, we will be able to see the mip.SEIE bit set as pending. This isn't a good default when CONFIG_RISCV_M_MODE is set, since in that case we will never enter a lower privilege mode (e.g. S-mode). Let's clear the S-mode enable bits when running the kernel in M-mode, such that we won't have a interrupt pending bit set, which we will never clear. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220302131544.3166154-3-Niklas.Cassel@wdc.com
2022-03-02irqchip/sifive-plic: Improve naming scheme for per context offsetsNiklas Cassel1-7/+7
The PLIC supports a fixed number of contexts (15872). Each context has fixed register offsets in PLIC. The number of contexts that we need to initialize depends on the privilege modes supported by each hart. Therefore, this mapping between PLIC context registers to hart privilege modes is platform specific, and is currently supplied via device tree. For example, canaan,k210 has the following mapping: Context0: hart0 M-mode Context1: hart0 S-mode Context2: hart1 M-mode Context3: hart1 S-mode While sifive,fu540 has the following mapping: Context0: hart0 M-mode Context1: hart1 M-mode Context2: hart1 S-mode Because the number of contexts per hart is not fixed, the names ENABLE_PER_HART and CONTEXT_PER_HART for the register offsets are quite confusing and might mislead the reader to think that these are fixed register offsets per hart. Rename the offsets to more clearly highlight that these are per PLIC context and not per hart. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220302131544.3166154-2-Niklas.Cassel@wdc.com
2022-03-01Merge branch irq/qcom-pdc-cleanup into irq/irqchip-nextMarc Zyngier1-109/+28
* irq/qcom-pdc-cleanup: : . : Spring cleanup for the Qualcomm PDC driver, simplifying its : use of irq domains, replacing open-coded functionnalities with : the core code equivalent, and fixing the dodgy locking. : . irqchip/qcom-pdc: Drop open coded version of __assign_bit() irqchip/qcom-pdc: Fix broken locking irqchip/qcom-pdc: Kill qcom_pdc_translate helper irqchip/qcom-pdc: Kill non-wakeup irqdomain irqchip/qcom-pdc: Kill PDC_NO_PARENT_IRQ Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-03-01irqchip/nvic: Release nvic_base upon failureSouptick Joarder (HPE)1-0/+2
smatch warning was reported as below -> smatch warnings: drivers/irqchip/irq-nvic.c:131 nvic_of_init() warn: 'nvic_base' not released on lines: 97. Release nvic_base upon failure. Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Souptick Joarder (HPE) <jrdr.linux@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220218163303.33344-1-jrdr.linux@gmail.com
2022-03-01irqchip/qcom-pdc: Drop open coded version of __assign_bit()Marc Zyngier1-5/+2
The driver uses what looks like an open-coded version of __assign_bit(). Replace it with the real thing. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-6-maz@kernel.org
2022-03-01irqchip/qcom-pdc: Fix broken lockingMarc Zyngier1-2/+3
pdc_enable_intr() serves as a primitive to qcom_pdc_gic_{en,dis}able, and has a raw spinlock for mutual exclusion, which is uses with interruptible primitives. This means that this critical section can itself be interrupted. Should the interrupt also be a PDC interrupt, and the endpoint driver perform an irq_disable() on that interrupt, we end-up in a deadlock. Fix this by using the irqsave/irqrestore variants of the locking primitives. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-5-maz@kernel.org
2022-03-01irqchip/qcom-pdc: Kill qcom_pdc_translate helperMarc Zyngier1-17/+2
qcom_pdc_translate() really is nothing but an open coded version of irq_domain_translate_twocell(). Get rid of it and use the common version instead. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-4-maz@kernel.org
2022-03-01irqchip/qcom-pdc: Kill non-wakeup irqdomainMarc Zyngier1-74/+10
A careful look at the way the PDC driver works shows that: - all interrupts are in the same space - all interrupts are treated the same And yet the driver creates two domains based on whether the interrupt gets mapped directly or from the pinctrl code, which is obviously a waste of resources. Kill the non-wakeup domain and unify all the interrupt handling. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220224101226.88373-3-maz@kernel.org
2022-03-01irqchip/qcom-pdc: Kill PDC_NO_PARENT_IRQMarc Zyngier1-17/+17
PDC_NO_PARENT_IRQ is pretty pointless, as all it indicates is that the PDC terminates the interrupt hierarchy. Which is exactly the same as not having a mapping in the GIC space. This is also bad practice to treat the absence of a hwirq as a hwirq itself. Just explicitly use the region mapping pointer, and drop the definition. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Maulik Shah <quic_mkshah@quicinc.com> Link: https://lore.kernel.org/r/20220224101226.88373-2-maz@kernel.org
2022-02-21irqchip/gic-v3: Use dsb(ishst) to order writes with ICC_SGI1R_EL1 accessesBarry Song1-1/+1
A dsb(ishst) barrier should be enough to order previous writes with the system register generating the SGI, as we only need to guarantee the visibility of data to other CPUs in the inner shareable domain before we send the SGI. A micro-benchmark is written to verify the performance impact on kunpeng920 machine with 2 sockets, each socket has 2 dies, and each die has 24 CPUs, so totally the system has 2 * 2 * 24 = 96 CPUs. ~2% performance improvement can be seen by this benchmark. The code of benchmark module: #include <linux/module.h> #include <linux/timekeeping.h> volatile int data0 ____cacheline_aligned; volatile int data1 ____cacheline_aligned; volatile int data2 ____cacheline_aligned; volatile int data3 ____cacheline_aligned; volatile int data4 ____cacheline_aligned; volatile int data5 ____cacheline_aligned; volatile int data6 ____cacheline_aligned; static void ipi_latency_func(void *val) { } static int __init ipi_latency_init(void) { ktime_t stime, etime, delta; int cpu, i; int start = smp_processor_id(); stime = ktime_get(); for ( i = 0; i < 1000; i++) for (cpu = 0; cpu < 96; cpu++) { data0 = data1 = data2 = data3 = data4 = data5 = data6 = cpu; smp_call_function_single(cpu, ipi_latency_func, NULL, 1); } etime = ktime_get(); delta = ktime_sub(etime, stime); printk("%s ipi from cpu%d to cpu0-95 delta of 1000times:%lld\n", __func__, start, delta); return 0; } module_init(ipi_latency_init); static void ipi_latency_exit(void) { } module_exit(ipi_latency_exit); MODULE_DESCRIPTION("IPI benchmark"); MODULE_LICENSE("GPL"); run the below commands 10 times on both Vanilla and the kernel with this patch: # taskset -c 0 insmod test.ko # rmmod test The result on vanilla: ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126757449 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126784249 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126177703 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:127022281 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126184883 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:127374585 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:125778089 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126974441 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:127357625 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:126228184 The result on the kernel with this patch: ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:124467401 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123474209 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123558497 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:122993951 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:122984223 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123323609 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:124507583 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123386963 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123340664 ipi_latency_init ipi from cpu0 to cpu0-95 delta of 1000times:123285324 Signed-off-by: Barry Song <song.bao.hua@hisilicon.com> [maz: tidied up commit message] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220220061910.6155-1-21cnbao@gmail.com
2022-02-15Merge branch irq/print_chip into irq/irqchip-nextMarc Zyngier6-99/+137
* irq/print_chip: : . : Convert irqchip drivers that use the .name field as a topology : description to the .irq_print_chip callback, which allows the : name to be made dymanic. The irq_chip structures are then made : 'const' in order to prevent further abuse. : . irqchip/versatile-fpga: Switch to dynamic chip name output irqchip/ts4800: Switch to dynamic chip name output irqchip/mvebu-pic: Switch to dynamic chip name output irqchip/lpc32xx: Switch to dynamic chip name output irqchip/gic: Switch to dynamic chip name output genirq/debugfs: Use irq_print_chip() when provided by irqchip genirq: Allow irq_chip registration functions to take a const irq_chip irqdomain: Let irq_domain_set_{info,hwirq_and_chip} take a const irq_chip Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-02-15irqchip/versatile-fpga: Switch to dynamic chip name outputMarc Zyngier2-21/+26
Move the name output to the relevant callback, which allows us some nice cleanups (mostly owing to the fact that the driver is now DT only. We also drop a random include directive from the ftintc010 driver. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-8-maz@kernel.org
2022-02-15irqchip/ts4800: Switch to dynamic chip name outputMarc Zyngier1-8/+17
Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-7-maz@kernel.org
2022-02-15irqchip/mvebu-pic: Switch to dynamic chip name outputMarc Zyngier1-10/+18
Instead of overriding the name field, track the corresponding device and use the relevant callback to output its name. This allows us to make the irq_chip structure const. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-6-maz@kernel.org
2022-02-15irqchip/lpc32xx: Switch to dynamic chip name outputMarc Zyngier1-12/+22
Instead of overriding the name field with the device name, use the relevant callback. This allows us to make the irq_chip structure const. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-5-maz@kernel.org
2022-02-15irqchip/gic: Switch to dynamic chip name outputMarc Zyngier1-48/+54
The last dynamic aspect of the GIC's irq_chip structure is the name that is associated to it. Move the output of that name to the relevant callback, which allows us to do a bit of cleanup and mark the structures const. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220209162607.1118325-4-maz@kernel.org
2022-02-10Merge branch irq/parent_device into irq/irqchip-nextMarc Zyngier4-13/+13
* irq/parent_device: : . : Move irq_chip::parent_device to irq_domain::dev to track the : PM state of the device implementing the irqchip. : . genirq: Kill irq_chip::parent_device pinctrl: starfive: Move PM device over to irq domain pinctrl: npcm: Fix broken references to chip->parent_device gpio: tpmx86: Move PM device over to irq domain gpio: rcar: Move PM device over to irq domain gpio: omap: Move PM device over to irq domain gpio: mt7621: Kill parent_device usage irqchip/imx-intmux: Move PM device over to irq domain irqchip/renesas-irqc: Move PM device over to irq domain irqchip/renesas-intc-irqpin: Move PM device over to irq domain irqchip/gic: Move PM device over to irq domain genirq: Allow the PM device to originate from irq domain Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-02-09irqchip/stm32-exti: Add STM32MP13 supportAlexandre Torgue1-0/+50
Enhance stm32-exti driver to support STM32MP13 SoC. This SoC uses the same hardware version than STM32MP15. Only EXTI line mapping is changed and following EXTI lines are supported: GPIO, RTC, I2C[1-5], UxART[1-8], USBH_EHCI, USBH_OHCI, USB_OTG, LPTIM[1-5], ETH[1-2]. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220202140005.860-3-alexandre.torgue@foss.st.com
2022-02-09irqchip/imx-intmux: Move PM device over to irq domainMarc Zyngier1-5/+3
Move the reference to the device over to the irq domain. This allows the irq_chip structure to be directly used instead of taking a copy for each instance. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220201120310.878267-6-maz@kernel.org
2022-02-09irqchip/renesas-irqc: Move PM device over to irq domainMarc Zyngier1-1/+2
Move the reference to the device over to the irq domain. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220201120310.878267-5-maz@kernel.org
2022-02-09irqchip/renesas-intc-irqpin: Move PM device over to irq domainMarc Zyngier1-1/+2
Move the reference to the device over to the irq domain. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220201120310.878267-4-maz@kernel.org
2022-02-09irqchip/gic: Move PM device over to irq domainMarc Zyngier1-6/+6
Move the reference to the GIC device over to the irq domain. This allows for some localised cleanup. Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220201120310.878267-3-maz@kernel.org
2022-02-07irqchip/apple-aic: Move PMU-specific registers to their own include fileMarc Zyngier1-10/+1
As we are about to have a PMU driver, move the PMU bits from the AIC driver into a common include file. Reviewed-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-02-07irqchip/apple-aic: Wire PMU interruptsMarc Zyngier1-12/+22
Add the necessary code to configure and P and E-core PMU interrupts with their respective affinities. When such an interrupt fires, map it onto the right pseudo-interrupt. Reviewed-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-02-07irqchip/apple-aic: Parse FIQ affinities from device-treeMarc Zyngier1-0/+49
In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, parse the affinities kindly provided in the device-tree. Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-02-02irqchip/sifive-plic: Add missing thead,c900-plic match stringGuo Ren1-0/+1
The thead,c900-plic has been used in opensbi to distinguish PLIC [1]. Although PLICs have the same behaviors in Linux, they are different hardware with some custom initializing in firmware(opensbi). Qute opensbi patch commit-msg by Samuel: The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver. [1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6 Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: Anup Patel <anup@brainfault.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Samuel Holland <samuel@sholland.org> Cc: Thomas Gleixner <tglx@linutronix.de> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220130135634.1213301-3-guoren@kernel.org
2022-02-02irqchip/gic-v3-its: Skip HP notifier when no ITS is registeredMarc Zyngier1-0/+3
We have some systems out there that have both LPI support and an ITS, but that don't expose the ITS in their firmware tables (either because it is broken or because they run under a hypervisor that hides it...). Is such a configuration, we still register the HP notifier to free the allocated tables if needed, resulting in a warning as there is no memory to free (nothing was allocated the first place). Fix it by keying the HP notifier on the presence of at least one sucessfully probed ITS. Fixes: d23bc2bc1d63 ("irqchip/gic-v3-its: Postpone LPI pending table freeing and memreserve") Reported-by: Steev Klimaszewski <steev@kali.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Valentin Schneider <valentin.schneider@arm.com> Link: https://lore.kernel.org/r/20220202103454.2480465-1-maz@kernel.org
2022-01-29Merge tag 'irqchip-fixes-5.17-1' of ↵Thomas Gleixner4-30/+114
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent Pull irqchip fixes from Marc Zyngier: - Drop an unused private data field in the AIC driver - Various fixes to the realtek-rtl driver - Make the GICv3 ITS driver compile again in !SMP configurations - Force reset of the GICv3 ITSs at probe time to avoid issues during kexec - Yet another kfree/bitmap_free conversion - Various DT updates (Renesas, SiFive) Link: https://lore.kernel.org/r/20220128174217.517041-1-maz@kernel.org
2022-01-26irqchip/gic-v3-its: Reset each ITS's BASERn register before probeMarc Zyngier1-21/+99
A recent bug report outlined that the way GICv4.1 is handled across kexec is pretty bad. We can end-up in a situation where ITSs share memory (this is the case when SVPET==1) and reprogram the base registers, creating a situation where ITSs that are part of a given affinity group see different pointers. Which is illegal. Boo. In order to restore some sanity, reset the BASERn registers to 0 *before* probing any ITS. Although this isn't optimised at all, this is only a once-per-boot cost, which shouldn't show up on anyone's radar. Cc: Jay Chen <jkchen@linux.alibaba.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Link: https://lore.kernel.org/r/20211216190315.GA14220@lpieralisi Link: https://lore.kernel.org/r/20220124133809.1291195-1-maz@kernel.org
2022-01-22irqchip/gic-v3-its: Fix build for !SMPArd Biesheuvel1-1/+2
Commit 835f442fdbce ("irqchip/gic-v3-its: Limit memreserve cpuhp state lifetime") added a reference to cpus_booted_once_mask, which does not exist on !SMP builds, breaking the build for such configurations. Given the intent of the check, short circuit it to always pass. Cc: Valentin Schneider <valentin.schneider@arm.com> Fixes: 835f442fdbce ("irqchip/gic-v3-its: Limit memreserve cpuhp state lifetime") Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220122151614.133766-1-ardb@kernel.org
2022-01-17irqchip/loongson-pch-ms: Use bitmap_free() to free bitmapChristophe JAILLET1-1/+1
kfree() and bitmap_free() are the same. But using the latter is more consistent when freeing memory allocated with bitmap_zalloc(). Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/0b982ab54844803049c217b2899baa59602faacd.1640529916.git.christophe.jaillet@wanadoo.fr
2022-01-17irqchip/realtek-rtl: Service all pending interruptsSander Vanheule1-2/+6
Instead of only servicing the lowest pending interrupt line, make sure all pending SoC interrupts are serviced before exiting the chained handler. This adds a small overhead if only one interrupt is pending, but should prevent rapid re-triggering of the handler. Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/5082ad3cb8b4eedf55075561b93eff6570299fe1.1641739718.git.sander@svanheule.net
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