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2016-02-19irqchip/mvebu-odmi: Add new driver for platform MSI on Marvell 7K/8KThomas Petazzoni1-0/+1
This commits adds a new irqchip driver that handles the ODMI controller found on Marvell 7K/8K processors. The ODMI controller provide MSI interrupt functionality to on-board peripherals, much like the GIC-v2m. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2016-02-18irqchip/tango: Add support for Sigma Designs SMP86xx/SMP87xx interrupt ↵Mans Rullgard1-0/+1
controller This adds support for the secondary interrupt controller used in Sigma Designs SMP86xx and SMP87xx chips. Signed-off-by: Mans Rullgard <mans@mansr.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1453313237-18570-2-git-send-email-mans@mansr.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2016-02-17irqchip/ath79-cpu: Move the CPU IRQ driver from arch/mips/ath79/Alban Bedel1-0/+1
Signed-off-by: Alban Bedel <albeu@free.fr> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1453553867-27003-2-git-send-email-albeu@free.fr Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2016-02-17irqchip/ath79-misc: Move the MISC driver from arch/mips/ath79/Alban Bedel1-0/+1
The driver stays the same but the initialization changes a bit. For OF boards we now get the memory map from the OF node and use a linear mapping instead of the legacy mapping. For legacy boards we still use a legacy mapping and just pass down all the parameters from the board init code. Signed-off-by: Alban Bedel <albeu@free.fr> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.fr Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2016-02-16irqchip/armada-370-xp: Add Kconfig option for the driverThomas Petazzoni1-1/+1
Instead of building the irq-armada-370-xp driver directly when CONFIG_ARCH_MVEBU is enabled, this commit introduces an intermediate CONFIG_ARMADA_370_XP_IRQ hidden Kconfig option. This allows this option to select other interrupt-related Kconfig options (which will be needed in follow-up commits) rather than having such selects done from arch/arm/mach-<foo>/. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1455115621-22846-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2016-02-08irqchips/bmips: Add bcm6345-l1 interrupt controllerSimon Arlott1-0/+1
Add the BCM6345 interrupt controller based on the SMP-capable BCM7038 and the BCM3380 but with packed interrupt registers. Add the BCM6345 interrupt controller to a list with the existing BCM7038 so that interrupts on CPU1 are not ignored. Update the maintainers file list for BMIPS to include this driver. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Pawel Moll <pawel.moll@arm.com> Cc: linux-mips@linux-mips.org Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Rob Herring <robh@kernel.org> Link: http://lkml.kernel.org/r/5651D176.6030908@simon.arlott.org.uk Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-01-24Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+1
Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for 4.5 plus some 4.4 fixes. The executive summary: - ATH79 platform improvments, use DT bindings for the ATH79 USB PHY. - Avoid useless rebuilds for zboot. - jz4780: Add NEMC, BCH and NAND device tree nodes - Initial support for the MicroChip's DT platform. As all the device drivers are missing this is still of limited use. - Some Loongson3 cleanups. - The unavoidable whitespace polishing. - Reduce clock skew when synchronizing the CPU cycle counters on CPU startup. - Add MIPS R6 fixes. - Lots of cleanups across arch/mips as fallout from KVM. - Lots of minor fixes and changes for IEEE 754-2008 support to the FPU emulator / fp-assist software. - Minor Ralink, BCM47xx and bcm963xx platform support improvments. - Support SMP on BCM63168" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits) MIPS: zboot: Add support for serial debug using the PROM MIPS: zboot: Avoid useless rebuilds MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function MIPS: bcm963xx: Update bcm_tag field image_sequence MIPS: bcm963xx: Move extended flash address to bcm_tag header file MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure MIPS: bcm63xx: nvram: Use nvram structure definition from header file MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure MAINTAINERS: Add KVM for MIPS entry MIPS: KVM: Add missing newline to kvm_err() MIPS: Move KVM specific opcodes into asm/inst.h MIPS: KVM: Use cacheops.h definitions MIPS: Break down cacheops.h definitions MIPS: Use EXCCODE_ constants with set_except_vector() MIPS: Update trap codes MIPS: Move Cause.ExcCode trap codes to mipsregs.h MIPS: KVM: Make kvm_mips_{init,exit}() static MIPS: KVM: Refactor added offsetof()s MIPS: KVM: Convert EXPORT_SYMBOL to _GPL ...
2016-01-24IRQCHIP: irq-pic32-evic: Add support for PIC32 interrupt controllerCristian Birsan1-0/+1
This adds support for the interrupt controller present on PIC32 class devices. It handles all internal and external interrupts. This controller exists outside of the CPU core and is the arbitrator of all interrupts (including interrupts from the CPU itself) before they are presented to the CPU. The following features are supported: - DT properties for EVIC and for devices/peripherals that use interrupt lines - Persistent and non-persistent interrupt handling - irqdomain and generic chip support - Configuration of external interrupt edge polarity Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12092/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-29irqchip/ts4800: Add TS-4800 interrupt controllerDamien Riegel1-0/+1
This commit adds support for the TS-4800 interrupt controller. This controller is instantiated in a companion FPGA, and multiplex interrupts for other FPGA IPs. As this component is external to the SoC, the SoC might need to reserve pins, so this controller is implemented as a platform driver and doesn't use the IRQCHIP_DECLARE construct. Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: kernel@savoirfairelinux.com Link: http://lkml.kernel.org/r/1450728683-31416-2-git-send-email-damien.riegel@savoirfairelinux.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-12-19Merge branch 'irq/gic-4.5' of ↵Thomas Gleixner1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull the GIC related updates from Marc Zyngier: "Not a lot this time (what a relief!), but an interesting series from Linus Walleij coming out of his work converting the ARM RealView platforms to DT, and a couple of mundane fixes."
2015-12-18irqchip/mgigen: Add platform device driver for mbigen deviceMa Jun1-0/+1
Mbigen means Message Based Interrupt Generator(MBIGEN). Its a kind of interrupt controller that collects the interrupts from external devices and generate msi interrupt. Mbigen is applied to reduce the number of wire connected interrupts. As the peripherals increasing, the interrupts lines needed is increasing much, especially on the Arm64 server SOC. Therefore, the interrupt pin in GIC is not enough to cover so many peripherals. Mbigen is designed to fix this problem. Mbigen chip locates in ITS or outside of ITS. Mbigen chip hardware structure shows as below: mbigen chip |---------------------|-------------------| mgn_node0 mgn_node1 mgn_node2 | |-------| |-------|------| dev1 dev1 dev2 dev1 dev3 dev4 Each mbigen chip contains several mbigen nodes. External devices can connect to mbigen node through wire connecting way. Because a mbigen node only can support 128 interrupt maximum, depends on the interrupt lines number of devices, a device can connects to one more mbigen nodes. Also, several different devices can connect to a same mbigen node. When devices triggered interrupt,mbigen chip detects and collects the interrupts and generates the MBI interrupts by writing the ITS Translator register. To simplify mbigen driver,I used a new conception--mbigen device. Each mbigen device is initialized as a platform device. Mbigen device presents the parts(register, pin definition etc.) in mbigen chip corresponding to a peripheral device. So from software view, the structure likes below mbigen chip |---------------------|-----------------| mbigen device1 mbigen device2 mbigen device3 | | | dev1 dev2 dev3 Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ma Jun <majun258@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-16irqchip/gic: Support RealView variant setupLinus Walleij1-0/+1
The ARM RealView PB11MPCore reference design has some special bits in a system controller register to set up the GIC in one of three modes: legacy, new with DCC, new without DCC. The register is also used to enable FIQ. Since the platform will not boot unless this register is set up to "new with DCC" mode, we need a special quirk to be compiled-in for the RealView platforms. If we find the right compatible string on the GIC TestChip, we enable this quirk by looking up the system controller and enabling the special bits. We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old boardfile code has the same fix hardcoded, and this is only needed for the attempts to modernize the RealView code using device tree. After fixing this, the PB11MPCore boots with device tree only. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-10-14irqchip/mxs: Add Alphascale ASM9260 supportOleksij Rempel1-1/+1
Freescale iMX23/iMX28 and Alphascale ASM9260 have similar interrupt collectors. We already prepared the mxs driver to handle a different register layout. Add the actual ASM9260 support. Differences between these devices: - Different register offsets - Different count of interupt lines per register - ASM9260 does not provide reset bit - ASM9260 does not support FIQ. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: marc.zyngier@arm.com Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1444677334-12242-6-git-send-email-linux@rempel-privat.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-08-24irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sourcesShenwei Wang1-0/+1
IMX7D contains a new version of GPC IP block (GPCv2). It has two major functions: power management and wakeup source management. When the system is in WFI (wait for interrupt) mode, the GPC block will be the first block on the platform to be activated and signaled. In normal wait mode during cpu idle, the system can be woken up by any enabled interrupts. In standby or suspend mode, the system can only be wokem up by the pre-defined wakeup sources. Based-on-patch-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <shawn.guo@linaro.org> Cc: <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1440443055-7291-1-git-send-email-shenwei.wang@freescale.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-08-20irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2Eric Anholt1-0/+1
This interrupt controller is the new root interrupt controller with the timer, PMU events, and IPIs, and the bcm2835's interrupt controller is chained off of it to handle the peripherals. I wrote the interrupt chip support, while Andrea Merello wrote the IPI code. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: linux-rpi-kernel@lists.infradead.org Cc: Lee Jones <lee@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1438902033-31477-5-git-send-email-eric@anholt.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-31MIPS/irqchip: Move i8259 irqchip driver to drivers/irqchipRalf Baechle1-0/+1
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-30irqchip/gicv3-its: Add platform MSI supportMarc Zyngier1-1/+1
In order to support non-PCI MSI with the GICv3 ITS, add the minimal required entry points for the MSI domain (an msi_prepare implementation). The rest is only boilerplate code to find the raw ITS domain. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Ma Jun <majun258@huawei.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Duc Dang <dhdang@apm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1438091186-10244-16-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-30irqchip/gicv3-its: Split PCI/MSI code from the core ITS driverMarc Zyngier1-1/+1
It is becoming obvious that having the PCI/MSI code in the same file as the the core ITS code is giving people implementing non-PCI MSI support the wrong kind of idea. In order to make things a bit clearer, let's move the PCI/MSI code out to its own file. Hopefully it will make it clear that whoever thinks of hooking into the core ITS better have a very strong point. We use a temporary entry point that will get removed in a subsequent patch, once the proper infrastructure is added. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Ma Jun <majun258@huawei.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Duc Dang <dhdang@apm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1438091186-10244-12-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-27Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+2
Pull MIPS updates from Ralf Baechle: - Improvements to the tlb_dump code - KVM fixes - Add support for appended DTB - Minor improvements to the R12000 support - Minor improvements to the R12000 support - Various platform improvments for BCM47xx - The usual pile of minor cleanups - A number of BPF fixes and improvments - Some improvments to the support for R3000 and DECstations - Some improvments to the ATH79 platform support - A major patchset for the JZ4740 SOC adding support for the CI20 platform - Add support for the Pistachio SOC - Minor BMIPS/BCM63xx platform support improvments. - Avoid "SYNC 0" as memory barrier when unlocking spinlocks - Add support for the XWR-1750 board. - Paul's __cpuinit/__cpuinitdata cleanups. - New Malta CPU board support large memory so enable ZONE_DMA32. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits) MIPS: spinlock: Adjust arch_spin_lock back-off time MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA MIPS: BCM47xx: Simplify handling SPROM revisions MIPS: Cobalt Don't use module_init in non-modular MTD registration. MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/ MIPS: use for_each_sg() MIPS: BCM47xx: Don't select BCMA_HOST_PCI MIPS: BCM47xx: Add helper variable for storing NVRAM length MIPS: IRQ/IP27: Move IRQ allocation API to platform code. MIPS: Replace smp_mb with release barrier function in unlocks. MIPS: i8259: DT support MIPS: Malta: Basic DT plumbing MIPS: include errno.h for ENODEV in mips-cm.h MIPS: Define GCR_GIC_STATUS register fields MIPS: BPF: Introduce BPF ASM helpers MIPS: BPF: Use BPF register names to describe the ABI MIPS: BPF: Move register definition to the BPF header MIPS: net: BPF: Replace RSIZE with SZREG MIPS: BPF: Free up some callee-saved registers MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers ...
2015-06-26Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds1-0/+1
Pull ARM updates from Russell King: "Bigger items included in this update are: - A series of updates from Arnd for ARM randconfig build failures - Updates from Dmitry for StrongARM SA-1100 to move IRQ handling to drivers/irqchip/ - Move ARMs SP804 timer to drivers/clocksource/ - Perf updates from Mark Rutland in preparation to move the ARM perf code into drivers/ so it can be shared with ARM64. - MCPM updates from Nicolas - Add support for taking platform serial number from DT - Re-implement Keystone2 physical address space switch to conform to architecture requirements - Clean up ARMv7 LPAE code, which goes in hand with the Keystone2 changes. - L2C cleanups to avoid unlocking caches if we're prevented by the secure support to unlock. - Avoid cleaning a potentially dirty cache containing stale data on CPU initialisation - Add ARM-only entry point for secondary startup (for machines that can only call into a Thumb kernel in ARM mode). Same thing is also done for the resume entry point. - Provide arch_irqs_disabled via asm-generic - Enlarge ARMv7M vector table - Always use BFD linker for VDSO, as gold doesn't accept some of the options we need. - Fix an incorrect BSYM (for Thumb symbols) usage, and convert all BSYM compiler macros to a "badr" (for branch address). - Shut up compiler warnings provoked by our cmpxchg() implementation. - Ensure bad xchg sizes fail to link" * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (75 commits) ARM: Fix build if CLKDEV_LOOKUP is not configured ARM: fix new BSYM() usage introduced via for-arm-soc branch ARM: 8383/1: nommu: avoid deprecated source register on mov ARM: 8391/1: l2c: add options to overwrite prefetching behavior ARM: 8390/1: irqflags: Get arch_irqs_disabled from asm-generic ARM: 8387/1: arm/mm/dma-mapping.c: Add arm_coherent_dma_mmap ARM: 8388/1: tcm: Don't crash when TCM banks are protected by TrustZone ARM: 8384/1: VDSO: force use of BFD linker ARM: 8385/1: VDSO: group link options ARM: cmpxchg: avoid warnings from macro-ized cmpxchg() implementations ARM: remove __bad_xchg definition ARM: 8369/1: ARMv7M: define size of vector table for Vybrid ARM: 8382/1: clocksource: make ARM_TIMER_SP804 depend on GENERIC_SCHED_CLOCK ARM: 8366/1: move Dual-Timer SP804 driver to drivers/clocksource ARM: 8365/1: introduce sp804_timer_disable and remove arm_timer.h inclusion ARM: 8364/1: fix BE32 module loading ARM: 8360/1: add secondary_startup_arm prototype in header file ARM: 8359/1: correct secondary_startup_arm mode ARM: proc-v7: sanitise and document registers around errata ARM: proc-v7: clean up MIDR access ...
2015-06-23h8300: IRQ chip driverYoshinori Sato1-0/+2
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
2015-06-21MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchipPaul Burton1-0/+1
Move the driver for Ingenic SoC interrupt controllers into drivers/irqchip where it belongs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10147/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.Ralf Baechle1-0/+1
While at it, rename it because in drivers/irqchip no longer every CPU is a MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-28ARM: 8368/1: sa1100: move irq driver to drivers/irqchip/Dmitry Eremin-Solenikov1-0/+1
Move current sa11x0 IRQ driver to the irqchip subsystem. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-17Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+1
Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for Linux 4.1. Most noteworthy: - Add more Octeon-optimized crypto functions - Octeon crypto preemption and locking fixes - Little endian support for Octeon - Use correct CSR to soft reset Octeons - Support LEDs on the Octeon-based DSR-1000N - Fix PCI interrupt mapping for the Octeon-based DSR-1000N - Mark prom_free_prom_memory() as __init for a number of systems - Support for Imagination's Pistachio SOC. This includes arch and CLK bits. I'd like to merge pinctrl bits later - Improve parallelism of csum_partial for certain pipelines - Organize DTB files in subdirs like other architectures - Implement read_sched_clock for all MIPS platforms other than Octeon - Massive series of 38 fixes and cleanups for the FPU emulator / kernel - Further FPU remulator work to support new features. This sits on a separate branch which also has been pulled into the 4.1 KVM branch - Clean up and fixes for the SEAD3 eval board; remove unused file - Various updates for Netlogic platforms - A number of small updates for Loongson 3 platforms - Increase the memory limit for ATH79 platforms to 256MB - A fair number of fixes and updates for BCM47xx platforms - Finish the implementation of XPA support - MIPS FDC support. No, not floppy controller but Fast Debug Channel :) - Detect the R16000 used in SGI legacy platforms - Fix Kconfig dependencies for the SSB bus support" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits) MIPS: Makefile: Fix MIPS ASE detection code MIPS: asm: elf: Set O32 default FPU flags MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G MIPS: Kconfig: Disable SMP/CPS for 64-bit MIPS: Hibernate: flush TLB entries earlier MIPS: smp-cps: cpu_set FPU mask if FPU present MIPS: lose_fpu(): Disable FPU when MSA enabled MIPS: ralink: add missing symbol for RALINK_ILL_ACC MIPS: ralink: Fix bad config symbol in PCI makefile. SSB: fix Kconfig dependencies MIPS: Malta: Detect and fix bad memsize values Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores." MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard. MIPS: Fix cpu_has_mips_r2_exec_hazard. MIPS: kernel: entry.S: Set correct ISA level for mips_ihb MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter MIPS: unaligned: Fix regular load/store instruction emulation for EVA MIPS: unaligned: Surround load/store macros in do {} while statements ...
2015-04-11Merge branch 'irqchip/stacked-tegra' into irqchip/coreJason Cooper1-0/+1
2015-04-01IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllersKevin Cernekee1-0/+1
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips; it has the following characteristics: - 64 to 160+ level IRQs - Atomic set/clear registers - Reasonably predictable register layout (N status words, then N mask status words, then N mask set words, then N mask clear words) - SMP affinity supported on most systems - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3 This driver registers one IRQ domain and one IRQ chip to cover all instances of the block. Up to 4 instances of the block may appear, as it supports 4-way IRQ affinity on BCM7435. The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC is used instead. So this driver is primarily intended for MIPS STB chips. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8844/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-03-15Merge branch 'irqchip/vybrid' into irqchip/coreJason Cooper1-0/+1
2015-03-15irqchip: tegra: Add DT-based support for legacy interrupt controllerMarc Zyngier1-0/+1
Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked IRQ domain framework fits this pretty well, and allows the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-08irqchip: vf610-mscm-ir: Add support for Vybrid MSCM interrupt routerStefan Agner1-0/+1
This adds support for Vybrid's interrupt router. On VF6xx models, almost all peripherals can be used by either of the two CPU's, the Cortex-A5 or the Cortex-M4. The interrupt router routes the peripheral interrupts to the configured CPU. This IRQ chip driver configures the interrupt router to route the requested interrupt to the CPU the kernel is running on. The driver makes use of the irqdomain hierarchy support. The parent is given by the device tree. This should be one of the two possible parents either ARM GIC or the ARM NVIC interrupt controller. The latter is currently not yet supported. Note that there is no resource control mechnism implemented to avoid concurrent access of the same peripheral. The user needs to make sure to use device trees which assign the peripherals orthogonally. However, this driver warns the user in case the interrupt is already configured for the other CPU. This provides a poor man's resource controller. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Link: https://lkml.kernel.org/r/1425249689-32354-2-git-send-email-stefan@agner.ch Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-03irqchip: st: Supply new driver for STi based devicesLee Jones1-0/+1
This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lkml.kernel.org/r/1424272444-16230-3-git-send-email-lee.jones@linaro.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-01-26irqchip: Conexant CX92755 interrupts controller driverBaruch Siach1-0/+1
Add interrupt controller driver to the Conexant CX92755 SoC, part of the Digicolor SoCs series. Use the generic irq framework support. Use syscon to access the system global UC_IRQ_CONTROL register. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Cc: linux-arm-kernel@lists.infradead.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/5b769e3c23dfa5fde08c4f3bc966c2c2b3921d8a.1421317616.git.baruch@tkos.co.il Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-12-16Merge branch 'irq-irqdomain-arm-for-linus' of ↵Linus Torvalds1-0/+3
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq domain ARM updates from Thomas Gleixner: "This set of changes make use of hierarchical irqdomains to provide: - MSI/ITS support for GICv3 - MSI support for GICv2m - Interrupt polarity extender for GICv1 Marc has come more cleanups for the existing extension hooks of GIC in the pipeline, but they are going to be 3.20 material" * 'irq-irqdomain-arm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) irqchip: gicv3-its: Fix ITT allocation irqchip: gicv3-its: Move some alloc/free code to activate/deactivate irqchip: gicv3-its: Fix domain free in multi-MSI case irqchip: gic: Remove warning by including linux/irqdomain.h irqchip: gic-v2m: Add DT bindings for GICv2m irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell irqchip: mtk-sysirq: dt-bindings: Add bindings for mediatek sysirq irqchip: mtk-sysirq: Add sysirq interrupt polarity support irqchip: gic: Support hierarchy irq domain. irqchip: GICv3: Binding updates for ITS irqchip: GICv3: ITS: enable compilation of the ITS driver irqchip: GICv3: ITS: plug ITS init into main GICv3 code irqchip: GICv3: ITS: DT probing and initialization irqchip: GICv3: ITS: MSI support irqchip: GICv3: ITS: device allocation and configuration irqchip: GICv3: ITS: tables allocators irqchip: GICv3: ITS: LPI allocator irqchip: GICv3: ITS: irqchip implementation irqchip: GICv3: ITS command queue irqchip: GICv3: rework redistributor structure ...
2014-12-12Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+1
Pull MIPS updates from Ralf Baechle: "This is an unusually large pull request for MIPS - in parts because lots of patches missed the 3.18 deadline but primarily because some folks opened the flood gates. - Retire the MIPS-specific phys_t with the generic phys_addr_t. - Improvments for the backtrace code used by oprofile. - Better backtraces on SMP systems. - Cleanups for the Octeon platform code. - Cleanups and fixes for the Loongson platform code. - Cleanups and fixes to the firmware library. - Switch ATH79 platform to use the firmware library. - Grand overhault to the SEAD3 and Malta interrupt code. - Move the GIC interrupt code to drivers/irqchip - Lots of GIC cleanups and updates to the GIC code to use modern IRQ infrastructures and features of the kernel. - OF documentation updates for the GIC bindings - Move GIC clocksource driver to drivers/clocksource - Merge GIC clocksource driver with clockevent driver. - Further updates to bring the GIC clocksource driver up to date. - R3000 TLB code cleanups - Improvments to the Loongson 3 platform code. - Convert pr_warning to pr_warn. - Merge a bunch of small lantiq and ralink fixes that have been staged/lingering inside the openwrt tree for a while. - Update archhelp for IP22/IP32 - Fix a number of issues for Loongson 1B. - New clocksource and clockevent driver for Loongson 1B. - Further work on clk handling for Loongson 1B. - Platform work for Broadcom BMIPS. - Error handling cleanups for TurboChannel. - Fixes and optimization to the microMIPS support. - Option to disable the FTLB. - Dump more relevant information on machine check exception - Change binfmt to allow arch to examine PT_*PROC headers - Support for new style FPU register model in O32 - VDSO randomization. - BCM47xx cleanups - BCM47xx reimplement the way the kernel accesses NVRAM information. - Random cleanups - Add support for ATH25 platforms - Remove pointless locking code in some PCI platforms. - Some improvments to EVA support - Minor Alchemy cleanup" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits) MIPS: Add MFHC0 and MTHC0 instructions to uasm. MIPS: Cosmetic cleanups of page table headers. MIPS: Add CP0 macros for extended EntryLo registers MIPS: Remove now unused definition of phys_t. MIPS: Replace use of phys_t with phys_addr_t. MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig. MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO MIPS: <asm/types.h> fix indentation. MAINTAINERS: Add entry for BMIPS multiplatform kernel MIPS: Enable VDSO randomization MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration MIPS: Remove declaration of obsolete arch_init_clk_ops() MIPS: atomic.h: Reformat to fit in 79 columns MIPS: Apply `.insn' to fixup labels throughout MIPS: Fix microMIPS LL/SC immediate offsets MIPS: Kconfig: Only allow 32-bit microMIPS builds MIPS: signal.c: Fix an invalid cast in ISA mode bit handling MIPS: mm: Only build one microassembler that is suitable ...
2014-11-26irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbellSuravee Suthikulpanit1-0/+1
ARM GICv2m specification extends GICv2 to support MSI(-X) with a new register frame. This allows a GICv2 based system to support MSI with minimal changes. Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> [maz: converted the driver to use stacked irq domains, updated changelog] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416941243-7181-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-26irqchip: mtk-sysirq: Add sysirq interrupt polarity supportYingjoe Chen1-0/+1
Mediatek SoCs have interrupt polarity support in sysirq which allows to invert polarity for given interrupt. Add this support using hierarchy irq domain. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Link: https://lkml.kernel.org/r/1416902662-19281-3-git-send-email-yingjoe.chen@mediatek.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-26irqchip: GICv3: ITS: enable compilation of the ITS driverMarc Zyngier1-0/+1
Get the show on the road... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-13-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-24MIPS: Move GIC to drivers/irqchip/Andrew Bresticker1-0/+1
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7812/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-09irqchip: bcm7120-l2: Decouple driver from brcmstb-l2Kevin Cernekee1-2/+2
Some chips, such as BCM6328, only require bcm7120-l2. Some BCM7xxx STB configurations only require brcmstb-l2. Treat them as two separate entities, and update the mach-bcm dependencies to reflect the change. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1415342669-30640-13-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-10-09Merge branch 'irq-core-for-linus' of ↵Linus Torvalds1-1/+4
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "The irq departement delivers: - a cleanup series to get rid of mindlessly copied code. - another bunch of new pointlessly different interrupt chip drivers. Adding homebrewn irq chips (and timers) to SoCs must provide a value add which is beyond the imagination of mere mortals. - the usual SoC irq controller updates, IOW my second cat herding project" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits) irqchip: gic-v3: Implement CPU PM notifier irqchip: gic-v3: Refactor gic_enable_redist to support both enabling and disabling irqchip: renesas-intc-irqpin: Add minimal runtime PM support irqchip: renesas-intc-irqpin: Add helper variable dev = &pdev->dev irqchip: atmel-aic5: Add sama5d4 support irqchip: atmel-aic5: The sama5d3 has 48 IRQs Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller irqchip: renesas-irqc: Add binding docs for new R-Car Gen2 SoCs irqchip: renesas-irqc: Add DT binding documentation irqchip: renesas-intc-irqpin: Document SoC-specific bindings openrisc: Get rid of handle_IRQ arm64: Get rid of handle_IRQ ARM: omap2: irq: Convert to handle_domain_irq ARM: imx: tzic: Convert to handle_domain_irq ARM: imx: avic: Convert to handle_domain_irq irqchip: or1k-pic: Convert to handle_domain_irq irqchip: atmel-aic5: Convert to handle_domain_irq irqchip: atmel-aic: Convert to handle_domain_irq irqchip: gic-v3: Convert to handle_domain_irq ...
2014-10-02Merge branch 'irqchip/broadcom' into irqchip/coreJason Cooper1-1/+2
Conflicts: drivers/irqchip/Makefile
2014-09-17arm: omap: irq: move irq.c to drivers/irqchip/Felipe Balbi1-0/+1
Just move the code over as it has no dependencies on arch/arm/ anymore. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-14Merge branch 'irqchip/hip04' into irqchip/coreJason Cooper1-0/+1
2014-09-14irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controllerFlorian Fainelli1-1/+2
This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using a single enable register. This interrupt controller is always present on the platforms supported by the irq-brcmstb-l2 driver, hence the reason why both are compiled using the same Kconfig symbol. [jac] removed the following warning: drivers/irqchip/irq-bcm7120-l2.c: In function 'bcm7120_l2_intc_irq_handle': drivers/irqchip/irq-bcm7120-l2.c:49:27: warning: unused variable 'gc' [-Wunused-variable] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1410309862-27784-2-git-send-email-f.fainelli@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-08-20irqchip: hip04: Enable Hisilicon HiP04 interrupt controllerHaojian Zhuang1-0/+1
HiP04 GIC is the variate of ARM GICv2. ARM GICv2 supports 8 cores. HiP04 GIC extends to support 16 cores. It results that bit fields in GIC_DIST_TARGET & GIC_DIST_SOFTINT are different from ARM GICv2. And the maximium IRQ is downgrade from 1020 to 510. Since different register offset & bitfields definitation breaks compartible with ARM GICv2, create a new hip04 irq driver. And this driver is derived from irq-gic.c to support the Hisilicon HiP04 interrupt controller, which is similar to the GIC, but deviates at some points. Support for power management, non-banked registers, cascaded GICs (and multiple controllers in general) and bigLittle support has been removed from the GIC driver. Affinity related functions have been adjusted to match the Hisilicon hardware implementation. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Link: https://lkml.kernel.org/r/1407408695-19626-9-git-send-email-haojian.zhuang@linaro.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-08-17irqchip: keystone: Add irq controller ip driverGrygorii Strashko1-0/+1
On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx registers. This is one of the component used by the IPC mechanism used on Keystone SOCs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lkml.kernel.org/r/1406126430-9978-1-git-send-email-grygorii.strashko@ti.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-19Merge branch 'irqchip/atmel-aic' into irqchip/coreJason Cooper1-0/+2
Topic branch set up to facilitate merging the rest of the series which removes the driver from arch code.
2014-07-19Merge tag 'tags/deps-irqchip-gic-3.17' into irqchip/coreJason Cooper1-1/+2
From local branch irqchip/gic, this is topic branch that was set up to facilitate merging other changes depending on the new GICv3 driver.
2014-07-17irqchip: atmel-aic: Add atmel AIC/AIC5 driversBoris BREZILLON1-0/+2
Add AIC (Advanced Interrupt Controller) and AIC5 (AIC5 is an evolution of the AIC block) drivers. Put common code in irq-atmel-aic-common.c/.h so that both driver can access shared functions (this will ease maintenance). These drivers are only compatible with dt enabled board and replace the old implementation found in arch/arm/mach-at91/irq.c. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Link: https://lkml.kernel.org/r/1405012462-766-4-git-send-email-boris.brezillon@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-09irqchip: gic-v3: Initial support for GICv3Marc Zyngier1-0/+1
The Generic Interrupt Controller (version 3) offers services that are similar to GICv2, with a number of additional features: - Affinity routing based on the CPU MPIDR (ARE) - System register for the CPU interfaces (SRE) - Support for more that 8 CPUs - Locality-specific Peripheral Interrupts (LPIs) - Interrupt Translation Services (ITS) This patch adds preliminary support for GICv3 with ARE and SRE, non-secure mode only. It relies on higher exception levels to grant ARE and SRE access. Support for LPI and ITS will be added at a later time. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Zi Shen Lim <zlim@broadcom.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> Reviewed-by: Yun Wu <wuyun.wu@huawei.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com> Tested-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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