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path: root/drivers/i2c
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2019-02-23i2c: tegra: remove master fifo support on tegra186Sowjanya Komatineni1-1/+1
Tegra186 does not have master FIFO control register and instead uses FIFO control register like prior Tegra chipset. This patch fixes this and prevents crashing during boot when accessing FIFO control registers. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-16i2c: tegra: change phrasing, "fallbacking" to "falling back"Colin Ian King1-2/+2
The phrasing in two dev_err messages is using fallbacking which os less understandable than "falling back", so fix this up. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-15i2c: expand minor range when registering chrdev regionChengguang Xu1-1/+1
Actually, total amount of available minor number for a single major is MINORMASK + 1. So expand minor range when registering chrdev region. Signed-off-by: Chengguang Xu <cgxu519@gmx.com> [wsa: fixed typo in commit message] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-15i2c: aspeed: Add multi-master use case supportJae Hyun Yoo1-26/+93
In multi-master environment, this driver's master cannot know exactly when a peer master sends data to this driver's slave so cases can be happened that this master tries sending data through the master_xfer function but slave data from a peer master is still being processed or slave xfer is started by a peer immediately after it queues a master command. To support multi-master use cases properly, this H/W provides arbitration in physical level and it provides priority based command handling too to avoid conflicts in multi-master environment, means that if a master and a slave events happen at the same time, H/W will handle a higher priority event first and a pending event will be handled when bus comes back to the idle state. To support this H/W feature properly, this patch adds the 'pending' state of master and its handling code so that the pending master xfer can be continued after slave operation properly. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-15i2c: bcm2835: Clear current buffer pointers and counts after a transferPaul Kocialkowski1-0/+12
The driver's interrupt handler checks whether a message is currently being handled with the curr_msg pointer. When it is NULL, the interrupt is considered to be unexpected. Similarly, the i2c_start_transfer routine checks for the remaining number of messages to handle in num_msgs. However, these values are never cleared and always keep the message and number relevant to the latest transfer (which might be done already and the underlying message memory might have been freed). When an unexpected interrupt hits with the DONE bit set, the isr will then try to access the flags field of the curr_msg structure, leading to a fatal page fault. The msg_buf and msg_buf_remaining fields are also never cleared at the end of the transfer, which can lead to similar pitfalls. Fix these issues by introducing a cleanup function and always calling it after a transfer is finished. Fixes: e2474541032d ("i2c: bcm2835: Fix hang for writing messages larger than 16 bytes") Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-15i2c: cadence: Fix the hold bit settingShubhrajyoti Datta1-2/+7
In case the hold bit is not needed we are carrying the old values. Fix the same by resetting the bit when not needed. Fixes the sporadic i2c bus lockups on National Instruments Zynq-based devices. Fixes: df8eb5691c48 ("i2c: Add driver for Cadence I2C controller") Reported-by: Kyle Roeschley <kyle.roeschley@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Tested-by: Kyle Roeschley <kyle.roeschley@ni.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: core-smbus: don't trace smbus_reply data on errorsJohn Sperbeck1-1/+1
If an smbus transfer fails, there's no guarantee that the output buffer was written. So, avoid trying to show the output buffer when tracing after an error. This was 'mostly harmless', but would trip up kasan checking if left-over cruft in byte 0 is a large length, causing us to read from unwritten memory. Signed-off-by: John Sperbeck <jsperbeck@google.com> Reviewed-by: Steven Rostedt (VMware) <rostedt@goodmis.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: ocores: Add support for bus clock via platform dataAndrew Lunn1-1/+4
Add the I2C bus clock speed to the platform data structure. If not set, default to 100KHz as before. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: ocores: Add support for IO mapper registers.Andrew Lunn1-3/+29
Some implementations of the OCORES i2c bus master use IO mapped registers. Add support for getting the IO registers from the platform data, and register accessor functions. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: ocores: checkpatch fixesFederico Vaga1-11/+18
Miscellaneous style fixes from checkpatch Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: ocores: add SPDX tagFederico Vaga1-4/+1
It adds the SPDX tag and it removes the old text about the GPLv2. Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: ocores: add polling interfaceFederico Vaga1-21/+161
This driver assumes that an interrupt line is always available for the I2C master. This is not always the case and this patch adds support for a polling version. Report from Andrew Lunn: I did some timing tests for this. On my box, we request a udelay of 80uS. The kernel actually delays for about 79uS. We then spin in ocores_wait() for an additional 10-11uS, which is 3 to 4 iterations. There are actually 9 bits on the wire, not 8, since there is an ACK/NACK bit after the actual data transfer. So i changed the delay to (9 * 1000) / i2c->bus_clock_khz. That resulted in ocores_wait() mostly not looping at all. But for reading an 4K AT24 EEPROM, it increased the read time by 10ms, from 424ms to 434ms. So we should probably keep with 8. Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: ocores: do not handle IRQ if IF is not setFederico Vaga1-3/+6
If the Interrupt Flag (IF) is not set, we should not handle the IRQ: - the line can be shared with other devices - it can be a spurious interrupt To avoid reading twice the status register, the ocores_process() function expects it to be read by the caller. Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Acked-by: Peter Korsgaard <peter@korsgaard.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: ocores: stop transfer on timeoutFederico Vaga1-9/+45
Detecting a timeout is ok, but we also need to assert a STOP command on the bus in order to prevent it from generating interrupts when there are no on going transfers. Example: very long transmission. 1. ocores_xfer: START a transfer 2. ocores_isr : handle byte by byte the transfer 3. ocores_xfer: goes in timeout [[bugfix here]] 4. ocores_xfer: return to I2C subsystem and to the I2C driver 5. I2C driver : it may clean up the i2c_msg memory 6. ocores_isr : receives another interrupt (pending bytes to be transferred) but the i2c_msg memory is invalid now So, since the transfer was too long, we have to detect the timeout and STOP the transfer. Another point is that we have a critical region here. When handling the timeout condition we may have a running IRQ handler. For this reason I introduce a spinlock. In order to make easier to understan locking I have: - added a new function to handle timeout - modified the current ocores_process() function in order to be protected by the new spinlock Like this it is obvious at first sight that this locking serializes the execution of ocores_process() and ocores_process_timeout() Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: add i2c interface timing supportSowjanya Komatineni1-30/+159
This patch adds I2C interface timing registers support for proper bus rate configuration along with meeting the I2C spec setup and hold times based on the tuning performed on Tegra210, Tegra186 and Tegra194 platforms. I2C_INTERFACE_TIMING_0 register contains TLOW and THIGH field and Tegra I2C controller design uses them as a part of internal clock divisor. I2C_INTERFACE_TIMING_1 register contains the setup and hold times for start and stop conditions. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: update transfer timeoutSowjanya Komatineni1-4/+11
Tegra194 allows max of 64K bytes and Tegra186 and prior allows max of 4K bytes of transfer per packet. one sec timeout is not enough for transfers more than 10K bytes at STD bus rate. This patch updates I2C transfer timeout based on the transfer size and I2C bus rate to allow enough time during max transfer size at lower bus speed. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: Add DMA supportSowjanya Komatineni1-49/+383
This patch adds DMA support for Tegra I2C. Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for transfer size of the max FIFO depth and DMA mode is used for transfer size higher than max FIFO depth to save CPU overhead. PIO mode needs full intervention of CPU to fill or empty FIFO's and also need to service multiple data requests interrupt for the same transaction. This adds delay between data bytes of the same transfer when CPU is fully loaded and some slave devices has internal timeout for no bus activity and stops transaction to avoid bus hang. DMA mode is helpful in such cases. DMA mode is also helpful for Large transfers during downloading or uploading FW over I2C to some external devices. Tegra210 and prior Tegra chips use APBDMA driver which is replaced with GPCDMA on Tegra186 and Tegra194. This patch uses has_apb_dma flag in hw_feature to differentiate DMA driver change between Tegra chipset. APBDMA driver is registered from module-init level and this patch also has a change to register I2C driver at module-init level rather than subsys-init to avoid deferring I2C probe till APBDMA driver is registered. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: update maximum transfer sizeSowjanya Komatineni1-2/+6
Tegra194 supports maximum 64K bytes per packet including 12 bytes of packet header irrespective of PIO or DMA mode transfer. This patch updates Tegra194 max write length to account for packet header size for transfers. Cc: stable@vger.kernel.org # 4.20+ Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: fix maximum transfer sizeSowjanya Komatineni1-1/+1
Tegra186 and prior supports maximum 4K bytes per packet transfer including 12 bytes of packet header. This patch fixes max write length limit to account packet header size for transfers. Cc: stable@vger.kernel.org # 4.4+ Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: add bus clear Master SupportSowjanya Komatineni1-0/+81
Bus clear feature of Tegra I2C controller helps to recover from bus hang when I2C master loses the bus arbitration due to the slave device holding SDA LOW continuously for some unknown reasons. Per I2C specification, the device that held the bus LOW should release it within 9 clock pulses. During bus clear operation, Tegra I2C controller sends 9 clock pulses and terminates the transaction with STOP condition. Upon successful bus clear operation, bus goes to idle state and driver retries the transaction. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: sort all the include headers alphabeticallySowjanya Komatineni1-11/+8
This patch sorts all the include headers alphabetically for the I2C Tegra driver. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14Merge branch 'i2c/for-current' into i2c/for-5.1Wolfram Sang3-9/+25
2019-02-09i2c: rcar: refactor TCYC handlingWolfram Sang1-9/+6
The latest documentation made it clear that we need to initialize the TCYC value independently of DMA. The old code used TCYC06 (wrongly) for non-DMA transfers. The new code sets TCYC up independently from DMA. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-09i2c: gpio: merge two very similar commentsWolfram Sang1-12/+5
I think it is clear enough if we have the explanation once and make it clear it is applicable for both SCL and SDA. Reword it a little with the help of Simon's native language skills :) Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-09i2c: sh_mobile: use new clock calculation formulas for Gen2Wolfram Sang1-5/+5
We measured the clock on a Lager and an Ebisu board. The new formula gives better results for both. So after Gen3, switch to this formula for all Gen2 SoCs. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-09i2c: sh_mobile: use new clock calculation formulas for Gen3Wolfram Sang1-3/+3
We could finally measure the clock on an Ebisu board. The new formula gives way better results, i.e. 100kHz instead of 106kHz and 400kHz instead of 387kHz. Switch to these formulas for all Gen3 SoCs. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-09i2c: sh_mobile: sort compatible entriesWolfram Sang1-2/+2
Makes it easier to add new ones. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-09i2c: cbus-gpio: Switch to use GPIO descriptorsLinus Walleij1-50/+30
This augments the CBUS GPIO I2C driver to use GPIO descriptors for clock, sel and data. We drop the platform data that was only used for carrying GPIO numbers and use machine descriptor tables instead. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: rcar: comment maintenanceWolfram Sang1-5/+2
Update copyright years and remove a comment which grew incorrect and useless over time. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: gpio: fault-injector: sort debugfs files alphabeticallyWolfram Sang1-2/+2
There is no value in chronological sorting. Make it easier to follow for humans. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: mediatek: remove completion_done()qii wang1-2/+0
Completion_done() is useless when we don't use its return value, so we remove it. Signed-off-by: qii wang <qii.wang@mediatek.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: mediatek: speeds is replaced by macros definitionsqii wang1-2/+2
Different speeds have been defined by macros, so we use macros definitions. Signed-off-by: qii wang <qii.wang@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: gpio: sort includesWolfram Sang1-5/+5
Less risk for duplications when adding new ones. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: algo-bit: convert to SPDX headerWolfram Sang1-17/+8
And use kernel style for the remaining comments in the header. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: iop3xx: Add device tree probingLinus Walleij1-0/+8
This adds device tree probing support for the IOP3xx I2C master. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: of: Try to find an I2C adapter matching the parentThierry Reding1-1/+13
If an I2C adapter doesn't match the provided device tree node, also try matching the parent's device tree node. This allows finding an adapter based on the device node of the parent device that was used to register it. This fixes a regression on Tegra124-based Chromebooks (Nyan) where the eDP controller registers an I2C adapter that is used to read to EDID. After commit 993a815dcbb2 ("dt-bindings: panel: Add missing .txt suffix") this stopped working because the I2C adapter could no longer be found. The approach in this patch fixes the regression without introducing the issues that the above commit solved. Fixes: 17ab7806de0c ("drm: don't link DP aux i2c adapter to the hardware device node") Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Tristan Bastian <tristan-c.bastian@gmx.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-05i2c: omap: Use noirq system sleep pm ops to idle device for suspendTony Lindgren1-8/+5
We currently get the following error with pixcir_ts driver during a suspend resume cycle: omap_i2c 4802a000.i2c: controller timed out pixcir_ts 1-005c: pixcir_int_enable: can't read reg 0x34 : -110 pixcir_ts 1-005c: Failed to disable interrupt generation: -110 pixcir_ts 1-005c: Failed to stop dpm_run_callback(): pixcir_i2c_ts_resume+0x0/0x98 [pixcir_i2c_ts] returns -110 PM: Device 1-005c failed to resume: error -110 And at least am437x based devices with pixcir_ts will fail to resume to a touchscreen that is configured as the wakeup-source in device tree for these devices. This is because pixcir_ts tries to reconfigure it's registers for noirq suspend which fails. This also leaves i2c-omap in enabled state for suspend. Let's fix the pixcir_ts issue and make sure i2c-omap is suspended by adding SET_NOIRQ_SYSTEM_SLEEP_PM_OPS. Let's also get rid of some ifdefs while at it and replace them with __maybe_unused as SET_RUNTIME_PM_OPS and SET_NOIRQ_SYSTEM_SLEEP_PM_OPS already deal with the various PM Kconfig options. Reported-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Acked-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-02PCI: Move Rohm Vendor ID to generic listAndy Shevchenko1-1/+0
Move the Rohm Vendor ID to pci_ids.h instead of defining it in several drivers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-23i2c: aspeed: Remove hard-coded bus timeout value settingJae Hyun Yoo1-1/+0
This commit removes hard-coded bus timeout value setting so that it can be set by i2c-core-base. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: sh_mobile: update copyright and commentsWolfram Sang1-4/+3
Update copyright years and add Renesas to it. Add/update comments to make driver easier to understand. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: sh_mobile: refactor rx isrWolfram Sang1-29/+21
Remove the do_while loop which was just there to have an easy exit with "break;" and replace it with if-else-blocks which should make the state machine clearer. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: sh_mobile: replace break; with if-blockWolfram Sang1-4/+3
In preparation to remove the do-while-loop. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: sh_mobile: remove is_first_byte functionWolfram Sang1-7/+2
All state machines deal with pd->pos values. This helper function is an exception and makes it only more confusing. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: sh_mobile: drop 'data' argument from i2c_op functionWolfram Sang1-24/+17
It is clear that we always send the address in TX_FIRST and data in TX. No need to pass it from the caller. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: sh_mobile: remove get_data functionWolfram Sang1-15/+8
It makes the code much easier comprehensible to explicitly code that the first byte will be client address and all the following bytes are the actual data. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: sh_mobile: simplify sending address for RXWolfram Sang1-6/+2
pd->pos won't be smaller than -1, so we can simplify the logic. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: rcar: Fix clients using i2c from suspend callbackGeert Uytterhoeven1-1/+3
When doing s2idle/s2ram on Salvator-X(S): WARNING: CPU: 2 PID: 971 at drivers/i2c/i2c-core-base.c:1869 __i2c_transfer+0x608/0x910 [...] Call trace: __i2c_transfer+0x608/0x910 i2c_smbus_xfer_emulated+0x158/0x5b0 __i2c_smbus_xfer+0x17c/0x818 i2c_smbus_xfer+0x64/0x98 i2c_smbus_read_byte_data+0x40/0x70 cs2000_bset.isra.1+0x2c/0x68 __cs2000_set_rate.constprop.7+0x80/0x148 cs2000_resume+0x18/0x20 dpm_run_callback+0x74/0x330 device_resume_early+0xd4/0x120 dpm_resume_early+0x158/0x4f8 suspend_devices_and_enter+0x36c/0xd98 [...] On second resume, the sound driver fails with: cs2000-cp 2-004f: pll lock failed rcar_sound ec500000.sound: can't use clk 1 As the CS2000 clock driver needs to send I2C messages during suspend, the I2C controller driver should be suspended later, and resumed earlier. Fix this by using the noirq sleep ops instead of the normal sleep ops, which are called after the late sleep ops, as used by the CS2000 clock driver. Fixes: 18569fa89a4db9ed ("i2c: rcar: add suspend/resume support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-23i2c: imx: Fix inconsistent IS_ERR and PTR_ERR in i2c_imx_dma_request()YueHaibing1-1/+1
Change the call to PTR_ERR to access the value just tested by IS_ERR. Fixes: 5b3a23a3cc94 ("i2c: imx: notify about real errors on dma i2c_imx_dma_request") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Esben Haabendal <esben@haabendal.dk> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-16i2c: imx: improve the error handling in i2c_imx_dma_request()Oleksij Rempel1-6/+10
Improve the error handling in i2c_imx_dma_request() and let it return an error indication that the caller then can handle accordingly. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-16i2c: imx: notify about real errors on dma i2c_imx_dma_requestOleksij Rempel1-9/+12
At least on i.MX5x, the DMA events for I2C and SDHC use the same channel and there can only be a single user. So in this case there should be no message emitted that looks like an error if the I2C device doesn't have an assigned DMA channel. In contrast real problems that were only emitted at debug level before should be described at a higher level to be better visible and so understandable. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 13:07:11 +0300