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2025-09-15drm/amd/pm: unified smu feature cap interfaceYang Wang2-0/+41
add a unified interface to provide smu feature cap set. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amd/pm: Allow to set power cap in vf modeAsad Kamal2-4/+9
Allow setting power cap for smu_v13_0_6 in 1vf mode Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Add virtual device capabilitiesLijo Lazar1-0/+5
Add a member to define the capabilities of virtual device. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Add generic capability classLijo Lazar2-0/+92
Define a utility macro for defining capabilities and their attributes. Capability attributes are read-only, write-only, read-write. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Read memory vendor informationLijo Lazar1-0/+8
Read VRAM vendor information from scratch register for GC v9.4.3 and GC v9.5.0 SOCs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: wait pmfw polling mca bank info doneStanley.Yang1-0/+8
wait 500ms to ensure pmfw polling mca bank info done. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Use memset32 for ring clearingTvrtko Ursulin1-4/+1
Use memset32 instead of open coding it, just because it is a tiny bit nicer. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Fix allocating extra dwords for rings (v2)Timur Kristóf4-4/+16
Rename extra_dw to extra_bytes and document what it's for. The value is already used as if it were bytes in vcn_v4_0.c and in amdgpu_ring_init. Just adjust the dword count in jpeg_v1_0.c so that it becomes a byte count. v2: Rename extra_dw to extra_bytes as discussed during review. Fixes: c8c1a1d2ef04 ("drm/amdgpu: define and add extra dword for jpeg ring") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amd/pm: Remove unneeded legacy DPM related code.Timur Kristóf6-89/+0
This code isn't needed anymore as we collect the same information into pm_display_cfg instead. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amd/pm: Use pm_display_cfg in legacy DPM (v2)Timur Kristóf6-57/+97
This commit is necessary for DC to function well with chips that use the legacy power management code, ie. SI and KV. Communicate display information from DC to the legacy PM code. Currently DC uses pm_display_cfg to communicate power management requirements from the display code to the DPM code. However, the legacy (non-DC) code path used different fields and therefore could not take into account anything from DC. Change the legacy display code to fill the same pm_display_cfg struct as DC and use the same in the legacy DPM code. To ease review and reduce churn, this commit does not yet delete the now unneeded code, that is done in the next commit. v2: Rebase. Fix single_display in amdgpu_dpm_pick_power_state. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amd/display: Add pixel_clock to amd_pp_display_configurationTimur Kristóf4-2/+4
This commit adds the pixel_clock field to the display config struct so that power management (DPM) can use it. We currently don't have a proper bandwidth calculation on old GPUs with DCE 6-10 because dce_calcs only supports DCE 11+. So the power management (DPM) on these GPUs may need to make ad-hoc decisions for display based on the pixel clock. Also rename sym_clock to pixel_clock in dm_pp_single_disp_config to avoid confusion with other code where the sym_clock refers to the DisplayPort symbol clock. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Release hive reference properlyLijo Lazar2-4/+7
xgmi hive reference is taken on function entry, but not released correctly for all paths. Use __free() to release reference properly. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Ce Sun <cesun102@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu/ttm: Allocate/Free 4K MMIO_REMAP SingletonSrinivasan Shanmugam2-0/+60
Add mmio_remap bookkeeping to amdgpu_device and introduce amdgpu_ttm_mmio_remap_bo_init()/fini() to manage a kernel-owned, one-page (4K) BO in AMDGPU_GEM_DOMAIN_MMIO_REMAP. Bookkeeping: - adev->rmmio_remap.bo : kernel-owned singleton BO The BO is allocated during TTM init when a remap bus address is available (adev->rmmio_remap.bus_addr) and PAGE_SIZE <= AMDGPU_GPU_PAGE_SIZE (4K), and freed during TTM fini. v2: - Check mmio_remap bus address (adev->rmmio_remap.bus_addr) instead of rmmio_base. (Alex) - Skip quietly if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE or no bus address (no warn). (Alex) - Use `amdgpu_bo_create()` (not *_kernel) - Only with this The object is stored in adev->mmio_remap.bo and will later be exposed to userspace via a GEM handle. (Christian) v3: - Remove obvious comment before amdgpu_ttm_mmio_remap_bo_fini() call. (Alex) v4: - Squash bookkeeping into this patch (Christian) Suggested-by: Christian König <christian.koenig@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: validate userq buffer virtual address and sizePrike Liang3-0/+58
It needs to validate the userq object virtual address to determine whether it is residented in a valid vm mapping. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amd/pm: make smu_set_temp_funcs() smu specific for smu v13.0.6Yang Wang3-7/+7
move smu_set_temp_funcs() into smu_v13.0.6 ppt.c file to keep same code layer in amdgpu_smu.c. (only set_ppt func in amdgpu_smu.c) Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu/ttm: Initialize AMDGPU_PL_MMIO_REMAP HeapSrinivasan Shanmugam1-0/+9
Add a one-page TTM range manager for AMDGPU_PL_MMIO_REMAP via amdgpu_ttm_init_on_chip(). This only registers the placement with TTM; no BO is allocated in this patch. The singleton 4K remap BO is created and freed in the following patch. This split follows to separate heap bring-up from BO allocation. Cc: Christian König <christian.koenig@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Implement TTM handling for MMIO_REMAP placementSrinivasan Shanmugam1-3/+16
Implement TTM-level behavior for AMDGPU_PL_MMIO_REMAP so it behaves as a CPU-visible IO page: * amdgpu_evict_flags(): mark as unmovable * amdgpu_res_cpu_visible(): consider CPU-visible * amdgpu_bo_move(): use null move when src/dst is MMIO_REMAP * amdgpu_ttm_io_mem_reserve(): program base/is_iomem/caching using the device's mmio_remap_* metadata * amdgpu_ttm_io_mem_pfn(): return PFN for the remapped HDP page * amdgpu_ttm_tt_pde_flags(): set AMDGPU_PTE_SYSTEM for this mem type v2: - Drop HDP-specific comment; keep generic remap (Alex). v3: - Fix indentation in amdgpu_res_cpu_visible (Christian). - Use adev->rmmio_remap.bus_addr for MMIO_REMAP bus/PFN calculations (Alex). v4: - Drop unnecessary (resource_size_t) casts in MMIO_REMAP io-mem paths (Alex) Cc: Christian König <christian.koenig@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Replace kzalloc + copy_from_user with memdup_userThorsten Blum1-14/+6
Replace kzalloc() followed by copy_from_user() with memdup_user() to improve and simplify ta_if_load_debugfs_write() and ta_if_invoke_debugfs_write(). No functional changes intended. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdkfd: Replace kzalloc + copy_from_user with memdup_userThorsten Blum1-9/+3
Replace kzalloc() followed by copy_from_user() with memdup_user() to improve and simplify kfd_ioctl_set_cu_mask(). Return early if an error occurs and remove the obsolete 'out' label. No functional changes intended. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Use (v)memdup_array_user in amdgpu_cs_pass1Tvrtko Ursulin1-23/+10
Replace k(v)malloc_array() + copy_from_user() with (v)memdup_array_user(). This shrinks the source code and improves separation between the kernel and userspace slabs. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Use memdup_array_user in amdgpu_cs_wait_fences_ioctlTvrtko Ursulin1-14/+5
Replace kmalloc_array() + copy_from_user() with memdup_array_user(). This shrinks the source code and improves separation between the kernel and userspace slabs. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Use vmemdup_array_user in amdgpu_bo_create_list_entry_arrayTvrtko Ursulin1-24/+17
Replace kvmalloc_array() + copy_from_user() with vmemdup_array_user() on the fast path. This shrinks the source code and improves separation between the kernel and userspace slabs. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Remove volatile references from VCNRodrigo Siqueira10-51/+51
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Remove volatile from amdgpu and amdgpu_ih headersRodrigo Siqueira2-4/+4
Remove the unnecessary use of volatile in some of the amdgpu.h and amdgpu_ih.h headers. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Remove volatile from ring manipulationRodrigo Siqueira5-10/+10
None of the pointer operations handled by the ring file requires volatile, for this reason, this commit removes all occurrences of volatile associated with rings. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Remove volatile from RLC filesRodrigo Siqueira2-4/+4
The RLC uses volatile with some pointers that are not directly related to any of the situations where volatile is advised to be used [1]. For this reason, this commit removes all the volatile occurrences associated with RLC. 1. https://docs.kernel.org/process/volatile-considered-harmful.html Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm/amdgpu: Remove volatile from CSB functionsRodrigo Siqueira10-25/+18
The CSB buffer manipulation occurs in memory where the BO is mapped during initialization, and some references to this buffer are handled with volatile, which is incorrect in this scenario. There are a few cases where the use of volatile is accepted, but none of them align with CSB operations. Therefore, this commit removes all the volatile variables associated with the CSB code. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-09-15drm: bridge: anx7625: Fix NULL pointer dereference with early IRQLoic Poulain1-2/+4
If the interrupt occurs before resource initialization is complete, the interrupt handler/worker may access uninitialized data such as the I2C tcpc_client device, potentially leading to NULL pointer dereference. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Fixes: 8bdfc5dae4e3 ("drm/bridge: anx7625: Add anx7625 MIPI DSI/DPI to DP") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250709085438.56188-1-loic.poulain@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-09-15drm/vc4: hdmi: switch to generic CEC helpersDmitry Baryshkov3-84/+55
Switch VC4 driver to using CEC helpers code, simplifying hotplug and registration / cleanup. The existing vc4_hdmi_cec_release() is kept for now. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Maxime Ripard <mripard@kernel.org> Tested-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20250705-drm-hdmi-connector-cec-v7-1-d14fa0c31b74@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-09-15drm/nouveau: Support devfreq for TegraAaron Kling12-0/+389
Using pmu counters for usage stats. This enables dynamic frequency scaling on all of the currently supported Tegra gpus. The register offsets are valid for gk20a, gm20b, gp10b, and gv11b. If support is added for ga10b, this will need rearchitected. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> [fixed tab alignment in gk20a_devfreq_target()] Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://lore.kernel.org/r/20250906-gk20a-devfreq-v2-1-0217f53ee355@gmail.com
2025-09-15drm/nouveau: Support reclocking on gp10bAaron Kling5-0/+200
Starting with Tegra186, gpu clock handling is done by the bpmp and there is little to be done by the kernel. The only thing necessary for reclocking is to set the gpcclk to the desired rate and the bpmp handles the rest. The pstate list is based on the downstream driver generates. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> [added newline before gp10b_clk macro declaration for checkpatch error] Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://lore.kernel.org/r/20250823-gp10b-reclock-v2-1-90a1974a54e3@gmail.com
2025-09-15drm/xe: defer free of NVM auxiliary container to device release callbackNitin Gote1-1/+4
Do not kfree the intel_dg_nvm_dev in xe_nvm_fini() right after auxiliary_device_delete/uninit. The auxiliary_device embeds the device/kobject (and its name); freeing it too early can race with asynchronous device_del/udev processing and cause a use-after-free. Signed-off-by: Nitin Gote <nitin.r.gote@intel.com> Fixes: c28bfb107dac ("drm/xe/nvm: add on-die non-volatile memory device") Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20250911052823.226696-1-nitin.r.gote@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> (cherry picked from commit d4c3ed963e41d488695cf91068eabb8eb9f538ec) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-09-15drm/xe/hwmon: Remove type castingMallesh Koujalagi1-16/+19
Refactor: eliminate type casts by using proper u32 declarations. v2: - Address review comments. (Karthik) v3: - Use the proper u32 type and drop cast. (Lucas De Marchi) - Modify variable when actually using u64 value. - Change r value to reg_value with u32 type. v4: - Remove newline between trailer and Signed-off-by. (Lucas De Marchi) - Change reg_val to val for more user-friendly logging. - Use mul_u32_u32 function since both values are u32. v5: - mul_u32_u32 function with shift. (Lucas De Marchi) Fixes: 7596d839f6228 ("drm/xe/hwmon: Add support to manage power limits though mailbox") Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20250912113458.2815172-1-mallesh.koujalagi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> (cherry picked from commit 4e1d3b5e6423dc841acd8691d75626b3d3b2b6a8) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-09-15drm/xe/guc: Add test for G2G communicationsJohn Harrison8-0/+801
Add a test for sending messages from every GuC to every other GuC to test G2G communications. Note that, being a debug only feature, the test interface only exists in pre-production builds of the GuC firmware. v2: Fix 'default' case to actually use the driver's registration code as well as allocation. Add comments explaining the different test types. Fix (C) date and an assert. Review feedback from Daniele. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://lore.kernel.org/r/20250910210237.603576-5-John.C.Harrison@Intel.com
2025-09-15drm/xe: Allow freeing of a managed boJohn Harrison2-0/+6
If a bo is created via xe_managed_bo_create_pin_map() then it cannot be freed by the driver using xe_bo_unpin_map_no_vm(), or indeed any other existing function. The DRM layer will still have a pointer stashed away for later freeing, causing a invalid memory access on driver unload. So add a helper for releasing the DRM action as well. v2: Drop 'xe' parameter (review feedbak from Michal W) Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://lore.kernel.org/r/20250910210237.603576-4-John.C.Harrison@Intel.com
2025-09-15drm/xe/guc: Add firmware build type to available infoJohn Harrison2-0/+4
Some test features are not available in production builds of the GuC firmware. So add the build type field to the available information that tests can inspect to decide if they should skip or run. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://lore.kernel.org/r/20250910210237.603576-3-John.C.Harrison@Intel.com
2025-09-15drm/xe/guc: Update CSS header structuresJohn Harrison2-35/+53
Rework the CSS header structure according to recent updates to the GuC API spec. Also include more field definitions. v2: Also pass the new GuC specific structure to a GuC specific function instead of the higher level, generic structure (review feedback from Daniele). Also correct naming of CSS_TIME_* fields. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://lore.kernel.org/r/20250910210237.603576-2-John.C.Harrison@Intel.com
2025-09-15drm/xe: Use ERR_CAST instead of ERR_PTR(PTR_ERR(...))Fushuai Wang1-1/+1
Use ERR_CAST inline function instead of ERR_PTR(PTR_ERR(...)). Signed-off-by: Fushuai Wang <wangfushuai@baidu.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20250914101630.17719-1-wangfushuai@baidu.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-09-15drm/xe: Use ARRAY_SIZE in guc_waklv_init()Lucas De Marchi1-2/+2
Prefer using ARRAY_SIZE where needed and just passing 1 instead of calculating the size of one element. Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202508130158.eogeBZQT-lkp@intel.com/ Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://lore.kernel.org/r/20250912-guc-ads-array-size-v1-1-a6555392a1f8@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-09-15drm/panel-edp: Add several panel configurations for mt8189 ChromebookZhongtian Wu1-0/+6
Add several panel configurations for mt8189 Chromebook. For B140HAK03.3, the enable timing required 50ms. For NV156FHM-N4S, the enable timing required 200ms. For N140HCA-EAC, the enable timing required 80ms. For N156HCA-EAB, the enable timing required 80ms. For MNE001BS1-4, the enable timing required 80ms. For MNF601BS1-3, the enable timing required 80ms, the disable timing required 50ms. B140HAK03.3 edid-decode (hex): 00 ff ff ff ff ff ff 00 06 af a9 b7 00 00 00 00 28 20 01 04 95 1f 11 78 03 f5 65 8f 55 5a 93 2a 1f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 60 3b 80 04 71 38 52 40 10 10 3e 00 35 ae 10 00 00 18 95 27 80 04 71 38 52 40 10 10 3e 00 35 ae 10 00 00 18 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20 00 00 00 fe 00 42 31 34 30 48 41 4b 30 33 2e 33 20 0a 00 f1 NV156FHM-N4S edid-decode (hex): 00 ff ff ff ff ff ff 00 09 e5 f2 0c 00 00 00 00 10 22 01 04 a5 22 13 78 03 00 f5 97 5e 5b 93 29 1f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 99 3b 80 10 71 38 50 40 30 20 36 00 58 c2 10 00 00 1a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe 00 42 4f 45 20 43 51 0a 20 20 20 20 20 20 00 00 00 fe 00 4e 56 31 35 36 46 48 4d 2d 4e 34 53 0a 00 dc N140HCA-EAC edid-decode (hex): 00 ff ff ff ff ff ff 00 0d ae 8f 14 00 00 00 00 0f 22 01 04 a5 1f 11 78 03 28 65 97 59 54 8e 27 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 b4 3b 80 4a 71 38 34 40 50 3c 68 00 35 ad 10 00 00 18 c2 2f 80 4a 71 38 34 40 50 3c 68 00 35 ad 10 00 00 18 00 00 00 fd 00 28 3c 44 44 10 01 0a 20 20 20 20 20 20 00 00 00 fc 00 4e 31 34 30 48 43 41 2d 45 41 43 0a 20 01 90 02 03 22 00 e3 05 80 00 e6 06 01 01 53 53 4b 72 1a 00 00 03 01 28 3c 00 00 00 00 00 00 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 N156HCA-EAB edid-decode (hex): 00 ff ff ff ff ff ff 00 0d ae 65 15 00 00 00 00 0b 22 01 04 a5 22 13 78 03 28 65 97 59 54 8e 27 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 b4 3b 80 4a 71 38 34 40 50 36 68 00 58 c1 10 00 00 18 c2 2f 80 4a 71 38 34 40 50 36 68 00 58 c1 10 00 00 18 00 00 00 fd 00 28 3c 44 44 10 01 0a 20 20 20 20 20 20 00 00 00 fc 00 4e 31 35 36 48 43 41 2d 45 41 42 0a 20 01 50 02 03 22 00 e3 05 80 00 e6 06 01 01 53 53 42 72 1a 00 00 03 01 28 3c 00 00 00 00 00 00 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6b MNE001BS1-4 edid-decode (hex): 00 ff ff ff ff ff ff 00 0e 77 4b 14 00 00 00 00 25 22 01 04 a5 1f 11 78 03 2c c5 94 5c 59 95 29 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 9a 36 80 a0 70 38 28 40 30 20 36 00 35 ae 10 00 00 1a 00 00 00 fd 00 28 3c 43 43 0e 01 0a 20 20 20 20 20 20 ae 2b 80 a0 70 38 28 40 30 20 36 00 35 ae 10 00 00 1a 00 00 00 fc 00 4d 4e 45 30 30 31 42 53 31 2d 34 0a 20 01 0e 70 20 79 02 00 81 00 1e 72 1a 00 00 03 01 28 3c 00 00 53 ff 53 ff 3c 00 00 00 00 e3 05 04 00 e6 06 01 01 53 53 ff 2b 00 06 27 00 28 3b 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b8 90 MNF601BS1-3 edid-decode (hex): 00 ff ff ff ff ff ff 00 0e 77 19 15 00 00 00 00 19 22 01 04 a5 22 13 78 03 2c c5 94 5c 59 95 29 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 9a 36 80 a0 70 38 28 40 30 20 36 00 58 c1 10 00 00 1a ae 2b 80 a0 70 38 28 40 30 20 36 00 58 c1 10 00 00 1a 00 00 00 fd 00 28 3c 43 43 0e 01 0a 20 20 20 20 20 20 00 00 00 fc 00 4d 4e 46 36 30 31 42 53 31 2d 33 0a 20 01 d4 70 20 79 02 00 81 00 1e 72 1a 00 00 03 01 28 3c 00 00 53 ff 53 ff 3c 00 00 00 00 e3 05 04 00 e6 06 01 01 53 53 ff 2b 00 06 27 00 28 3b 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b8 90 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250915113437.665345-1-wuzhongtian@huaqin.corp-partner.google.com
2025-09-15drm/panel: Add support for KD116N3730A07Zhijian Yan1-0/+1
Add panel driver support for the KD116N3730A07 11.6" eDP panel. This includes initialization sequence and compatible string, the enable timimg required 50ms. KD116N3730A07: edid-decode (hex): 00 ff ff ff ff ff ff 00 2c 83 10 01 00 00 00 00 02 23 01 04 95 1a 0e 78 03 3a 75 9b 5d 5b 96 28 19 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 09 1e 56 dc 50 00 28 30 30 20 36 00 00 90 10 00 00 1a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe 00 4b 44 31 31 36 4e 33 37 33 30 41 30 37 00 2e Signed-off-by: Zhijian Yan <yanzhijian@huaqin.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250915064715.662312-1-yanzhijian@huaqin.corp-partner.google.com
2025-09-15drm/sun4i/sun4i_tcon_dclk: convert from round_rate() to determine_rate()Brian Masney1-8/+10
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/20250811-drm-clk-round-rate-v2-9-4a91ccf239cf@redhat.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-09-15drm/sun4i/sun4i_hdmi_ddc_clk: convert from round_rate() to determine_rate()Brian Masney1-5/+7
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/20250811-drm-clk-round-rate-v2-8-4a91ccf239cf@redhat.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-09-15drm/stm/lvds: convert from round_rate() to determine_rate()Brian Masney1-5/+7
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Acked-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Signed-off-by: Brian Masney <bmasney@redhat.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250811-drm-clk-round-rate-v2-7-4a91ccf239cf@redhat.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-09-15drm/stm/dw_mipi_dsi-stm: convert from round_rate() to determine_rate()Brian Masney1-6/+8
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Acked-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Signed-off-by: Brian Masney <bmasney@redhat.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250811-drm-clk-round-rate-v2-6-4a91ccf239cf@redhat.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-09-15drm/pl111: convert from round_rate() to determine_rate()Brian Masney1-5/+8
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/20250811-drm-clk-round-rate-v2-5-4a91ccf239cf@redhat.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-09-15drm/mcde/mcde_clk_div: convert from round_rate() to determine_rate()Brian Masney1-5/+8
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/20250811-drm-clk-round-rate-v2-2-4a91ccf239cf@redhat.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-09-15drm/imx/ipuv3/imx-tve: convert from round_rate() to determine_rate()Brian Masney1-7/+10
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20250811-drm-clk-round-rate-v2-1-4a91ccf239cf@redhat.com Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
2025-09-15drm/xe: Fix a NULL vs IS_ERR() in xe_vm_add_compute_exec_queue()Dan Carpenter1-2/+2
The xe_preempt_fence_create() function returns error pointers. It never returns NULL. Update the error checking to match. Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://lore.kernel.org/r/aJTMBdX97cof_009@stanley.mountain Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-09-15drm/xe/pf: Drop rounddown_pow_of_two fair LMEM limitationMichal Wajdeczko1-1/+0
This effectively reverts commit 4c3fe5eae46b ("drm/xe/pf: Limit fair VF LMEM provisioning") since we don't need it any more after non-contig VRAM allocations were fixed. This allows larger LMEM auto-provisioning for VFs, so instead: [ ] GT0: PF: LMEM available(14096M) fair(1 x 8192M) [ ] GT0: PF: VF1 provisioned with 8589934592 (8.00 GiB) LMEM or [ ] GT0: PF: LMEM available(14096M) fair(2 x 4096M) [ ] GT0: PF: VF1..VF2 provisioned with 4294967296 (4.00 GiB) LMEM we may get: [ ] GT0: PF: LMEM available(14096M) fair(1 x 14096M) [ ] GT0: PF: VF1 provisioned with 14780727296 (13.8 GiB) LMEM and [ ] GT0: PF: LMEM available(14096M) fair(2 x 7048M) [ ] GT0: PF: VF1..VF2 provisioned with 7390363648 (6.88 GiB) LMEM Fixes: 1e32ffbc9dc8 ("drm/xe/sriov: support non-contig VRAM provisioning") Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://lore.kernel.org/r/20250910222439.32869-1-michal.wajdeczko@intel.com (cherry picked from commit 95c1cfa306087142989bff34ea0e05dcd95ddc58) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-06-08 03:34:23 +0300