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2025-11-19drm/i915/dram: Fix ICL DIMM_S decodingVille Syrjälä2-64/+155
Unfortunately the MAD_DIMM DIMM_S and DIMM_L bits on ICL are not idential, so we are currently decoding DIMM_S incorrectly. Fix the problem by defining the DIMM_S and DIMM_L bits separately. And for consistency do that same for SKL, even though there the bits do match between the two DIMMs. The result is rather repetitive in places, but I didn't feel like obfuscatign things with cpp macros/etc. Broken decoding on Dell XPS 13 7390 2-in-1: CH0 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 DIMM S size: 32 Gb, width: X32, ranks: 3, 16Gb+ DIMMs: no CH0 ranks: 2, 16Gb+ DIMMs: no CH1 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 DIMM S size: 32 Gb, width: X32, ranks: 3, 16Gb+ DIMMs: no CH1 ranks: 2, 16Gb+ DIMMs: no Memory configuration is symmetric? no Fixed decoding on Dell XPS 13 7390 2-in-1: CH0 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 DIMM S size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 ranks: 2, 16Gb+ DIMMs: no CH1 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 DIMM S size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 ranks: 2, 16Gb+ DIMMs: no Memory configuration is symmetric? yes Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029204215.12292-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915/dram: Sort SKL+ DIMM register bitsVille Syrjälä1-9/+9
Use the customary big endian order when defining the SKL/ICL DIMM registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029204215.12292-3-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-11-19drm/i915/dram: Use REG_GENMASK() & co. for the SKL+ DIMM regsVille Syrjälä2-34/+29
Modernize the SKL/ICL DIMM registers with REG_GENMASK() & co. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029204215.12292-2-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-11-19drm/panel: sofef00: Non-continuous mode and video burst are supportedDavid Heidelberg1-1/+2
The panel supports both modes. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-12-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Mark the LPM mode always-onDavid Heidelberg1-2/+5
The panel operated in low-power mode, with exception of changing the brightness levels. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-11-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Simplify get_modesDavid Heidelberg1-14/+7
Levearage drm_connector_helper_get_modes_fixed helper function. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-10-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Introduce compatible which includes the panel nameDavid Heidelberg1-3/+4
Compatible should correspond to the panel used and the driver currently supports only AMS628NW01 panel. Adapt the internal driver structures to reflect the name. Original, not very descriptive, compatible is kept to ensure compatibility with older device-trees. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-9-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Initialise at 50% brightnessCasey Connolly1-1/+1
Initialising at max brightness is not necessary. Half brightness is much more comfortable. Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-8-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Add prepare_prev_first flag to drm_panelCasey Connolly1-0/+2
This corrects the host initialisation sequence so that we can send DSI/DCS commands in prepare(). Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-7-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Introduce page macroDavid Heidelberg1-5/+10
Introducing the macro make the code a bit clearer. Looking at other Samsung drivers, I assume it's lvl2, thou due to not available documentation it's only educated guess. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-6-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Split sending commands to the enable/disable functionsDavid Heidelberg1-1/+19
It's not possible to send DSI panel commands in the .unprepare. Move it to .disable and do similar for prepare, where we move the display on to the .enable. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-5-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Handle all regulatorsDavid Heidelberg1-11/+17
Recently we documented, there is more than vddio regulator, adapt the driver to work with VCI and POC regulator. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-4-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Clean up panel description after s6e3fc2x01 removalDavid Heidelberg2-5/+6
Remove leftover from s6e3fc2x01 support drop and clarify supported panel. The Samsung SOFEF00 DDIC is used in multiple phones, so describe it properly and generalize. Fixes: e1eb7293ab41 ("drm/panel: samsung-sofef00: Drop s6e3fc2x01 support") Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-3-6cd55471e84e@ixit.cz
2025-11-19drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panelChaoyi Chen1-0/+225
W552946AAA is a panel by Wanchanglong. This panel utilizes the Ilitek ILI9881D controller. W552946AAA is similar to W552946ABA, but the W552946AAA only uses 2 lanes. Tested on rk3506g-evb1-v10. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251106020632.92-6-kernel@airkyi.com
2025-11-19drm/panel: ronbo-rb070d30: fix warning with gpio controllers that sleepJosua Mayer1-4/+4
The ronbo-rb070d30 controles the various gpios for reset, standby, vertical and horizontal flip using the non-sleeping gpiod_set_value() function. Switch to using gpiod_set_value_cansleep() when controlling reset_gpio to support GPIO providers that may sleep, such as I2C GPIO expanders. This fixes noisy complaints in kernel log for gpio providers that do sleep. Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251117-imx8mp-hb-iiot-v3-5-bf1a4cf5fa8e@solid-run.com
2025-11-19drm/panel: jadard-jd9365da-h3: Use dev_err_probe() instead of ↵Abhishek Rajput1-12/+9
DRM_DEV_ERROR() during probing The DRM_DEV_ERROR() has been deprecated, and use dev_err_probe() can be better. The other reason is that dev_err_probe() help avoid unexpected repeated err logs during defered probing. Signed-off-by: Abhishek Rajput <abhiraj21put@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251117064702.222424-1-abhiraj21put@gmail.com
2025-11-19drm/panel: simple: Add Raystar RFF500F-AWH-DNN panel entryFabio Estevam1-0/+27
Add support for the Raystar RFF500F-AWH-DNN 5.0" TFT 840x480 LVDS panel. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251115025827.3113790-3-festevam@gmail.com
2025-11-19gpu/drm: panel: simple-panel: add Samsung LTL106AL01 LVDS panel supportSvyatoslav Ryhel1-0/+34
Samsung LTL106AL01 is a 10.6" FWXGA (1366x768) simple LVDS panel found in Microsoft Surface RT tablet. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251110091440.5251-6-clamor95@gmail.com
2025-11-19gpu/drm: panel: add support for LG LD070WX3-SL01 MIPI DSI panelSvyatoslav Ryhel4-31/+198
The LD070WX3 is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally Black mode. This TFT-LCD has 7.0 inches diagonally measured active display area with WXGA resolution (800 by 1280 pixel array). LG LD070WX3-SL01 MIPI DSI panel was treated as simple DSI panel when it is actually not and requires proper setup for correct work. Simple panel work relied on preliminary configuration done by bootloader. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251110091440.5251-3-clamor95@gmail.com
2025-11-19drm/xe/vm: Use for_each_tlb_inval() to calculate invalidation fencesMatt Roper1-8/+7
ops_execute() calculates the size of a fence array based on XE_MAX_GT_PER_TILE, while the code that actually fills in the fence array uses a for_each_tlb_inval() iterator. This works out okay today since both approaches come up with the same number of invalidation fences (2: primary GT invalidation + media GT invalidation), but could be problematic in the future if there isn't a 1:1 relationship between TLBs needing invalidation and potential GTs on the tile. Adjust the allocation code to use the same for_each_tlb_inval() counting logic as the code that fills the array to future-proof the code. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20251118202604.3715782-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-11-19Merge drm/drm-fixes into drm-misc-fixesThomas Zimmermann47-111/+274
Backmerging to get fixes from v6.18-rc6. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2025-11-19drm/i915/cx0: Enable dpll framework for MTL+Mika Kahola5-86/+6
MTL+ platforms are supported by dpll framework remove a separate check for hw comparison and rely solely on dpll framework hw comparison. Finally, all required hooks are now in place so initialize PLL manager for MTL+ platforms and remove the redirections to the legacy code paths from the following interfaces: * intel_encoder::clock_enable/disable() * intel_encoder::get_config() * intel_dpll_funcs::get_hw_state() * intel_ddi_update_active_dpll() * pipe_config_pll_mismatch() v2: Rebase on !HAS_LT_PHY check in intel_ddi_update_active_dpll() v3: Rebase on !display->dpll.mgr check in intel_ddi_update_active_dpll() Add check for NVL as the platform is not part of pll framework (Suraj) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251118132859.2584452-1-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ Thunderbolt PLL hooksImre Deak3-2/+59
Add the PLL hooks for the TBT PLL on MTL+. These are simple stubs similarly to the TBT PLL on earlier platforms, since this PLL is always on from the display POV - so no PLL enable/disable programming is required as opposed to the non-TBT PLLs - and the clocks for different link rates are enabled/disabled at a different level, via the intel_encoder::enable_clock()/disable_clock() interface. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-32-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLsMika Kahola1-6/+75
For DDI initialization get encoder configuration for C10 and C20 chips. v2: Get configuration either for a C10 or on the PTL port B eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this case as "non_tc_phy" instead of "c10phy". Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-31-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDIMika Kahola5-16/+64
To enable pll clock on DDI move part of the pll enabling sequence into a ddi clock enabling function. Simililarly, do the same for pll disabling sequence. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-30-mika.kahola@intel.com
2025-11-19drm/i915/cx0: PLL verify debug state printImre Deak1-5/+12
Print out hw and sw pll states for better debugging support. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-29-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .crtc_get_dpll hookMika Kahola1-0/+1
Add .crtc_get_dpll function pointer to support MTL+ platforms. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-28-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .get_freq hookMika Kahola1-0/+13
Add .get_freq hook to support dpll framework for MTL+ platforms. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-27-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .get_hw_state hookMika Kahola3-3/+37
Add .get_hw_state hook to MTL+ platforms for dpll framework. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-26-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add .compare_hw_state hookMika Kahola1-0/+10
Add .compare_hw_state function pointer for MTL+ platforms to support dpll framework. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-25-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .dump_hw_state hookMika Kahola4-40/+45
Add .dump_hw_state function pointer for MTL+ platforms to support dpll framework. While at it, switch to use drm_printer structure to print hw state information. v2: Keep debug messages on one line if they not necessarily needed to split into two or more lines (Suraj) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-24-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hookMika Kahola1-0/+1
Add .update_dpll_ref_clks function pointer to MTL+ platforms to support dpll framework. Reuse ICL function pointer. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-23-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .update_active_dpll hookMika Kahola2-2/+3
Add .update_active_dpll function pointer to support dpll framework. Reuse ICL function pointer. v2: Add check for !HAS_LT_PHY (Suraj) v3: Remove the incorrect !HAS_LT_PHY condition and check for existing dpll_mgr Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1 Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251118132830.2584422-1-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .put_dplls hookMika Kahola1-0/+1
Add .put_dplls function pointer to support MTL+ platforms on dpll framework. Reuse ICL function pointer. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-21-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .get_dplls hookMika Kahola2-0/+58
Add .get_dplls function pointer for MTL+ platforms to support dpll framework. Reuse the ICL function pointer. v2: Getting configuration either for a C10 or on the PTL port B eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this case as "non_tc_phy" instead of "c10phy". v3: Fix comment to "eDP over TypeC" (Suraj) Fix pll id as separate variable (Suraj) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-20-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola1-0/+69
To bring MTL+ platform aligned call and calculate PLL state from dpll framework. v2: Rename mtl_compute_c10phy_dpll() to mtl_compute_non_tc_phy_dpll(). The state is computed either for a C10 or on the PTL port B eDP over TypeC PHY case for a C20 PHY PLL. Hence refer to this case as "non_tc_phy" instead of "c10phy". Rename mtl_compute_c20phy_dplls() to mtl_compute_tc_phy_dplls() for symmetry with mtl_compute_non_tc_phy_dpll(). v3: Reword commit message (Suraj) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-19-mika.kahola@intel.com
2025-11-19drm/xe: Switch to use %ptSpAndy Shevchenko1-2/+2
Use %ptSp instead of open coded variants to print content of struct timespec64 in human readable format. Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113150217.3030010-9-andriy.shevchenko@linux.intel.com Signed-off-by: Petr Mladek <pmladek@suse.com>
2025-11-19drm/vblank: Switch to use %ptSpAndy Shevchenko1-4/+2
Use %ptSp instead of open coded variants to print content of struct timespec64 in human readable format. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113150217.3030010-8-andriy.shevchenko@linux.intel.com Reviewed-by: Petr Mladek <pmladek@suse.com> Signed-off-by: Petr Mladek <pmladek@suse.com>
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola3-35/+40
Update several functions in intel_cx0_phy.c to make PLL state management more explicit. Changes include * add 'const' qualifiers to intel_crtc_state parameter for cx0 state calculation functions * refactor C10/C20 PLL state calculations helpers to take explicit hardware state pointers instead of directly modifying 'crtc_state->dpll_hw_state' Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-18-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add PLL information for MTL+Mika Kahola1-0/+19
Start bringing MTL+ platforms as part of PLL framework. The work is started by adding PLL information and related function hooks. BSpec: 55726 v2: Revise commit message and add BSpec ID (Suraj) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-17-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola3-117/+0
When pll's are moved to dpll framework we no longer need Cx0 specific state verification as we can rely on dpll state verification instead. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-16-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak1-3/+15
Print all the Cx0 PLL state in the PLL state dumper. v2: Use BUILD_BUG_ON() instead of WARN_ON() (Jani) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-15-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak1-1/+3
Ensure Cx0 pll state is initialized to zero before any computation or HW readouts, to prevent leaving some parameter in the state uninitialized in the actual compute/HW readout functions later. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-14-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak1-12/+5
The port clock is tracked in the PLL state, so there is no need to pass it separately to __intel_cx0pll_enable(). Drop the port clock function param accordingly. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-13-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak1-7/+36
The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI mode. The PLL manager framework doesn't pass the CRTC state to the PLL's enable hook, so prepare here for the conversion to use the PLL manager for Cx0 PHY PLLs by determining the DP/HDMI mode from the PLL state. For C10 PHYs use the fact that the HDMI divider value in the PLL registers are set if and only if the PLL is in HDMI mode. For C20 PHYs use the DP mode flag programmed to the VDR SERDES register, which is set if and only if the PLL is in DP mode. Assert that the above PLL/VDR SERDES register values match the DP/HDMI mode being configured already during state computation. This also allows dropping the is_dp param from the __intel_cx0pll_enable() function, since it can retrieve this now from the PLL state. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-12-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak1-0/+25
Read out the C10, C20 PHY PLLs SSC enabled state, so the PLL HW/SW state verification can check this state as well. C10 PHY PLLs program some PLL registers zeroed out for the non-SSC case, while programming non-zero values to the same registers for the SSC case, so check that these PLL registers being zero or non-zero matches the PLL's overall SSC-enabled state (stored in the intel_c10pll_state::ssc_enabled flag). Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-11-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak1-2/+8
Define the C10 PLL SSC register range via macros, so the HW/SW state of these register can be verified by a follow-up change, reusing these macros. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-10-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak2-7/+49
The Cx0 PLL enable programming requires the enabled lane count. The PLL manager framework doesn't pass the CRTC state to the PLL's enable hook, so prepare here for the conversion to use the PLL manager, by tracking the enabled lane count in the PLL state as well. This has the advantage, that the enabled lane count can be verified against the PHY/PLL's enabled TX lanes. This also allows dropping the lane count param from the __intel_cx0pll_enable() function, since it can retrieve this now from the PLL state. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-9-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak1-1/+6
A follow-up change will need to retrieve the DDI port field from the register value, add a macro for this. Make things symmetric with setting the field in the register. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-8-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak1-105/+98
Move the definitions of the intel_c10pll_calc_port_clock() intel_c20_get_dp_rate() intel_c20_get_hdmi_rate() is_hdmi_frl() is_dp2() intel_get_c20_custom_width() functions earlier to avoid the forward declarations. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-7-mika.kahola@intel.com
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