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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2026-03-24drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-PTvrtko Ursulin1-0/+8
2026-03-24drm/xe/display: Add support for AuxCCSTvrtko Ursulin1-1/+27
2026-03-24drm/xe/display: Respect remapped plane alignmentTvrtko Ursulin1-3/+12
2026-03-24drm/xe/display: Change write_dpt_remapped_tiled function signatureTvrtko Ursulin1-25/+35
2026-03-24drm/xe/display: Move remapped plane loop out of __xe_pin_fb_vma_dptTvrtko Ursulin1-14/+20
2026-03-24drm/xe/xelp: Add AuxCCS invalidation to the indirect context workaroundsTvrtko Ursulin1-0/+23
2026-03-24drm/xe: Move aux table invalidation to ring opsTvrtko Ursulin2-28/+83
2026-03-24drm/xe/xelp: Wait for AuxCCS invalidation to completeTvrtko Ursulin3-2/+15
2026-03-24drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCSTvrtko Ursulin1-1/+9
2026-03-24drm/xe/xelpg: Limit AuxCCS ring buffer programming to AlderlakeTvrtko Ursulin1-2/+2
2026-03-24drm/xe: Implement recent spec updates to Wa_16025250150Matt Roper2-1/+3
2026-03-24drm/xe: Use write-combine mapping when populating DPTTvrtko Ursulin1-1/+2
2026-03-24drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WCTvrtko Ursulin7-19/+26
2026-03-24drm/display: hdmi: Use drm_output_color_format instead of hdmi_colorspaceMaxime Ripard13-179/+202
2026-03-24drm/rockchip: analogix: Convert to drm_output_color_formatMaxime Ripard1-2/+2
2026-03-24drm/mediatek: dp: Convert to drm_output_color_formatMaxime Ripard1-2/+2
2026-03-24drm/arm: komeda: Convert to drm_output_color_formatMaxime Ripard4-11/+12
2026-03-24drm/bridge: synopsys: dw-hdmi: Convert to drm_output_color_formatMaxime Ripard1-8/+8
2026-03-24drm/bridge: synopsys: dw-dp: Convert to drm_output_color_formatMaxime Ripard1-35/+36
2026-03-24drm/bridge: cadence: Convert to drm_output_color_formatMaxime Ripard2-13/+13
2026-03-24drm/bridge: analogix: Convert to drm_output_color_formatMaxime Ripard1-2/+2
2026-03-24drm/bridge: adv7511: Convert to drm_output_color_formatMaxime Ripard1-1/+1
2026-03-24drm/amdgpu: display: Convert to drm_output_color_formatMaxime Ripard1-2/+2
2026-03-24drm/display: hdmi: Convert to drm_output_color_formatMaxime Ripard1-4/+4
2026-03-24drm/edid: Convert to drm_output_color_format enumMaxime Ripard1-9/+9
2026-03-24drm/xe/pf: Add FLR_PREPARE state to VF control flowPiotr Piórkowski6-16/+91
2026-03-24drm/imagination: Implement handling of context reset notificationAlexandru Dadu4-0/+136
2026-03-24drm/imagination: Switch reset_reason fields from enum to u32Alexandru Dadu2-3/+11
2026-03-24drm/imagination: Add missing rogue context reset reasonsAlexandru Dadu1-0/+12
2026-03-24drm/i915/lt_phy: Replace crtc compute clockMika Kahola1-24/+1
2026-03-24drm/i915/lt_phy: Enable dpll framework for xe3plpdMika Kahola4-35/+6
2026-03-24drm/i915/lt_phy: Remove LT PHY specific state verificationMika Kahola4-45/+13
2026-03-24drm/i915/lt_phy: Add xe3plpd Thunderbolt PLL hooksMika Kahola3-2/+33
2026-03-24drm/i915/lt_phy: Get encoder configuration for xe3plpd platformMika Kahola1-16/+4
2026-03-24drm/i915/lt_phy: Readout lane countMika Kahola3-4/+9
2026-03-24drm/i915/lt_phy: Dump lane count for HW stateMika Kahola1-2/+2
2026-03-24drm/i915/lt_phy: Add .disable_clock hook on DDIMika Kahola2-1/+13
2026-03-24drm/i915/lt_phy: Add .enable_clock hook on DDIMika Kahola4-21/+34
2026-03-24drm/i915/lt_phy: Add xe3plpd .crtc_get_dpllMika Kahola1-0/+1
2026-03-24drm/i915/lt_phy: Add xe3plpd .get_freq hookMika Kahola1-0/+13
2026-03-24drm/i915/lt_phy: Add xe3plpd .get_hw_state hookMika Kahola4-8/+21
2026-03-24drm/i915/lt_phy: Add xe3plpd .compare_hw_state hookMika Kahola1-0/+10
2026-03-24drm/i915/lt_phy: Add xe3plpd .dump_hw_state hookMika Kahola4-12/+19
2026-03-24drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hookMika Kahola1-0/+1
2026-03-24drm/i915/lt_phy: Add xe3plpd .update_active_dpll hookMika Kahola1-0/+1
2026-03-24drm/i915/lt_phy: Add xe3plpd .put_dplls hookMika Kahola1-0/+1
2026-03-24drm/i915/lt_phy: Add xe3plpd .get_dplls hookMika Kahola1-0/+1
2026-03-24drm/i915/lt_phy: Add xe3plpd .compute_dplls hookMika Kahola4-9/+78
2026-03-24drm/i915/lt_phy: Add lane_count to PLL stateMika Kahola2-4/+6
2026-03-24drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL stateMika Kahola1-21/+46
generated by cgit v1.2.3 (git 2.39.0) at 2026-06-17 19:54:05 +0300