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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2017-05-17drm/i915: Remove kref from i915_sw_fenceChris Wilson2-45/+11
2017-05-17drm/i915/gen9: Reintroduce WaEnableYV12BugFixInHalfSliceChicken7Arkadiusz Hiler1-0/+2
2017-05-16drm/i915: use vma->size for appgtt allocate_va_rangeMatthew Auld1-1/+1
2017-05-16gpu: drm: i915: compress logic into one lineGustavo A. R. Silva1-3/+1
2017-05-16gpu: drm: i915: remove dead codeGustavo A. R. Silva1-8/+1
2017-05-16drm/i915/guc:fix spelling mistake: "adddress" -> "address"Colin Ian King1-1/+1
2017-05-15drm/i915/glk: Calculate high/low switch count for GLKMadhav Chauhan1-4/+4
2017-05-15drm/i915: Fixup 64bit divides in timelines selftestChris Wilson1-6/+4
2017-05-15drm/i915: Update DRIVER_DATE to 20170515Daniel Vetter1-2/+2
2017-05-13drm/i915/perf: rate limit spurious oa report noticeRobert Bragg2-1/+33
2017-05-13drm/i915/perf: better pipeline aged/aging tail updatesRobert Bragg1-18/+23
2017-05-13drm/i915/perf: improve invalid OA format debug messageRobert Bragg1-2/+4
2017-05-13drm/i915/perf: improve tail race workaroundRobert Bragg2-96/+241
2017-05-13drm/i915/perf: no head/tail ref in gen7_oa_readRobert Bragg1-32/+18
2017-05-13drm/i915/perf: avoid read back of head registerRobert Bragg2-25/+32
2017-05-13drm/i915/perf: avoid poll, read, EAGAIN busy loopsRobert Bragg1-1/+9
2017-05-13drm/i915/perf: fix gen7_append_oa_reports commentRobert Bragg1-1/+1
2017-05-12drm/i915: Restore brightness level in aux backlight driverPuthikorn Voravootivat1-0/+1
2017-05-12drm/i915: Set backlight mode before enable backlightPuthikorn Voravootivat1-2/+2
2017-05-12drm/i915: Correctly enable backlight brightness adjustment via DPCDPuthikorn Voravootivat1-6/+27
2017-05-12drm/i915: Fix cap check for intel_dp_aux_backlight driverPuthikorn Voravootivat1-0/+1
2017-05-12drm/i915: don't do allocate_va_range again on PIN_UPDATEMatthew Auld1-4/+8
2017-05-12drm/i915: set initialised only when init_context callback is NULLChuanxiao Dong1-1/+1
2017-05-11drm/i915: Do not sync RCU during shrinkingJoonas Lahtinen1-5/+0
2017-05-11drm/i915/guc: Make scratch register base and count flexibleMichal Wajdeczko2-7/+41
2017-05-11drm/i915/guc: Move notification code into virtual functionMichal Wajdeczko2-1/+18
2017-05-11drm/i915: Remove vma unpin in intel_plane_destroyMaarten Lankhorst1-17/+1
2017-05-11drm/i915: Fix hw state verifier access to crtc->state.Maarten Lankhorst1-10/+14
2017-05-11drm/i915/guc: Dump the GuC stage descriptor pool in debugfsOscar Mateo1-5/+71
2017-05-10drm/i915: Fix __intel_wait_for_register_fw to not sleep in atomicDaniel Vetter1-2/+2
2017-05-10drm/i915: Simplify cursor register write sequenceVille Syrjälä1-35/+34
2017-05-10drm/i915: Relax 845/865 CURBASE alignemnt requirement to 32 bytesVille Syrjälä1-0/+2
2017-05-10drm/i915: Handle fb offset and src coordinates for cursorsVille Syrjälä1-2/+25
2017-05-10drm/i915: Fix gen3 physical cursor alignment requirementsVille Syrjälä1-2/+12
2017-05-10drm/i915: Support variable cursor height on ivb+Ville Syrjälä3-8/+36
2017-05-10drm/i915: Use fb->pitches[0] in cursor codeVille Syrjälä1-30/+18
2017-05-10drm/i915: Generalize cursor size checks a bitVille Syrjälä1-21/+13
2017-05-10drm/i915: Split cursor check_plane into i845 and i9xx variantsVille Syrjälä1-104/+171
2017-05-10drm/i915: Drop useless posting reads from cursor commitVille Syrjälä1-17/+15
2017-05-10drm/i915: Move cursor position and base handling into the platform specific f...Ville Syrjälä1-46/+49
2017-05-10drm/i915: Refactor CURPOS calculationVille Syrjälä1-15/+22
2017-05-10drm/i915: Clean up cursor junk from intel_crtcVille Syrjälä3-89/+47
2017-05-10drm/i915: Refactor CURBASE calculationVille Syrjälä1-20/+29
2017-05-10drm/i915: Pass intel_plane and intel_crtc to plane hooksVille Syrjälä4-129/+104
2017-05-10drm/i915: Parametrize cursor/primary pipe select bitsVille Syrjälä2-11/+5
2017-05-10drm/i915: Add support for sprites on g4xVille Syrjälä3-12/+12
2017-05-10drm/i915: Add g4x watermark tracepointVille Syrjälä2-0/+54
2017-05-10drm/i915: Enable HPLL watermarks on g4xVille Syrjälä1-1/+2
2017-05-10drm/i915: Two stage watermarks for g4xVille Syrjälä5-226/+791
2017-05-10drm/i915: Apply the g4x TLB miss w/a to SR watermarks as wellVille Syrjälä1-6/+9
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