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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2015-09-04drm/i915: ignore link rate in TPS3 selectionJani Nikula1-3/+4
2015-09-04drm/i915/dp: move TPS3 logic to where it's usedJani Nikula2-15/+17
2015-09-04drm/i915: Future proof panel fitter.Rodrigo Vivi1-12/+6
2015-09-04drm/i915: Future proof uncore_init.Rodrigo Vivi1-2/+0
2015-09-04drm/i915: Future proof interrupt handler.Rodrigo Vivi1-4/+4
2015-09-04drm/i915/gtt: Avoid calling kcalloc in a loop when allocating temp bitmapsMichał Winiarski1-31/+18
2015-09-04drm/i915/skl+: Add YUV pixel format in Capability listKumar, Mahesh1-0/+4
2015-09-04drm/i915/skl: Avoid using un-initialized bits_per_pixelKumar, Mahesh1-1/+2
2015-09-02drm/i915: Don't call intel_get_hpd_pins() when there's no hotplug interruptVille Syrjälä1-8/+14
2015-09-02drm/i915: Rewrite BXT HPD code to conform to pre-existing styleVille Syrjälä2-38/+13
2015-09-02drm/i915: Refactor the hpd irq handling functionsVille Syrjälä1-63/+49
2015-09-02drm/i915: Rewrite bxt_hpd_handler() to look like everyone elseVille Syrjälä1-21/+16
2015-09-02drm/i915: Reinitialize HPD after runtime D3Ville Syrjälä1-0/+9
2015-09-02drm/i915: Add port A HPD support for SPTVille Syrjälä2-3/+22
2015-09-02drm/i915: Add port A HPD support for BDWVille Syrjälä1-12/+74
2015-09-02drm/i915: LPT:LP needs port A HPD enabled in both north and southVille Syrjälä1-0/+6
2015-09-02drm/i915: Add port A HPD support for IVB/HSWVille Syrjälä1-7/+28
2015-09-02drm/i915: Add port A HPD support for ILK/SNBVille Syrjälä1-3/+56
2015-09-02drm/i915: Introduce spt_irq_handler()Ville Syrjälä1-40/+84
2015-09-02drm/i915: Move {pin, long}_mask initialization to caller from intel_get_hpd_p...Ville Syrjälä1-8/+11
2015-09-02drm/i915: Rename BXT PORTA HPD definesVille Syrjälä2-6/+6
2015-09-02drm/i915: Add HAS_PCH_LPT_LP() macroVille Syrjälä3-10/+8
2015-09-02drm/i915: Factor out ilk_update_display_irq()Ville Syrjälä1-15/+26
2015-09-02drm/i915: Extract intel_hpd_enabled_irqs()Ville Syrjälä1-22/+21
2015-09-02drm/i915: Clean up various HPD definesVille Syrjälä1-36/+38
2015-09-02drm/i915: Update comments around base bppDaniel Vetter1-5/+1
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter363-14699/+45765
2015-09-02drm/i915: Also record time difference if vblank evasion fails, v2.Maarten Lankhorst2-2/+7
2015-09-02drm/i915: Remove start frame argument to pipe_update_begin/end.Maarten Lankhorst3-15/+14
2015-09-02drm/i915: guest i915 notification for Intel GVT-gZhiyuan Lv1-0/+41
2015-09-02drm/i915: Update PV INFO page definition for Intel GVT-gZhiyuan Lv1-2/+32
2015-09-02drm/i915: Always enable execlists on BDW for vgpuZhiyuan Lv2-0/+13
2015-09-02drm/i915: preallocate pdps for 32 bit vgpuZhiyuan Lv2-1/+35
2015-09-02drm/i915: add yesno utility functionJani Nikula3-10/+5
2015-09-02drm/i915: move intel_hrawclk() to intel_display.cJani Nikula3-34/+34
2015-09-02drm/i915: Notify GuC rc6 stateAlex Dai1-0/+15
2015-09-02drm/i915/guc: Support GuC version 4.3Alex Dai2-14/+14
2015-09-02drm/i915: Fix module initialisation, v2.Maarten Lankhorst3-18/+7
2015-09-01drm/i915: Factor out intel_crtc_has_encoders()Ville Syrjälä1-9/+13
2015-09-01drm/i915: Fix clock readout when pipes are enabled w/o portsVille Syrjälä1-0/+8
2015-09-01drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä2-17/+111
2015-09-01drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä2-0/+62
2015-09-01drm/i915: Clean up CHV lane soft reset programmingVille Syrjälä2-82/+100
2015-09-01i915: Set ddi_pll_sel in DP MST pathAnder Conselvan de Oliveira3-1/+7
2015-09-01drm/i915: Bump command parser version number.Francisco Jerez1-1/+2
2015-09-01drm/i915/dp: use the drm dp helper for determining sink tps3 supportJani Nikula1-2/+1
2015-09-01drm/i915: Don't use link_bw for PLL setupVille Syrjälä2-29/+26
2015-09-01drm/i915: Preserve SSC earlierLukas Wunner1-11/+18
2015-08-31drm/i915/skl: Adding DDI_E power well domainXiong Zhang4-1/+7
2015-08-31drm/i915: eDP can be present on DDI-ERodrigo Vivi2-9/+5
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