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2017-07-26drm: Convert to using %pOF instead of full_nameRob Herring1-2/+2
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Russell King <linux@armlinux.org.uk> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Inki Dae <inki.dae@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Cc: Seung-Woo Kim <sw0312.kim@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Xinliang Liu <z.liuxinliang@hisilicon.com> Cc: Rongrong Zou <zourongrong@gmail.com> Cc: Xinwei Kong <kong.kongxinwei@hisilicon.com> Cc: Chen Feng <puck.chen@hisilicon.com> Cc: CK Hu <ck.hu@mediatek.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Mark Yao <mark.yao@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jyri Sarha <jsarha@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Partially-Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [seanpaul changed subject prefix and fixed conflict in stm/ltdc.c] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-06-16BackMerge tag 'v4.12-rc5' into drm-nextDave Airlie2-15/+13
Linux 4.12-rc5 for nouveau fixes
2017-06-08gpu: ipu-v3: vdic: include AUTO field order bit in ipu_vdi_set_field_orderSteve Longerbeam1-2/+2
The field order selection in VDIC_C register uses different bits depending on whether the VDIC is receiving from a CSI ("AUTO") or from memory ("MAN"). Since the VDIC cannot receive from both CSI and memory at the same time, set or clear both field order bits to cover both cases. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-08gpu: ipu-v3: remove interrupt busy waiting routinePhilipp Zabel2-17/+0
This is not used anymore since commit eb8c88808c83 ("drm/imx: add deferred plane disabling"), remove it. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-08gpu: ipu-v3: allocate ipuv3_channels as neededPhilipp Zabel2-14/+17
Most of the 64 IPUv3 DMA channels are never used, some of them (channels 16, 30, 32, 34-39, and 53-63) are even marked as reserved. Allocate the channel control structure only when a channel is actually requested, replace the fixed size array with a list, and remove the unused enabled and busy fields from the ipuv3_channel structure. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-08gpu: ipu-v3: Add support for double read/write reductionPhilipp Zabel1-0/+6
Allow to skip writing odd chroma rows by setting the RDRW bit for 4:2:0 chroma subsampled formats for any IDMAC write channel. This also allows to skip reading odd rows for the VDIC read channel. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-08gpu: ipu-v3: prg: remove counter load enableLucas Stach1-2/+0
The counter load enable bit has no effect when the shadow register set is activated. As we always operate the PRG with shadow enabled it is safe to remove this. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-06gpu: ipu-v3: Fix CSI selection for VDICMarek Vasut1-7/+8
The description of the CSI_SEL bit in the i.MX6 reference manual is incorrect. It states "This bit defines which CSI is the input to the IC. This bit is effective only if IC_INPUT is bit cleared". From experiment it was found this is in fact not correct. The CSI_SEL bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC receives from in that case. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-06gpu: ipu-v3: pre: only use internal clock gatingLucas Stach1-8/+5
By setting the SFTRST bit, the PRE will be held in the lowest power state with clocks to the internal blocks gated. When external clock gating is used (from the external clock controller, or by setting the CLKGATE bit) the PRE will sporadically fail to start. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Fixes: d2a34232580a ("gpu: ipu-v3: add driver for Prefetch Resolve Engine") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-04-04gpu: ipu-v3: don't depend on DRM being enabledLucas Stach2-2/+9
The PRE/PRG drivers, which need the DRM infrastructure, are only used from the output path, so we skip building them into the ipu-v3 driver if CONFIG_DRM is not enabled. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-16gpu: ipu-v3: only set non-zero AXI ID for IC when PRG is absentLucas Stach1-1/+6
Using non-zero AXI IDs for anything other than the display channels collides with the PRG AXI snooping, so only do this if there is no PRG present. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-16gpu: ipu-v3: hook up PRG unitLucas Stach1-1/+10
The i.MX6 QuadPlus IPU needs to PRG unit to gain access to the data bus. Make sure it is present and available to be used. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-16gpu: ipu-v3: add driver for Prefetch Resolve GasketLucas Stach4-1/+432
This adds support for the i.MX6 QUadPlus PRG unit. It glues together the IPU and the PRE units. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> --- v4: add missing ipu_soc->prg_priv
2017-03-15gpu: ipu-v3: add driver for Prefetch Resolve EngineLucas Stach4-2/+320
This adds support for the i.MX6 QuadPlus PRE units. Currently only linear prefetch into SRAM is supported, other modes of operation like the tiled-to-linear conversion will be added later. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15gpu: ipu-v3: add support for separate alpha channelsPhilipp Zabel2-0/+63
The IPUv3 can read 8-bit alpha values from a separate IDMAC channel driven by the Alpha Transparency Controller (ATC) for the graphics IDMAC channels. This allows to reduce memory bandwidth via a conditional read mechanism or to support planar YUV formats with alpha transparency. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15drm/imx: add deferred plane disablingPhilipp Zabel1-3/+0
The DP (display processor) channel disable code tried to busy wait for the DP sync flow end interrupt status bit when disabling the partial plane without a full modeset. That never worked reliably, and it was disabled completely by the recent "gpu: ipu-v3: remove IRQ dance on DC channel disable" patch, causing ipu_wait_interrupt to always time out after 50 ms, which in turn would trigger a timeout in drm_atomic_helper_wait_for_vblanks. This patch changes ipu_plane_atomic_disable to only queue a DP channel register update at the next frame boundary and set a flag, which can be done without any waiting whatsoever. The imx_drm_atomic_commit_tail then calls a new ipu_plane_disable_deferred function that does the actual IDMAC teardown of the planes that are flagged for deferred disabling, after waiting for the vblank. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2017-03-15gpu: ipu-v3: add unsynchronised DP channel disablingPhilipp Zabel3-10/+17
When disabling the foreground DP channel during a modeset, the DC is already disabled without waiting for end of frame. There is no reason to wait for a frame boundary before updating the DP registers in that case. Add support to apply updates immediately. No functional changes, yet. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2017-03-15gpu: ipu-v3: remove IRQ dance on DC channel disableLucas Stach1-57/+4
This has never worked properly, as the IRQ got retriggered immediately on unmask. Remove the IRQ wait dance, as it is apparently safe to disable the DC channel at any point in time. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15gpu: ipu-cpmem: add bayer formats to ipu_cpmem_set_imagePhilipp Zabel1-0/+13
The IPU does not natively understand bayer formats, but it can pass them through unchanged. Add support for setting the image base address and cropping offset to ipu_cpmem_set_image. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15gpu: ipu-cpmem: set image base address even for incorrect formatsPhilipp Zabel1-2/+6
Otherwise, if the image base address is kept at zero, and if the user ignores the error return value, the IPU may be configured to write into the dma-apbh@00110000 region for large frames, which will lock up the system. Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-17gpu: ipu-v3: Stop overwriting pdev->dev.of_node of child devicesPhilipp Zabel1-6/+0
Setting dev->of_node changes the modalias and breaks module autoloading. Since there is an of_node field in the platform data passed to child devices, we don't even need this anymore. Suggested-by: Russell King <linux@armlinux.org.uk> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-02-17gpu: ipu-v3: export ipu_csi_set_downsizePhilipp Zabel1-0/+1
This function will be used by the media drivers and needs to be exported to allow them to be built as modules. Reported-by: Russell King <linux@armlinux.org.uk> Fixes: 867341b95891 ("gpu: ipu-v3: add ipu_csi_set_downsize") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-11-11Merge tag 'imx-drm-next-2016-11-10' of ↵Dave Airlie4-38/+30
git://git.pengutronix.de/git/pza/linux into drm-next imx-drm plane update cleanup, YUV formats - request modeset if plane offsets changed, only the plane base address can be changed without disabling the plane IDMAC channel. - cleanup of plane atomic_update - remove unused ipu_cpmem_set_yuv_planar function - support YUV 4:4:4, 4:2:2, NV12 and NV16 plane formats - not only mask interrupts during irq init, also clear them - remove a legacy check from imx-ldb - add support to set the CSI downsizing bits - silence an obnoxious warning during modeset * tag 'imx-drm-next-2016-11-10' of git://git.pengutronix.de/git/pza/linux: gpu: ipu-di: silence videomode logspam gpu: ipu-v3: add ipu_csi_set_downsize drm/imx: imx-ldb: remove unnecessary double disable check gpu: ipu-v3: initially clear all interrupts drm/imx: ipuv3-plane: add support for YUV 4:2:2 and 4:4:4, NV12, and NV16 formats gpu: ipu-v3: add YUV 4:4:4 support gpu: ipu-cpmem: remove unused ipu_cpmem_set_yuv_planar function drm/imx: ipuv3-plane: let drm_plane_state_to_ubo/vbo handle chroma subsampling other than 4:2:0 drm/imx: ipuv3-plane: merge ipu_plane_atomic_set_base into atomic_update drm/imx: ipuv3-plane: request modeset if plane offsets changed
2016-11-09gpu: ipu-di: silence videomode logspamLucas Stach1-1/+1
Adapting the videomode to the hardware constraints is something that can and must happen during normal operation and isn't something that the user can avoid. So printing a warning each time it happens isn't helpful. Demote this message to the debug level. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-11-07gpu: ipu-v3: add ipu_csi_set_downsizePhilipp Zabel1-0/+16
Support downsizing to 1/2 width and/or height in the CSI. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-11-07Backmerge tag 'v4.9-rc4' into drm-nextDave Airlie1-1/+1
Linux 4.9-rc4 This is needed for nouveau development.
2016-10-20gpu: ipu-v3: initially clear all interruptsPhilipp Zabel1-1/+4
If we want to stop resetting the IPU in the future, masking all interrupts before registering the irq handlers will not be enough to avoid spurious interrupts. We also have to clear them. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Liu Ying <gnuiyl@gmail.com>
2016-10-20gpu: ipu-v3: add YUV 4:4:4 supportPhilipp Zabel2-0/+9
The IDMAC does support reading and writing DRM_FORMAT_YUV444 and DRM_FORMAT_YVU444. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Liu Ying <gnuiyl@gmail.com>
2016-10-20gpu: ipu-cpmem: remove unused ipu_cpmem_set_yuv_planar functionPhilipp Zabel1-36/+0
ipu_cpmem_set_yuv_planar_full is only used directly, remove the wrapper. Suggested-by: Liu Ying <gnuiyl@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Liu Ying <gnuiyl@gmail.com>
2016-10-19gpu: Remove depends on RESET_CONTROLLER when not a providerStephen Boyd1-1/+0
These GPU drivers only depend on the RESET_CONTROLLER config option to fix build issues that existed when there weren't stub reset APIs for reset controller consumers. Given that these drivers aren't providing any reset controllers themselves, they don't actually depend on the API to build (just to function) so they don't need to depend on it. Remove the dependency to fix recursive build errors like the following: drivers/usb/Kconfig:39:error: recursive dependency detected! drivers/usb/Kconfig:39: symbol USB is selected by MOUSE_APPLETOUCH drivers/input/mouse/Kconfig:187: symbol MOUSE_APPLETOUCH depends on INPUT drivers/input/Kconfig:8: symbol INPUT is selected by VT drivers/tty/Kconfig:12: symbol VT is selected by FB_STI drivers/video/fbdev/Kconfig:674: symbol FB_STI depends on FB drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER drivers/gpu/drm/Kconfig:42: symbol DRM_KMS_FB_HELPER is selected by DRM_KMS_CMA_HELPER drivers/gpu/drm/Kconfig:98: symbol DRM_KMS_CMA_HELPER is selected by DRM_IMX drivers/gpu/drm/imx/Kconfig:1: symbol DRM_IMX depends on IMX_IPUV3_CORE drivers/gpu/ipu-v3/Kconfig:1: symbol IMX_IPUV3_CORE depends on RESET_CONTROLLER drivers/reset/Kconfig:4: symbol RESET_CONTROLLER is selected by USB_CHIPIDEA drivers/usb/chipidea/Kconfig:1: symbol USB_CHIPIDEA depends on USB_EHCI_HCD drivers/usb/host/Kconfig:84: symbol USB_EHCI_HCD depends on USB Cc: Arnd Bergmann <arnd@arndb.de> Cc: <dri-devel@lists.freedesktop.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Mark Yao <mark.yao@rock-chips.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: robdclark@gmail.com Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161018205719.20575-1-stephen.boyd@linaro.org
2016-10-17gpu: ipu-v3: Use ERR_CAST instead of ERR_PTR(PTR_ERR())Wei Yongjun1-1/+1
Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(...)). Generated by: scripts/coccinelle/api/err_cast.cocci Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-09-19gpu: ipu-v3: Add queued image conversion supportSteve Longerbeam4-1/+1725
This patch implements image conversion support using the IC tasks, with tiling to support scaling to and from images up to 4096x4096. Image rotation is also supported. Image conversion requests are added to a run queue under the IC tasks. The internal API is subsystem agnostic (no V4L2 dependency except for the use of V4L2 fourcc pixel formats). Callers prepare for image conversion by calling ipu_image_convert_prepare(), which initializes the parameters of the conversion. The caller passes in the ipu and IC task to use for the conversion, the input and output image formats, a rotation mode, and a completion callback and completion context pointer: struct ipu_image_converter_ctx * ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, struct ipu_image *in, struct ipu_image *out, enum ipu_rotate_mode rot_mode, ipu_image_converter_cb_t complete, void *complete_context); A new conversion context is created that is added to an IC task context queue. The caller is given the new conversion context, which can then be passed to the further APIs: int ipu_image_convert_queue(struct ipu_image_converter_run *run); This queues the given image conversion request run to a run queue, and starts the conversion immediately if the run queue is empty. Only the physaddr's of the input and output image buffers are needed, since the conversion context was created previously with ipu_image_convert_prepare(). When the conversion completes, the run pointer is returned to the completion callback. void ipu_image_convert_abort(struct ipu_image_converter_ctx *ctx); This will abort any active or pending conversions for this context. Any currently active or pending runs belonging to this context are returned via the completion callback with an error status. void ipu_image_convert_unprepare(struct ipu_image_converter_ctx *ctx); Unprepares the conversion context. Any active or pending runs will be aborted by calling ipu_image_convert_abort(). Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-09-19gpu: ipu-v3: Add ipu_rot_mode_is_irt()Steve Longerbeam1-1/+1
Add a macro that returns boolean true if the given ipu_rotate_mode requires the use of the Image Rotator. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-09-19gpu: ipu-v3: fix a possible NULL dereferenceLABBE Corentin1-3/+3
of_match_device could return NULL, and so cause a NULL pointer dereference later. For fixing this problem, we use of_device_get_match_data(), this will simplify the code a little by using a standard function for getting the match data. Testing the return value of of_device_get_match_data is also necessary for avoiding a second NULL deref later on devtype. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-29gpu: ipu-v3: Add FSU channel linking supportSteve Longerbeam2-0/+158
Adds functions to link and unlink source channels to sink channels in the FSU: int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch); int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch); The channels numbers are usually IDMAC channels, but they can also be channels that do not transfer data to or from memory. The following convenience functions can be used in place of ipu_fsu_link/unlink() when both source and sink channels are IDMAC channels: int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink); int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink); So far the following links are supported: IPUV3_CHANNEL_IC_PRP_ENC_MEM -> IPUV3_CHANNEL_MEM_ROT_ENC PUV3_CHANNEL_IC_PRP_VF_MEM -> IPUV3_CHANNEL_MEM_ROT_VF IPUV3_CHANNEL_IC_PP_MEM -> IPUV3_CHANNEL_MEM_ROT_PP IPUV3_CHANNEL_CSI_DIRECT -> IPUV3_CHANNEL_CSI_VDI_PREV More links can be added to the fsu_link_info[] array. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-29gpu: ipu-v3: Add Video Deinterlacer unitSteve Longerbeam4-1/+261
Adds the Video Deinterlacer (VDIC) unit. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-29gpu: ipu-v3: Do not wait for DMFC FIFO to clear when disabling DMFC channelLiu Ying1-17/+1
According to basic tests, it looks there is no issue if we don't wait for DMFC FIFO to clear when disabling DMFC channel. NXP BSP doesn't do that, either. This patch is needed to avoid the annoying warning caused by a timeout on waiting for the FIFO to clear after we add the new DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET flag to the imx-drm driver which changes the procedure to disable display channel slightly. Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: David Airlie <airlied@linux.ie> Cc: Russell King <linux@armlinux.org.uk> Cc: Peter Senna Tschudin <peter.senna@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Liu Ying <gnuiyl@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08gpu: ipu-v3: rename CSI client deviceSteve Longerbeam1-2/+2
Rename the CSI client device in the client_reg[] table to "imx-ipuv3-csi". Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08gpu: ipu-v3: Fix IRT usageSteve Longerbeam1-9/+31
There can be multiple IC tasks using the IRT, so the IRT needs a separate use counter. Create a private ipu_irt_enable() to enable the IRT module when any IC task requires rotation, and ipu_irt_disable() when a task no longer needs the IRT. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08gpu: ipu-v3: Fix CSI data format for 16-bit media bus formatsSteve Longerbeam1-5/+1
The CSI data format was being programmed incorrectly for the 1x16 media bus formats. The CSI data format for 16-bit must be bayer/generic (CSI_SENS_CONF_DATA_FMT_BAYER). Suggested-by: Carsten Resch <Carsten.Resch@de.bosch.com> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08gpu: ipu-v3: set correct full sensor frame for PAL/NTSCSteve Longerbeam1-7/+13
Set the sensor full frame based on whether the passed in mbus_fmt is 720x480 (NTSC) or 720x576 (PAL). Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08gpu: ipu-v3: Add ipu_get_num()Steve Longerbeam2-0/+9
Adds of-alias id to ipu_soc and retrieve with ipu_get_num(). Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()Steve Longerbeam1-0/+6
Adds ipu_cpmem_get_burstsize(). Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-08gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()Steve Longerbeam1-0/+7
Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-12gpu: ipu-v3: ipu-dc: don't bug out on invalid bus_formatPhilipp Zabel1-3/+3
If imx-drm is combined with a bridge or panel that requests an unsupported format, warn and use a default mapping instead of hanging the machine. The worst that can happen here are wrong colors. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-12drm/imx: atomic phase 1: Use transitional atomic CRTC and plane helpersLiu Ying2-7/+1
Use the drm_plane_helper_update/disable() and drm_helper_crtc_mode_set() transitional atomic helpers. The crtc->mode_set_nofb callback is added so that the primary plane is no longer tied to the CRTC. Check/update logics are separated to make sure crtc->mode_set_nofb and plane->atomic_update are always successful. Also, some necessary logics are tweaked for a smooth transition. Signed-off-by: Liu Ying <gnuiyl@gmail.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-12gpu: ipu-v3: ipu-dmfc: Use static DMFC FIFO allocation mechanismLiu Ying1-206/+7
For all video modes we support currently, we always get 2 slots for a plane by using the current existing dynamic DMFC FIFO allocation mechanism. So, let's change to use the static one to simplify the code. This also makes it easier to implement the atomic mode setting as we don't need to handle allocation failure cases then. Signed-off-by: Liu Ying <gnuiyl@gmail.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-05-23drm/imx: Match imx-ipuv3-crtc components using device node in platform dataPhilipp Zabel1-2/+3
The component master driver imx-drm-core matches component devices using their of_node. Since commit 950b410dd1ab ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading"), the imx-ipuv3-crtc dev->of_node is not set during probing. Before that, of_node was set and caused an of: modalias to be used instead of the platform: modalias, which broke module autoloading. On the other hand, if dev->of_node is not set yet when the imx-ipuv3-crtc probe function calls component_add, component matching in imx-drm-core fails. While dev->of_node will be set once the next component tries to bring up the component master, imx-drm-core component binding will never succeed if one of the crtc devices is probed last. Add of_node to the component platform data and match against the pdata->of_node instead of dev->of_node in imx-drm-core to work around this problem. Cc: <stable@vger.kernel.org> # 4.4.x Fixes: 950b410dd1ab ("gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Lothar Waßmann <LW@KARO-electronics.de> Tested-by: Heiko Schocher <hs@denx.de> Tested-by: Chris Ruehl <chris.ruehl@gtsys.com.hk>
2016-05-05gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloadingPhilipp Zabel1-1/+6
If of_node is set before calling platform_device_add, the driver core will try to use of: modalias matching, which fails because the device tree nodes don't have a compatible property set. This patch fixes imx-ipuv3-crtc module autoloading by setting the of_node property only after the platform modalias is set. Fixes: 304e6be652e2 ("gpu: ipu-v3: Assign of_node of child platform devices to corresponding ports") Reported-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-By: Dennis Gilmore <dennis@ausil.us> Cc: stable@vger.kernel.org # 4.4+ Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-03-31gpu: ipu-v3: ipu-dmfc: Rename ipu_dmfc_init_channel to ipu_dmfc_config_wait4eotLiu Ying1-2/+2
The function name 'ipu_dmfc_config_wait4eot' matches the implementation of the function better than 'ipu_dmfc_init_channel', since it only touches the wait4eot bits. Signed-off-by: Liu Ying <gnuiyl@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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